SANDBRIDGE TECHNOLOGIES, INC.
|SANDBRIDGE TECHNOLOGIES, INC. Patent applications|
|Patent application number||Title||Published|
|20100299319||METHOD, APPARATUS, AND ARCHITECTURE FOR AUTOMATED INTERACTION BETWEEN SUBSCRIBERS AND ENTITIES - A method for interaction between a subscriber and an entity includes determining a current locus and acquiring change in status information for a subscriber. Preference information, for one or more searchable parameters selected by the subscriber, and association information, for one ore more contacts made by the subscriber, are acquired. First and second strength information is then acquired. First strength information pertains to the subscriber's affinity for the preference information and second strength information encompasses the subscriber's affinity for the association information. Responsive to the change in status information, a group of first entities is selected. First entity information about the group of first entities is then generated. The current locus information, the preference information, the association information, the first strength information, and the second strength information are correlated with the first entity information to produce correlation information. Finally, the correlation information is provided to the subscriber to be displayed.||11-25-2010|
|20100293210||SOFTWARE IMPLEMENTATION OF MATRIX INVERSION IN A WIRELESS COMMUNICATION SYSTEM - A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.||11-18-2010|
|20100241834||METHOD OF ENCODING USING INSTRUCTION FIELD OVERLOADING - The method selects registers by a register instruction field having x bits. A first group of registers has up to 2||09-23-2010|
|20100228938||METHOD AND INSTRUCTION SET INCLUDING REGISTER SHIFTS AND ROTATES FOR DATA PROCESSING - A method includes identifying a first register with M bits and a second register with N bits. The process also includes shifting K bits, where K<=N, from the second register into the first register. The shifting operation executes a left shift operation including reading bits K . . . N−1 from the first register, writing bits K . . . N−1 into bit positions O . . . N−K−1 of the first register, reading K bits from the second register, and writing K bits from second register into bit positions N−K . . . N−1 of first register, or a right shift operation including reading bits O . . . N−K−1 from the first register, writing bits O . . . N−K−1 into bit position K . . . N−1 of the first register, reading the K bits from the second register, and writing K bits from second register into bit positions O . . . K−1 of first register.||09-09-2010|
|20100115527||METHOD AND SYSTEM FOR PARALLELIZATION OF PIPELINED COMPUTATIONS - A method of parallelizing a pipeline includes stages operable on a sequence of work items. The method includes allocating an amount of work for each work item, assigning at least one stage to each work item, partitioning the at least one stage into at least one team, partitioning the at least one team into at least one gang, and assigning the at least one team and the at least one gang to at least one processor. Processors, gangs, and teams are juxtaposed near one another to minimize communication losses.||05-06-2010|
|20100031007||METHOD TO ACCELERATE NULL-TERMINATED STRING OPERATIONS - A method reads and compares first and second register values, each with a size of at least two bytes. A third register indicates a match if: (1) a byte in the first register value is equal to (or, alternatively, not equal to) a corresponding byte in the second register value, or (2) if a byte in the first register value is zero. Next, a fourth register value is set to one of the following: (1) a count of the matching byte, if the corresponding bytes in the first and second register values are equal (or, alternatively, are not equal), or (2) a number outside of a range between 0 and n−1, if the corresponding bytes in the first and second register values are not equal (or, alternatively, are equal). The value, n, is an integer equal to the number of bytes in the first and second register values.||02-04-2010|
|20090193279||METHOD FOR ENABLING MULTI-PROCESSOR SYNCHRONIZATION - A method for providing at least one sequence of values to a plurality of processors is described. In the method, a sequence generator from one or more sequence generators is associated with a memory location. The sequence generator is configured to generate the at least one sequence of values. One or more read accesses of the memory location are enabled by a processor from the plurality of processors. In response to enabling the read access, the sequence generator is executed so that it returns a first value from the sequence of values to the processor. After executing the sequence generator, the sequence generator is advanced so that the next access generates a second value from the sequence of values. The second value is sequentially subsequent to the first value.||07-30-2009|
|20090160518||METHOD IMPLEMENTING PERIODIC BEHAVIORS USING A SINGLE REFERENCE - A method for processing information is described. The method includes providing a phase reference, Φ||06-25-2009|
|20090079658||Microstrip Multi-Band Composite Antenna - The multi-band antenna structure includes a first antenna having a band width about a middle frequency and a second antenna spaced and electrically isolated from the antenna. Ends of the second antenna are shorted to each other and the antenna floats electrically. The first and second antennas are planar and superimposed in parallel planes. At least two layers of dielectric material of a thickness is between the two antennas. A third layer of dielectric material of a third thickness is between the two antennas.||03-26-2009|
|20080239940||Method of QAM Soft Demapping - A method of demapping in a receiver including deriving M intermediate soft bit values y||10-02-2008|
Patent applications by SANDBRIDGE TECHNOLOGIES, INC.