# SAANKHYA LABS PVT LTD

SAANKHYA LABS PVT LTD Patent applications | ||

Patent application number | Title | Published |
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20120254274 | Index Generation Scheme for Prime Factor Algorithm Based Mixed Radix Discrete Fourier Transform (DFT) - In one embodiment, a processor performs a method of generating pipelined data read indexes and data write indexes for a Prime Factor Algorithm (PFA) Discrete Fourier Transform (DFT) without look-up tables. The processor is adapted to factorize an āNā point PFA DFT into one or more mutually prime factors and zero or more non-prime factors, calculate a 0th column index for an ith row (Xi0), calculate an IndCor when the value of Xi0 equals zero and when a row number (i) does not equal zero, calculate Xij, generate the data read indexes, perform a DFT kernel computation on Lk point for the mutually prime factors and the non-prime factors, and generate the data write indexes for the mutually prime factors and the non-prime factors. Xij represents ith row and jth column of 2D input Buffer and enables a selection of a linear index from the 2D input buffer. | 10-04-2012 |

20120250807 | SCHEMES FOR DETECTING GUARD INTERVALS IN OFDM SYSTEM - A receiver and method of detecting a guard interval estimate accurately by performing an Nth order polynomial based non-linear quantization on a pre-estimated guard interval in a received Orthogonal Frequency Division Multiplexing (OFDM) signal in a receiver is provided. The pre-estimated guard interval is obtained by performing normalized auto-correlation on the received OFDM signal. The method includes (i) performing a rounding operation on (a) one or more m | 10-04-2012 |

20120250799 | BLIND SYMBOL SYNCHRONIZATION SCHEME FOR OFDM SYSTEM - An Orthogonal Frequency Division Multiplexing (OFDM) receiver system for improved pilotless detection of symbol boundary of a received OFDM symbols using M-ary Phase Shift Keying (M-PSK) modulated carriers as a cost function is provided. The OFDM receiver includes a symbol boundary detection block that detects a symbol boundary of the received OFDM symbols. The symbol boundary detection block detects the symbol boundary by computing cost function of second order moment of the M-PSK modulated carriers. The receiver system is capable of detecting the symbol boundary for unknown information on said received OFDM symbols and thus increases throughput per given transmission bandwidth of a modulation scheme. | 10-04-2012 |

20120250750 | METHOD AND SYSTEM FOR RELIABLE CFO AND STO ESTIMATION IN THE PRESENCE OF TUNER INDUCED IMPAIRMENT - A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation. | 10-04-2012 |

20120249887 | System and Method to Reduce Channel Acquisition and Channel Switch Timings in Communication Receivers - A Television (TV) receiver for faster channel switch times between a plurality of broadcasting TV channels with reduced latency in overall demodulation cycle for multiple demodulation standards is provided. The TV receiver includes a tuner that receives the broadcasting TV channels from a broadcasting system, performs a tuning operation, and sets a desired frequency for each of the broadcasting TV channels during a channel scan operation. A demodulator demodulates each of the broadcasting TV channels and acquires one or more acquisition channel parameters of each of the broadcasting TV channels during the channel scan operation. An application processor is coupled to the demodulator via a low throughput interface. The application processor performs a read operation and a write operation of the acquisition channel parameters to memory mapped registers on the demodulator when a channel status switches from a first state to a second state. | 10-04-2012 |

20100211858 | Scalable VLIW Processor For High-Speed Viterbi and Trellis Coded Modulation Decoding - An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions. | 08-19-2010 |

20100211762 | Mechanism for Efficient Implementation of Software Pipelined Loops in VLIW Processors - A system to implement a zero overhead software pipelined (SFP) loop includes a Very Long Instruction Word (VLIW) processor having an N number of execution slots. The VLIW processor executes a plurality of instructions in parallel without any limitation of an instruction buffer size. A program memory receives a Program Memory address to fetch an instruction packet. The program memory is closely coupled with the instruction buffer size to implement the zero overhead software pipelined (SFP) loop. The size of the zero overhead software pipelined (SFP) loop can exceed the instruction buffer size. A CPU control register includes a block count and an iteration count. The block count is loaded into a block counter and counts the plurality of instructions executed in the SFP loop, and the iteration count is loaded into an iteration counter and counts a number of iterations of the SFP loop based on the block count. | 08-19-2010 |