| Renesas Electronics Corporation Patent applications |
| Patent application number | Title | Published |
|---|
| 20120135611 | METHOD OF MANUFACTURING POROUS INSULATING FILM - A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group. | 05-31-2012 |
| 20120135275 | MAGNETIC MEMORY INCLUDING MEMORY CELLS INCORPORATING DATA RECORDING LAYER WITH PERPENDICULAR MAGNETIC ANISOTROPY FILM - A magnetic memory includes: a magnetization fixed layer having perpendicular magnetic anisotropy, a magnetization direction of the magnetization fixed layer being fixed; an interlayer dielectric; an underlayer formed on upper faces of the magnetization fixed layer and the interlayer dielectric; and a data recording layer formed on an upper face of the underlayer and having perpendicular magnetic anisotropy. The underlayer includes: a first magnetic underlayer; and a non-magnetic underlayer formed on the first magnetic underlayer. The first magnetic underlayer is formed with such a thickness that the first magnetic underlayer does not exhibit in-plane magnetic anisotropy in a portion of the first magnetic underlayer formed on the interlayer dielectric. | 05-31-2012 |
| 20120134601 | Image compression device, image compression method, and image compression program - A high-frequency integrator acquires a first integrated value by integrating a high-frequency component of first image data. A corrector handles second image data, which is obtained when an image processor subjects the first image data to an image process affecting frequency characteristics, and acquires a second integrated value by correcting the first integrated value acquired by the high-frequency integrator in accordance with a change in the frequency characteristics that is brought about by the image process. An encoder calculates, in accordance with the second integrated value acquired by the corrector, a quantization scale for compressing the second image data acquired by the image processor to a predefined number of bytes at once, and compresses the second image data accordingly. | 05-31-2012 |
| 20120134444 | Semiconductor Device Having First and Second Demodulation Circuits for Wireless Communication - A device receives ASK signals by using an ASK signal receiving circuit that is different from an ASK signal receiving circuit for R/W mode, when an NFC-enabled semiconductor device operates in a mode other than the R/W mode. An ASK signal receiving circuit for 100% ASK is provided on the side of a pair of transmitting terminals. This arrangement eliminates the influence of an ESD provided within an ASK signal receiving circuit for 10% ASK coupled to a pair of receiving terminals. There is no need for management of threshold values that are different according to type of ASK and it is possible to support different modulation schemes by a smaller circuit configuration. | 05-31-2012 |
| 20120133810 | SOLID STATE IMAGING DEVICE - A solid state imaging device has a semiconductor substrate, a light receiving region provided on a surface layer on a first surface side of the semiconductor substrate, the light receiving region having a silicided surface, second impurity diffusion layer provided adjacent to the light receiving region on the surface layer on the first surface side of the semiconductor substrate, a gate insulating film provided adjacent to the second impurity diffusion layer on the first surface of the semiconductor substrate, a gate electrode provided on the gate insulating film, and a third impurity diffusion layer provided on an opposite side to the second impurity diffusion layer, with the gate insulating film and the gate electrode sandwiched. | 05-31-2012 |
| 20120133438 | DIFFERENTIAL AMPLIFIER AND DATA DRIVER - A differential amplifier has an interpolating function and has: first and second differential pairs including transistors of a first conductivity type; third and fourth differential pairs including transistors of a second conductivity type; first and second current sources providing operating currents to the first and second differential pairs; third and fourth current sources providing operating currents to the third and fourth differential pairs; a first control circuit which controls, in a first operating range where the amounts of currents flowing through the first and second differential pairs become smaller, respectively, a changing point at which the operating current of the first differential pair changes; and a second control circuit which controls, in a second operating range where the amounts of currents flowing through the third and fourth differential pairs become smaller, respectively, a changing point at which the operating current of the fourth differential pair changes. | 05-31-2012 |
| 20120133431 | POWER AMPLIFICATION CIRCUIT HAVING TRANSFORMER - In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted. | 05-31-2012 |
| 20120133407 | SEMICONDUCTOR INTEGRATED CIRCUIT - An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks. | 05-31-2012 |
| 20120133291 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF - A DC-DC converter supplies an output voltage to a plurality of channels of a light emitting device array in common. A current driver has a plurality of driver units which drive the channels. Each of the driver units includes a drive transistor and a detector which detects an abnormality of a drive current. A logic unit generates digital data in response to a plurality of detection signals and supplies the same to a D/A converter. An analog reference voltage of the D/A converter is supplied to the DC-DC converter. The logic unit executes a calibration operation which determines digital data for setting the minimum output DC voltage at the normal operation of all the channels by sequential updating of the digital data. | 05-31-2012 |
| 20120133055 | Semiconductor chip and semiconductor device - A semiconductor chip capable of realizing reduction in cost when the semiconductor chip is mounted over a package substrate, miniaturization of the package substrate, and optimization of an interconnect pattern. The semiconductor chip includes a first electrode pad group provided in the semiconductor chip, and comprised of at least one electrode pad, and a second electrode pad group provided in the semiconductor chip, and comprised of at least one other electrode pad capable of outputting a signal identical to a signal outputted by the one electrode pad. Further, either the one electrode pad of the first electrode pad group, or the one other electrode pad of the second electrode pad group, closer in distance to one other electrode pad of one other semiconductor chip is coupled to the one other electrode pad of the one other semiconductor chip. | 05-31-2012 |
| 20120133045 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 05-31-2012 |
| 20120133035 | TCP-TYPE SEMICONDUCTOR DEVICE AND METHOD OF TESTING THEREOF - A semiconductor device includes a base film, a semiconductor chip mounted on the base film, and a plurality of leads formed on the base film, each of the leads including one end coupled to the semiconductor chip and another end being opposite to the one end. The another end of a first one of the leads and the another end of a second one of the leads are located at different positions respectively between the semiconductor chip and a cut line along which the base film is cut. | 05-31-2012 |
| 20120131410 | ERROR CORRECTION CODE DECODING DEVICE - An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other. | 05-24-2012 |
| 20120129307 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The present invention provides a technique capable of attaining an improvement in current detection accuracy in a trench gate type power MISFET equipped with a current detection circuit. Inactive cells are disposed so as to surround the periphery of a sense cell. That is, the inactive cell is provided between the sense cell and an active cell. All of the sense cell, active cell and inactive cells are respectively formed of a trench gate type power MISFET equipped with a dummy gate electrode. At this time, the depth of each trench extends through a channel forming region and is formed up to the deep inside (the neighborhood of a boundary with a semiconductor substrate) of an n-type epitaxial layer. Further, a p-type semiconductor region is provided at a lower portion of each trench. The p-type semiconductor region is formed so as to contact the semiconductor substrate. | 05-24-2012 |
| 20120127446 | LIGHT EXPOSURE METHOD, AND LIGHT EXPOSURE APPARATUS - There is provided an EUV exposure apparatus which restrains its optical systems or a mask used therein from being polluted by contaminations generated in its chamber. An energy beam generating source is arranged near a wafer stage set in the chamber of the EUV exposure apparatus to decompose an emission gas generated from a resist painted on the front surface of a wafer by an energy beam. In this manner, lightening mirrors configuring a lightening optical system as one of the optical systems, projection mirrors configuring a projection optical system as another of the optical systems, the mask, and others are protected from being polluted by contaminations. | 05-24-2012 |
| 20120127343 | Audio processing device, audio processing method, program, and audio acquisition apparatus - In an audio-accompanying moving-image taking apparatus, a noise period setting unit sets a second period with respect to an audio signal acquired by image-taking. The second period is a period between the endpoint of a first period which is a predetermined period starting from the timing when a drive instruction is made to a drive unit for driving a lens and the point in time when the drive unit stops driving according to the drive instruction. A noise level estimation unit estimates a noise level using the signal present in the second period set by the noise period setting unit. A noise suppression unit suppresses noise from the signal present in the second period using the noise level estimated by the noise estimation unit. | 05-24-2012 |
| 20120127188 | IMAGE PROCESSING CIRCUIT, AND DISPLAY PANEL DRIVER AND DISPLAY DEVICE MOUNTING THE CIRCUIT - A display panel driver includes a compression circuit configured to, when receiving image data of a plurality of pixels of a target block, generate compressed image data corresponding to the target block by compressing the image data, an image memory configured to store the compressed image data, a decompression circuit configured to generate decompressed image data by decompressing the compressed image data reading from the image memory, and a drive circuit configured to drive a display panel in response to the decompressed image data. The number of bits of the compression type recognition bit of the compressed image data becomes low, when the correlation between the image data of the plurality of pixels becomes low. | 05-24-2012 |
| 20120127138 | Output circuit, data driver, and display device - An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit, input and output terminals, and first to third supply terminals applied with first to third supply voltages, respectively. The third supply voltage is set a voltage between the first and second supply voltages. The differential amplifier circuit differentially receives signals of the input and output terminals. The output amplifier circuit includes first and second transistors of different conduction type each other coupled in series between the first and third supply terminals via the output terminal, and having control terminals coupled to first and second output nodes of the differential amplifier circuit, respectively. The control circuit includes a third transistor and a switch, and controls the third transistor being in a diode coupling mode between the first supply terminal and the control terminal of the first transistor for a given period of the output period. | 05-24-2012 |
| 20120126915 | ATTENUATOR - An attenuator includes a first terminal, a second terminal, a first circuit coupled between the first and second terminals and including a field effect transistor including a gate terminal coupled to a resistor, a second circuit coupled between the first circuit and the second terminal, coupled to the first circuit via a node, and including another field effect transistor including another gate terminal coupled to another resistor, and a third circuit coupled to the node. The resistor and the another resistor are coupled to different nodes respectively. | 05-24-2012 |
| 20120126894 | DIFFERENTIAL AMPLIFIER - A differential amplifier includes first and second current paths, each connected between first and second power supplies (PS) and respectively outputting first and second differential output signals. The first current path includes: first transistor, selectively interconnected between the first PS and a first output terminal, its gate receiving one differential input signal; second transistor, connected between the second PS and the first output terminal, its gate receiving the other differential input signal; and first switch circuit. The second current path includes: third transistor, selectively interconnected between the second PS and a second output terminal, its gate receiving one differential input signal; fourth transistor, connected between the first PS and the second output terminal, its gate receiving the other differential input signal; and second switch circuit. One of the first and second switch circuits is connected to the first PS and the other is connected to the second PS. | 05-24-2012 |
| 20120126769 | VOLTAGE BOOSTING/LOWERING CIRCUIT AND VOLTAGE BOOSTING/LOWERING CIRCUIT CONTROL METHOD - A voltage boosting/lowering circuit according to an aspect of the present invention includes an output voltage generation circuit | 05-24-2012 |
| 20120126633 | Power supply switch circuit - A power supply switch circuit according to an aspect of the present invention includes a first switch element that is connected between a first power supply line and a second power supply line and switches connection and disconnection between the first power supply line and the second power supply line according to a first enable signal; a second switch element that is connected between the first power supply line and the second power supply line and switches connection and disconnection between the first power supply line and the second power supply line; and a switch control circuit that includes at least one logic gate supplied with power from the second power supply line and controls the second switch element. The switch control circuit controls the second switch element based on a second enable signal supplied to the switch control circuit and on a voltage of the second power supply line. | 05-24-2012 |
| 20120126404 | SEMICONDUCTOR DEVICE - In a semiconductor device comprising a semiconductor chip, electrodes formed on the major surface of the semiconductor chip, and a wiring board for mounting the semiconductor chip, for example, wirings for electrically connecting the wirings of the wiring board to the electrodes are provided. As the wirings, those relaxing stress generated between the semiconductor chip and the wiring board are used. | 05-24-2012 |
| 20120126316 | SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device, that buried gate electrodes are formed in a pair of trenches in a substrate, so as to be recessed from the level of the top end of the trenches, a base region is formed between a predetermined region located between the pair of trenches, and a source region is formed over the base region. | 05-24-2012 |
| 20120126288 | Semiconductor device and method of manufacturing the same - A semiconductor device having first and second stacks formed successively over a common substrate, in which the first stack that remains after removing the second stack comprises a field effect transistor, the second stack that is stacked over the first stack comprises a device different from the field effect transistor, and the first stack comprising the field effect transistor has an etching stopper layer that defines a stopping position of a recess formed in the first stack and comprises InGaP, a lower compound semiconductor layer that is disposed below a gate electrode disposed in the recess and comprises AlGaAs, and a spacer layer that is interposed between the etching stopper layer and the lower compound semiconductor layer for preventing phosphorus contained in the etching stopper layer from thermally diffusing as far as the lower compound semiconductor layer and chemically bonding with constituents elements of the lower compound semiconductor layer. | 05-24-2012 |
| 20120124278 | MEMORY SYSTEM FOR PORTABLE TELEPHONE - A memory system is constituted of a file storage flash memory storing a control program required for a control portion and a large amount of data, and a random access memory storing a program used by the control portion and functioning as a buffer memory for received data. Thus, a memory system for a portable telephone capable of storing a large amount of received data at high-speed and allowing reading of the stored data at high-speed is provided. | 05-17-2012 |
| 20120122393 | COMMUNICATION DEVICE - A communication device includes a transmission signal processing unit, a driver amplifier coupled to the transmission signal processing unit, a selector coupled to the driver amplifier, a first attenuator coupled to the selector and an output portion of the communication device, a second attenuator coupled to the selector and the output portion of the communication device, and a controller coupled to the selector and the driver amplifier to switch between the first attenuator and the second attenuator based on a notification signal. | 05-17-2012 |
| 20120122246 | METHOD FOR MANUFACTURING MAGNETIC MEMORY CHIP DEVICE - A method for manufacturing a magnetic memory chip device comprises the steps of: writing information in each of a plurality of magnetic memory chips formed on a silicon wafer; adhering a high magnetic permeability plate on a back face of the silicon wafer after writing information, the high magnetic permeability plate having a higher magnetic permeability than silicon and having a thickness of 50 um or more; dicing the silicon wafer into respective magnetic memory chips after adhering the high magnetic permeability plate. | 05-17-2012 |
| 20120119826 | Semiconductor integrated circuit for minimizing a deviation of an internal power supply from a desired value - A semiconductor integrated circuit includes first and second external terminals receiving an external power supply voltage, an internal power supply line coupling to the first and second external terminals, a first transistor coupling between the first external terminal and the internal power supply line, a second transistor that is coupled between the second external terminal and the internal power supply line, a first monitor line coupling to a first node of the internal power supply line, a second monitor line coupling to a second node of the internal power supply line, the second node being different from the first node, and a controller coupling to the first and second monitor lines, the controller outputs a control signal corresponding to potentials of the first and second monitor lines to the first and second transistors. | 05-17-2012 |
| 20120119808 | SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD THEROF - An integrated circuit is equipped with a reception mixer and a signal generator. A multistage delay circuit generates a plurality of clock pulses in response to a reception carrier signal. A phase detection unit detects differences between a voltage level of a specific clock pulse and voltage levels of a predetermined number of clock pulses generated prior to the specific clock pulse to thereby detect a predetermined phase of the specific clock pulse. A selector of a clock generation unit outputs a plurality of selection clock pulse signals respectively having a plurality of phases from the clock pulse signals. A first signal synthetic logic circuit performs logical operations on the selection clock pulses to thereby generate local signals supplied to the reception mixer. | 05-17-2012 |
| 20120119338 | Semiconductor Device And Method Of Manufacturing Semiconductor Device - A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion. | 05-17-2012 |
| 20120115324 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A REFRACTORY METAL CONTAINING FILM - A semiconductor device and a method for manufacturing the same of the present invention in which the semiconductor device is provided with a fuse structure or an electrode pad structure, suppress the copper blowing-out from a copper containing metal film. The semiconductor device comprises a silicon substrate, SiO | 05-10-2012 |
| 20120115253 | Semiconductor apparatus - A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material. | 05-10-2012 |
| 20120113731 | SEMICONDUCTOR SIGNAL PROCESSING DEVICE - A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage SOI transistors is singly connected to the read port. Therefore, an AND operation result or a NOT operation result of data stored in the unit operator cells can be obtained, and operation processing can be performed only by writing and reading data. A semiconductor signal processing device that can perform logic operation processing and arithmetic operation processing at high speed is implemented with low power consumption and a small occupation area. | 05-10-2012 |
| 20120113709 | Semiconductor Integrated Circuit Device with Reduced Leakage Current - The gate tunnel leakage current is increased in the up-to-date process, so that it is necessary to reduce the gate tunnel leakage current in the LSI which is driven by a battery for use in a cellular phone and which needs to be in a standby mode at a low leakage current. In a semiconductor integrated circuit device, the ground source electrode lines of logic and memory circuits are kept at a ground potential in an active mode, and are kept at a voltage higher than the ground potential in an unselected standby mode. The gate tunnel leakage current can be reduced without destroying data. | 05-10-2012 |
| 20120113552 | SEMICONDUCTOR INTEGRATED CIRCUIT - An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized. | 05-10-2012 |
| 20120112843 | SEMICONDUCTOR INTEGRATED CIRCUIT - A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop. | 05-10-2012 |
| 20120112838 | RF POWER AMPLIFIER AND RF POWER MODULE USING THE SAME - The RF power amplifier circuit including multiple amplification stages has a previous-stage amplifier, a next-stage amplifier and a controller. The previous-stage amplifier responds to an RF transmission input signal. The next-stage amplifier responds to an amplification signal output by the previous-stage amplifier. In response to an output-power-control voltage, the controller controls the former- and next-stage amplifiers in quiescent current and gain. In response to the output-power-control voltage, the quiescent current and gain of the previous-stage amplifier are continuously changed according to a first continuous function, whereas those of the next-stage amplifier are continuously changed according to a second continuous function. The second continuous function is higher than the first continuous function by at least one in degree. The RF power amplifier circuit brings about the effect that the drop of the power added efficiency in low and middle power modes is relieved. | 05-10-2012 |
| 20120112836 | OPERATIONAL AMPLIFIER - An operational amplifier includes a differential amplifier input stage that supplies an operating current to a differential pair, the differential amplifier input stage including a first transistor having a first polarity, a push-pull amplifier output stage that includes a second transistor having the first polarity, and a third transistor having a second polarity, the second transistor and the third transistor being connected in series, a first capacitive element that connects a gate of the first transistor and a gate of the second transistor, and a second capacitive element that connects the gate and a drain of the first transistor. | 05-10-2012 |
| 20120110505 | AUTOMATIC UPDATING APPARATUS, AUTOMATIC UPDATING METHOD, AND PROGRAMMABLE STORAGE MEDIUM EMBODYING PROGRAM TO PERFORM METHOD FOR AUTOMATIC UPDATING - An automatic updating apparatus includes a traffic receiver that receives numbers per unit time of the access of more than one menu displayed in a screen and calculates rates of variability with respect to the numbers of the access to each menu, and a menu updating unit that updates a menu display in the screen based on the rates of variability. | 05-03-2012 |
| 20120110268 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The data processing apparatus according to an embodiment of the present invention includes: a first processor; a second processor; and an external RAM to/from which the first processor writes/reads data, the first processor including a cache memory for storing data used in the first processor in association with an address on the external RAM, and the data being written to the cache memory by the second processor not through the external RAM. | 05-03-2012 |
| 20120108055 | MANUFACTURING PROCESS OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate. | 05-03-2012 |
| 20120108013 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating. | 05-03-2012 |
| 20120106219 | SEMICONDUCTOR DEVICE FOR WIRELESS COMMUNICATION - Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors. | 05-03-2012 |
| 20120106110 | HYBRID INTEGRATED CIRCUIT DEVICE, AND METHOD FOR FABRICATING THE SAME, AND ELECTRONIC DEVICE - A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals. | 05-03-2012 |
| 20120105155 | PULSE WIDTH MODULATION CIRCUIT AND VOLTAGE-FEEDBACK CLASS-D AMPLIFIER CIRCUIT - The frequency characteristic of a voltage-feedback class-D amplifier circuit for driving an output load is improved. A triangular-wave correction circuit which compensates a gradient of a triangular wave is provided to a triangular-wave signal generator which supplies a triangular wave signal used as a PWM carrier to a comparison circuit for performing PWM modulation of an input signal. In an area where a duty of a command value for an output circuit drive becomes about 50%, a slew rate (gradient) of the triangular wave is decreased. | 05-03-2012 |
| 20120104636 | METHOD OF MANUFACTURING AN OPTICALLY COUPLED DEVICE - An optically coupled device includes a light emitting element and a light receiving element which are electrically isolated from each other, and an optical waveguide allowing therethrough transmission of light from the light emitting element to the light receiving element, wherein the optical waveguide is covered with an encapsulation resin containing a light reflective inorganic particle which is typically composed of titanium oxide, the light emitting element and the light receiving element are respectively provided on a base (for example, package terminals), and the entire portion of the outer surface of the optical waveguide, brought into contact with none of the light emitting element, the light receiving element and the base, is covered with the encapsulation resin. | 05-03-2012 |
| 20120104614 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A semiconductor device manufacturing method which prevents the resistance of a Ni silicide layer from increasing due to an additive element. First, a reaction control layer which contains a metallic element with an atomic number greater than Ni and does not contain Ni is formed over a silicon layer. Then, Ni is deposited over the reaction control layer and the silicon layer, reaction control layer and Ni are heat-treated to form a Ni silicide layer in the silicon layer. It is preferable that the reaction control layer be comprised of a metallic element with an atomic number greater than Ni. | 05-03-2012 |
| 20120104560 | SEMICONDUCTOR DEVICE HAVING A THROUGH ELECTRODE - A semiconductor device | 05-03-2012 |
| 20120104553 | Semiconductor device - A semiconductor device in which only the trigger voltage can be controlled without change in the hold voltage. In the semiconductor device, a protection device includes a lower doped collector layer, a sinker layer, a highly-doped collector layer, an emitter layer, a highly-doped base layer, a base layer, a first conductivity type layer, and a second conductivity type layer. The second conductivity type layer is formed in the lower doped collector layer and located between the base layer and first conductivity type layer. The second conductivity type layer has a higher impurity concentration than the lower doped collector layer. | 05-03-2012 |
| 20120104544 | SEMICONDUCTOR DEVICE - A semiconductor device adapted such that written information cannot be analyzed even by using a method of analyzing the presence or absence of electric charge, accumulated on a gate electrode, in which a substrate is a first conduction type, for example, p-type semiconductor substrate (for example, silicon substrate), an antifuse has a gate electrode and a second conduction type diffusion layer, the second conduction type diffusion layer is formed in the substrate and has, for example, an n-conduction type, a first contact is connected to the gate electrode, second contacts are formed in a layer identical with the first contact and connected to a region of the substrate in which the second conduction type diffusion layer is not formed, and the second contact is adjacent to the first contact. | 05-03-2012 |
| 20120104494 | SEMICONDUCTOR DEVICE - A field-effect transistor ( | 05-03-2012 |
| 20120104481 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion. | 05-03-2012 |
| 20120102354 | TIMER UNIT CIRCUIT HAVING PLURALITY OF OUTPUT MODES AND METHOD OF USING THE SAME - A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator. | 04-26-2012 |
| 20120100715 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH ELECTRODE - The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region. | 04-26-2012 |
| 20120099475 | NoC SYSTEM AND INPUT SWITCHING DEVICE - An input switching device is provided between a plurality of functional blocks (NoC routers or IP) connected to a specific router among a plurality of NoC routers of a NoC system and the specific router. The specific router includes a plurality of first buffers that temporarily store flits from the input switching device. A plurality of second buffers in the input switching device correspond to the respective one of the plurality of functional blocks, and temporarily store the flits from the functional block. A controller selectively sets one of the plurality of first buffers as output destination of the flit stored in each of the second buffers based on a free space of the plurality of first buffers. A distributor outputs the flit stored in each of the second buffers to output destination set for the flit by the controller. In this way, throughput degradation of the NoC system can be prevented. | 04-26-2012 |
| 20120098635 | RESISTIVE ELEMENT AND MANUFACTURING METHOD THEREFOR - A higher precision resistive element suppresses variation of the resistance value due to variation of film thickness. A resistive element includes a first portion having a first film thickness and a first width, and a second portion having the first film thickness and a second width determined by the first width. The sum of the first and second widths is constant. The first portion has an upper surface at a position at which a height from the bottom surface of the resistive element first portion is a first height. The resistive element second portion has an upper surface of the resistive element second portion at a position at which a height from a surface including the bottom surface of the resistive element first portion is the first height. The resistive element first portion and the resistive element second portion are coupled to each other via a coupling portion. | 04-26-2012 |
| 20120098606 | HIGH-FREQUENCY SIGNAL PROCESSING DEVICE - Disclosed is a high-frequency signal processing device capable of reducing transmission power variation and harmonic distortion. For example, the high-frequency signal processing device includes a pre-driver circuit, which operates within a saturation region, and a final stage driver circuit, which operates within a linear region and performs a linear amplification operation by using an inductor having a high Q-value. The pre-driver circuit suppresses the amplitude level variation of a signal directly modulated, for instance, by a voltage-controlled oscillator circuit. Harmonic distortion components (2HD and 3HD), which may be generated by the pre-driver circuit, are reduced, for instance, by the inductor of the final stage driver circuit. | 04-26-2012 |
| 20120098587 | Power semiconductor device and operation method thereof - A power semiconductor device has: an output transistor connected between a power-supply terminal and an output terminal; a gate charge-discharge circuit configured to charge/discharge a first node connected to a gate of the output transistor to ON/OFF control the output transistor; a short switch circuit connected between the first node and the output terminal; and a short control circuit configured to control the short switch circuit. In the turn-ON period, the ON period and the turn-OFF period, the short control circuit cuts off electrical connection between the first node and the output terminal through the short switch circuit. In the OFF period, the short control circuit electrically connects the first node and the output terminal through the short switch circuit. | 04-26-2012 |
| 20120098060 | SEMICONDUCTOR DEVICE - A semiconductor device for preventing an outer well from being separated by a trench gate electrode from the well of a cell region while suppressing increase in the gate resistance in which buried gate electrodes extending in a direction overlapping a gate contact region extend only before a gate electrode so as not to overlap the gate electrode, the source contact situated between each of the buried gate electrodes is shorter than the buried gate electrode in the vertical direction, the ends of the buried gate electrodes on the side of the gate electrode are connected with each other by a buried connecting electrode disposed before the gate electrode, the buried connecting electrode extends in a direction parallel with the longer side of the semiconductor device, and is not connected to the buried gate electrode on the side of the contact situated adjacent to the contact-side buried gate electrode. | 04-26-2012 |
| 20120097912 | SEMICONDUCTOR DEVICE - For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized. | 04-26-2012 |
| 20120094497 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer. | 04-19-2012 |
| 20120092322 | LIQUID CRYSTAL DISPLAY DRIVE CIRCUIT AND METHOD FOR DRIVING SAME - A liquid crystal display drive circuit includes first and second buffer circuits, first to fourth switches, and a control signal generation circuit (CSGC). The first buffer circuit drives a first or second data line, and the second buffer circuit drives the second or first data line. Closing the first switch makes the first buffer circuit drive the first data line responsive to a first control signal. Closing the second switch makes the second buffer circuit drive the second data line. Closing the third switch makes the first buffer circuit drive the second data line in responsive to a second control signal. Closing the fourth switch is makes the second buffer circuit drive the first data line. The CSGC generates the first-third control signals for causing respective outputs of the first buffer circuit, and the second buffer circuit to be in high impedance state on the basis of a strobe signal. | 04-19-2012 |
| 20120092088 | RADIO COMMUNICATION APPARATUS - A large scale integrated (LSI) circuit includes a first terminal, a second terminal, a transmitting circuit coupled to the first terminal and the second terminal, and a receiving circuit coupled to the first terminal and the second terminal. The first and second terminals are coupled to an external portion of the large scale integrated circuit. The external portion includes a first branching circuit, a second branching circuit coupled to the first branching circuit, and first and second antennas coupled to the second branching circuit. | 04-19-2012 |
| 20120092065 | FILTER CIRCUIT AND COMMUNICATION SEMICONDUCTOR DEVICE USING THE SAME - The present invention intends to provide a filter circuit in which an area occupied by the circuit can be reduced by suppressing the scale of its circuit configuration while a predetermined vicinity disturbance wave rejection ratio is maintained and a communication semiconductor device using the same, the filter circuit filtering an analog signal and including a voltage/current conversion circuit for converting the analog signal from voltage to current, and a capacitor array which executes signal processing by charging/discharging the current converted by the voltage/current conversion circuit to/from plural capacitors, the capacitor array being so constructed that the plural capacitors are divided to plural stages so that signals averaged by the capacitor on a preceding stage are accumulated in the capacitor on a next stage successively. | 04-19-2012 |
| 20120091510 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, MASK FOR SEMICONDUCTOR MANUFACTURE, AND OPTICAL PROXIMITY CORRECTION METHOD - An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area ( | 04-19-2012 |
| 20120089771 | Data Processing Apparatus - A data processing apparatus reduces the number of the buffer SRAMs to decrease chip area. The data processing apparatus includes an SDRAM address allocation register that holds information indicating which region of the SDRAM will be allocated to each of the IPs, and a buffer SRAM address allocation register that holds information indicating which region of the first and second buffer SRAMs will be allocated to each of the IPs. The bus I/F stores the data read from the SDRAM into the second buffer SRAM with reference to the SDRAM address allocation register and the buffer SRAM address allocation register. Therefore, it is not necessary to provide each of the IPs with a buffer SRAM, which allows integration into a small number of buffer SRAMs. | 04-12-2012 |
| 20120087489 | CRYPTOGRAPHIC PROCESSING APPARATUS AND CONTROL METHOD FOR CRYPTOGRAPHIC PROCESSING CIRCUIT - An aspect of the present invention is a cryptographic processing apparatus including a division unit that divides input data into multiple partial data items, the input data being one of plaintext and a round processing result; multiple data holding units that hold the partial data items, respectively; and a combining unit that combines the partial data items held in the multiple data holding units into a single round processing target data item to be subjected to round processing. The division unit selects a storage destination of each partial data item from among the data holding units, and stores each of the partial data items into the storage destination selected. The combining unit combines the partial data items into a round processing target item to reconstruct the input data according to the storage destination of each partial data item selected by the division unit. | 04-12-2012 |
| 20120087225 | Digital PLL circuit, information readout device, disc readout device, and signal processing method - A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal. | 04-12-2012 |
| 20120087219 | WOBBLE SIGNAL EXTRACTING CIRCUIT, METHOD FOR EXTRACTING WOBBLE SIGNAL, AND OPTICAL DISK UNIT - A wobble signal extracting circuit includes: a readout signal generating circuit generating an RF signal by adding first and second detection signals corresponding to reflected light from inside and outside a recording track; a first subtractor generating a push-pull signal by subtracting the first and second detection signals, respectively; a first analog-to-digital converter (ADC) converting the RF signal to digital; a second ADC converting the push-pull signal to digital; a residual RF component generating circuit generating a residual RF signal component equivalent to the RF signal component remaining in the digitized push-pull signal; and a second subtractor generating the wobble signal by subtracting the residual RF signal component from the digitized push-pull signal. The residual RF component generating circuit generates the residual RF signal component so that it may approach the remaining RF signal component based on correlation between the wobble signal and the digitized RF signal. | 04-12-2012 |
| 20120087198 | SEMICONDUCTOR MEMORY DEVICE WITH ADJUSTABLE SELECTED WORK LINE POTENTIAL UNDER LOW VOLTAGE CONDITION - A level shift element adjusting a voltage level at the time of selection of a word line according to fluctuations in threshold voltage of a memory cell transistor is arranged for each word line. This level shift element lowers a driver power supply voltage, and transmits the level-shifted voltage onto a selected word line. The level shift element can be replaced with a pull-down element for pulling down the word line voltage according to the threshold voltage level of the memory cell transistor. In either case, the selected word line voltage level can be adjusted according to the fluctuations in threshold voltage of the memory cell transistor without using another power supply system. Thus, the power supply circuitry is not complicated, and it is possible to achieve a semiconductor memory device that can stably read and write data even with a low power supply voltage. | 04-12-2012 |
| 20120086478 | SEMICONDUCTOR DEVICE INCLUDING A TEST CIRCUIT OF A MULTIVALUED LOGIC CIRCUIT HAVING AN IMPEDANCE CONTROL - A semiconductor device, having an input terminal configured to receive a multi-valued input signal as input, the multi-valued input signal including a plurality of values, a multi-valued logic circuit that operates with a multi-valued function and output binary signals to an output section in response to the input signal that has been input to the input terminal, the output section having a number of nodes being one less than a number of the plurality of values of the multi-valued input signal, and an impedance control circuit that is connected to the input terminal and the output section, and changes a combined resistance value in response to the binary signals of the plurality of nodes to change a current which flows in the input terminal. | 04-12-2012 |
| 20120086416 | POWER SUPPLY DEVICE - Miniaturization of a multiphase type power supply device can be achieved. A power supply control unit in which, for example, a microcontroller unit, a memory unit and an analog controller unit are formed over a single chip, a plurality of PWM-equipped drive units, and a plurality of inductors configure a multiphase power supply. The microcontroller unit outputs clock signals each having a frequency and a phase defined based on a program on the memory unit to the respective PWM-equipped drive units. The analog controller unit detects a difference between a voltage value of a load and a target voltage value acquired via a serial interface and outputs an error amp signal therefrom. Each of the PWM-equipped drive units drives each inductor by a peak current control system using the clock signal and the error amp signal. | 04-12-2012 |
| 20120085888 | BACK-SIDE ILLUMINATED SOLID-STATE IMAGING DEVICE - A back-side illuminated solid-state imaging device includes a photodiode and MOS transistors at a semiconductor substrate. The MOS transistors are formed over the front surface of the semiconductor substrate. The photodiode responds to an incident light applied to the back surface opposite to the front surface of the semiconductor substrate. A charge storing portion, and a first and second transfer gates are formed over the main part of the photodiode and the front surface of the semiconductor substrate located above the vicinity of the main part so as to achieve the global shutter function. Since the irradiation light is incident on the photodiode from the back surface of the semiconductor substrate in back-side illuminated solid-state imaging device, the sensitivity of the photodiode is not reduced even when the first and second transfer gates, and the charge storing portion are formed to achieve the global shutter function. | 04-12-2012 |
| 20120084495 | SEMICONDUCTOR PROGRAMMABLE DEVICE - An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function. | 04-05-2012 |
| 20120083119 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes forming a first insulating interlayer positioned above one surface of a substrate, forming a first hole extended from the surface of the first insulating interlayer to midway of the substrate, forming a through-electrode in the first hole, forming an electro-conductive pattern positioned on the surface of the first insulating interlayer, and connected to one end of the through-electrode, making the other end of the through-electrode expose, by removing the other surface of the substrate, and forming a connection terminal connected to the other end of the through-electrode, on the other surface of the substrate. | 04-05-2012 |
| 20120083115 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING AN INTERCONNECT STRUCTURE AND A REINFORCING INSULATING FILM - A semiconductor device includes in an interconnect structure which includes a first interconnect made of a copper-containing metal, a first Cu silicide layer covering the upper portion of the first interconnect, a conductive first plug provided on the upper portion of the Cu silicide layer and connected to the first interconnect, a Cu silicide layer covering the upper portion of the first plug, a first porous MSQ film provided over the side wall from the first interconnect through the first plug and formed to cover the side wall of the first interconnect, the upper portion of the first interconnect, and the side wall of the first plug, and a first SiCN film disposed under the first porous MSQ film to contact with the lower portion of the side wall of the first interconnect and having the greater film density than the first porous MSQ film. | 04-05-2012 |
| 20120081262 | SWITCH CIRCUIT, SEMICONDUCTOR DEVICE, AND PORTABLE WIRELESS DEVICE - A switch circuit with a unit capable of improving a margin voltage without using a negative bias generation circuit is provided. A switch comprising an N-type MOSFET is used for a switch passing a signal to an antenna and a switch comprising a P-type MOSFET is used for a shunt switch grounding a signal. A common control signal is input to the gate terminal of the MOSFET constituting each switch. The inverted signal of this control signal is coupled to a ground terminal of the switch, and thus the potential of the gate terminal of each MOSFET can be set to the ground voltage. | 04-05-2012 |
| 20120080805 | Semiconductor device and method of manufacturing the same - A semiconductor device according to the invention includes a first Cu interconnect and a first barrier insulating film. a The first barrier insulating film is provided on the first Cu interconnect, and prevents Cu from being diffused from the first Cu interconnect. In addition, the semiconductor device includes a second Cu interconnect and a second barrier insulating film on the first barrier insulating film. The second barrier insulating film is provided on a first Cu interconnect, and prevents Cu from being diffused from the second Cu interconnect. The first and second barrier insulating films are made of a silicon-based insulating film having a branched alkyl group and a carbon-carbon double bond. | 04-05-2012 |
| 20120080736 | SEMICONDUCTOR DEVICE - An antifuse whose internal written information cannot be analyzed even by utilizing methods to determine whether there is a charge-up in the electrodes. The antifuse includes a gate insulation film, a gate electrode, and a first diffusion layer. A second diffusion layer is isolated from the first diffusion layer by way of a device isolator film, and is the same conduction type as the first diffusion layer. The gate wiring is formed as one integrated piece with the gate electrode, and extends over the device isolator film. A common contact couples the gate wiring to the second diffusion layer. The gate electrode is comprised of semiconductor material such as polysilicon that is doped with impurities of the same conduction type as the first diffusion layer. The second diffusion layer is coupled only to the common contact. | 04-05-2012 |
| 20120079308 | USB COMMUNICATION APPARATUS AND METHOD OF REDUCING POWER CONSUMPTION AMOUNT THEREOF - A USB (Universal Serial Bus) communication apparatus includes: a driver circuit connected to a USB bus and configured to transmit a packet onto the USB bus for a packet transmission period which is determined based on a transmission request signal from another unit. A receiver control circuit generates a fixation request signal and a generation control signal in response to the transmission request signal. A receiver circuit connected to the USB bus generates a squelch signal showing that the packet is being transmitting onto the USB bus, and stops generating the squelch signal in response to the generation control signal. A line state signal control circuit is configured to output a specific line state signal based on the squelch signal to notify to another unit that the packet is been transmitting onto the USB bus, and to fix the specific line state signal in response to the fixation request signal. | 03-29-2012 |
| 20120079286 | DATA PROCESSING APPARATUS - A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal. | 03-29-2012 |
| 20120079238 | DATA PROCESSING DEVICE - A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board. | 03-29-2012 |
| 20120077332 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented. | 03-29-2012 |
| 20120076209 | TRANSCODING DEVICE, TRANSCODING METHOD AND PROGRAM THEREOF - A device, a method and a program to simplify transcoding of TTS (timestamped transport streams). When transcoding video data in the input TTS, the video processor unit reattaches time stamps in sequence within the applicable frame period of each video frame to each video packet within the applicable video frame after recompression. When transcoding audio data in the input TTS, the audio processor unit reattaches time stamps in sequence within the applicable video frame period of each video frame to each audio packet in the applicable video frame after recompression. | 03-29-2012 |
| 20120075050 | CIRCUIT DEVICE - The device includes a first inductor, a first insulating layer, a second inductor, and a third inductor. The first inductor includes a helical conductive pattern. | 03-29-2012 |
| 20120074986 | SEMICONDUCTOR DEVICE - A high-accuracy clock signal is generated even when the settings of the clock frequency are changed or there is a variation in power supply, temperature, or the like. A frequency-voltage conversion circuit includes a switch portion including switches, electrostatic capacitive elements, and other switches. The electrostatic capacitive elements have different absolute capacitance values, and are provided so as to cover a frequency range intended by a designer. For example, based on 4-bit frequency adjustment control signals, the other switches select the electrostatic capacitive elements having the electrostatic capacitance values thereof each weighted with 2 to perform the switching of a frequency. | 03-29-2012 |
| 20120074472 | Power Semiconductor Device Having Gate Electrode Coupling Portions for Etchant Control - A general insulated gate power semiconductor active element with many gate electrodes arranged in parallel has a laminated structure including a barrier metal film and a thick aluminum electrode film formed over the gate electrodes via an interlayer insulating film. When the aluminum electrode film is embedded in between the gate electrodes in parallel, voids may be generated with the electrodes. Such voids allow the etchant to penetrate in wet etching, which may promote the etching up to a part of the electrode film in an active cell region which is to be left. Thus, an insulated gate power semiconductor device is provided to include gate electrodes protruding outward from the inside of the active cell region, and a gate electrode coupling portion for coupling the gate electrodes outside the active cell region. The gate electrode coupling portion is covered with a metal electrode covering the active cell region. | 03-29-2012 |
| 20120072804 | DATA READ-OUT CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA READING IN SEMICONDUCTOR MEMORY DEVICE - A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data. | 03-22-2012 |
| 20120070986 | SEMICONDUCTOR DEVICE HAVING INSULATING FILM WITH SURFACE MODIFICATION LAYER AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor device, which includes an interlayer insulating film formed on a semiconductor substrate, a wiring layer filled in a recess formed in the interlayer insulating film, and a cap insulating film. The interlayer insulating film includes a first SiOCH film and a surface modification layer including an SiOCH film formed by modifying a surface layer of the first SiOCH film, the SiOCH film having a lower carbon concentration and a higher oxygen concentration than the first SiOCH film has. The cap insulating film contacts with surfaces of the metal wiring and the surface modification layer. | 03-22-2012 |
| 20120069692 | SEMICONDUCTOR DEVICE - A data input buffer is changed from an inactive to an active state after the reception of instruction for a write operation effected on a memory unit. The input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by turning on a power switch to cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, it is rendered inactive in advance before the instruction is provided, whereby wasteful power consumption is reduced. In another aspect, power consumption is reduced by changing from the active to the inactive state in a time period from a write command issuing to a next command issuing. | 03-22-2012 |
| 20120069690 | SEMICONDUCTOR INTEGRATED CIRCUIT AND CONTROL METHOD - A semiconductor integrated circuit for selecting one from a plurality of external storage devices and loading an execution program that includes a fuse part having a plurality of internal fuse circuits, and a processing unit that loads the execution program from the external storage device selected according to a value indicated by the internal fuse circuit. | 03-22-2012 |
| 20120068362 | SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR MEMBER AND MOUNTING MEMBER - A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased. | 03-22-2012 |
| 20120065920 | EVALUATION METHOD, EVALUATION APPARATUS, AND SIMULATION METHOD OF SEMICONDUCTOR DEVICE - An evaluation method of a semiconductor device according to an aspect of the present invention includes MISFETs including a gate insulating film, the evaluation method including measuring an RTN of a plurality of MISFETs, and extracting at least two parameters selected from a position of a trap in the gate insulating film, an energy of the trap, an RTN time constant, and an RTN amplitude based on a measurement result of the RTN, and obtaining a correlation between these at least two parameters. | 03-15-2012 |
| 20120064952 | Radio Frequency Module Having an Isolation Mode Between Transmission Mode and Power Saving Mode - A radio frequency module is configured to enter a power saving mode with high reliability. The radio frequency module includes, e.g., a first switch transistor for coupling a transmission node to an antenna, a second switch transistor for shunting the transmission node to a ground voltage, and a level shift circuit for performing on-off control of the first and second switch transistors by positive and negative power supply voltages. The level shift circuit, upon receiving a sleep instruction while the module is in a transmission operation mode in which the first switch transistor for coupling a transmission node to an antenna is turned on and the second switch transistor for shunting the transmission node to a ground voltage is turned off, first transitions to an isolation operation mode in which the first switch transistor for coupling a transmission node to an antenna is turned off and the second switch transistor for shunting the transmission node to a ground voltage is turned on for a first period of time, and then transitions to a sleep mode in which the positive and negative power supply voltages are deactivated. | 03-15-2012 |
| 20120064850 | Harmonic rejection mixer and phase adjustment method thereof - A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics. | 03-15-2012 |
| 20120063496 | Wireless Transmitters - Transmitter circuits for generating baseband signals having low receiver-band noise are disclosed. In one embodiment, the transmitter circuit comprises an active filtering-and-amplifying component comprising a first input configured to receive a first input signal, and a first output configured to output a first output signal. The transmitter circuit further comprises a passive filtering component comprising a second input connected to the first output and configured to receive the first output signal, a passive pole arrangement comprising a number of switchable resistance elements and a capacitance element connected across the plurality of switchable resistance elements, and a second output configured to output a second output signal having reduced noise as compared to the first output signal. The transmitter still further comprises a number of feedback loops connecting the passive filtering component to the first input. | 03-15-2012 |
| 20120063213 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element | 03-15-2012 |
| 20120062369 | WIRELESS COMMUNICATION SYSTEM, WIRELESS COMMUNICATION METHOD, RADIO EQUIPMENT, AND DATA TRANSMITTER - Provided is a wireless communication system including a first radio equipment that transmits first data using first radio waves, a data transmitter that outputs a second radio wave generated by modulating the first radio wave according to second data to be transmitted, and a second radio equipment that receives the first radio wave and the second radio wave, and separates and demodulates the first data transmitted from the first radio equipment and the second data transmitted from the data transmitter contained in the received radio waves. | 03-15-2012 |
| 20120062301 | Control voltage generating circuit, constant current source circuit, and delay circuit and logic circuit including the same - A control voltage generating circuit according to an aspect of the present invention includes: a reference voltage unit that includes a plurality of first transistors of the same conductivity type connected in series between a first power supply and a second power supply, and generates a drain voltage of one of the plurality of first transistor as a reference voltage; and a voltage conversion unit that includes a plurality of second transistors connected in series between the first power supply and the second power supply and having the same conductivity type as that of the reference voltage, supplies the reference voltage to a gate of one of the plurality of second transistors, and outputs a drain voltage of one of the plurality of second transistors as a control voltage. | 03-15-2012 |
| 20120061817 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor chip is mounted on a heat sink disposed inside a through-hole of a wiring board, electrodes of the semiconductor chip and connecting terminals of the wiring board are connected by bonding wires, a sealing resin is formed to cover the semiconductor chip and the bonding wires, and solder balls are formed on the lower surface of the wiring board, thereby constituting the semiconductor device. The heat sink is thicker than the wiring board. The heat sink has a protruded portion protruding to outside from the side surface of the heat sink, the protruded portion is located on the upper surface of the wiring board outside the through-hole, and the lower surface of the protruded portion contacts to the upper surface of the wiring board. When the semiconductor device is manufactured, the heat sink is inserted from the upper surface side of the wiring board. | 03-15-2012 |
| 20120058618 | Nonvolatile semiconductor storage device with charge storage layer and its manufacturing method - A method of manufacturing a nonvolatile semiconductor storage device includes sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate, sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove, forming a word gate electrode to fill in the groove whose inside is covered with an insulating film, after said forming the word gate electrode, removing the mask film, after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode, etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film, removing the conductive film and the charge storage film to form a control gate electrode, and forming a source drain diffusion layer. | 03-08-2012 |
| 20120057828 | OPTICAL TRANSMISSION MODULE AND METHOD FOR MANUFACTURING OPTICAL TRANSMISSION MODULE - An optical transmission module includes a stem, a semiconductor laser element mounted over the stem, a cap fixed to the stem and hermetically sealing the semiconductor laser element, and an optical isolator arranged on an optical path of light emitted from the semiconductor laser element. The cap includes a tubular body, one end side of which is fixed to the stem, and a light transmitting section located on the optical path while closing an opening on the other end side of the body, and fixed to the body so as to keep hermeticity with the body. The optical isolator is arranged inside an area hermetically sealed by the cap. | 03-08-2012 |
| 20120056657 | INTERFACE CIRCUIT - An interface circuit according to one aspect of the present invention may include a receiving circuit operating on a supply voltage lower than a high-level voltage value of an input binary signal, an input level determination circuit generating an input level determination signal having a frequency higher than a frequency of the binary signal and controls whether to output the input level determination signal or not, based on a voltage level of the binary signal, and an AC coupling element connected between an output terminal of the input level determination circuit and an input terminal of the receiving circuit. | 03-08-2012 |
| 20120056605 | Integrated circuit device for switching regulator and designing method therefor - An integrated circuit device for a switching regulator, includes: a controller configured to generate a digital duty signal for a current mode control of the switching regulator based on an output voltage to be supplied from the switching regulator to a load circuit; and a switching pulse generating section configured to set a time ratio of a switching pulse signal for controlling turning-on and turning-off of a switching circuit which is provided in the switching regulator, based on the digital duty signal. The controller is a digital circuit which operates based on a master clock of the same frequency as a switching frequency of the switching circuit. | 03-08-2012 |
| 20120056302 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor. | 03-08-2012 |
| 20120056296 | SEMICONDUCTOR DEVICE AND METHOD OF BLOWING FUSE THEREOF - A semiconductor device comprises an active region including a core circuit forming region and a buffer forming region, and a fuse element forming region arranged on a corner of the active region and to be able to be electrically fused. It is possible to arrange the fuse element without forming the fuse in the core circuit forming region by arranging the fuse element forming region at the corner of the active region. | 03-08-2012 |
| 20120047376 | Semiconductor integrated circuit - In a semiconductor LSI that sequentially performs predetermined processing on data input successively, a host CPU, a plurality of sequencers, and a data engine are connected in a hierarchical manner with the host CPU at top and the data engine at bottom. Each sequencer includes a memory that stores a parameter for execution of the sequencer, a memory controller, a loop counter, a sequence controller, and an interface unit that handles transmission and reception of signals with an external unit of the sequencer. The interface units of the plurality of sequencers have the same specifications. | 02-23-2012 |
| 20120045114 | Authentication device, authentication method, and an information storage medium storing a program - There is provided an authentication device including an authentication information storage unit that stores authentication information acquired from an authentication pattern including a part or the entirety of a mottled pattern or a dot pattern formed over an electronic component as information for indentifying each of a plurality of electronic components, an authentication information acquiring unit that acquires a first authentication information acquired from the authentication pattern formed over a first electronic component that is an object to be authenticated, a search unit that searches whether or not the authentication information storage unit stores the first authentication information by using the first authentication information as a search key, and an output unit that outputs a search result of the search unit. | 02-23-2012 |
| 20120044741 | Semiconductor device having memory unit, method of writing to or reading from memory unit, and semiconductor device manufacturing method - A first semiconductor device is formed over a substrate and includes a first insulation film, a first electrode, and a first diffusion layer. A second semiconductor device is formed over a substrate and includes a second insulation film, a second electrode, and a second diffusion layer. The second electrode is coupled to the first electrode. A control transistor allows one of a source and a drain to be coupled to the first electrode and the second electrode, allows the other one of the source and the drain to be coupled to a bit line, and allows a gate electrode to be coupled to a word line. A first potential control line is coupled to the first diffusion layer and controls a potential of the first diffusion layer. A second potential control line is coupled to the second diffusion layer and controls a potential of the second diffusion layer. | 02-23-2012 |
| 20120044216 | Display system and display device driver - A display system includes: a display device, a transmitting device which generates compressed data by performing a compression process on image data corresponding to a display image, and a driver which drives the display device in response to the compressed data received from the transmitting device. The driver includes: a decompression circuit which generates decompressed data by decompressing the compressed data, an FRC circuit configured to perform an FEC process on the decompressed data to generate display data and a drive circuit which drives the display device in response to the display data. The following relation holds: | 02-23-2012 |
| 20120044117 | PLANAR ANTENNA APPARATUS - A ground conductor is formed by a conductor pattern placed to a surface of a dielectric substrate, and includes a first and a second opening. A transmission line is formed over the dielectric substrate by the conductor pattern. The transmission line supplies a signal to a first and a second peripheral conductor respectively surrounding the first and the second opening. The first and second opening are arranged axis-symmetrically with respect to the transmission line. Opening areas of the first and the second opening are determined so that, due to loop currents supplied by the transmission line flowing through the first and the second peripheral conductor, a region including the first opening and the first peripheral conductor operates as a magnetic field radiation first loop radiating element, and a region including the second opening and the second peripheral conductor operates as a magnetic field radiation second loop radiating element. | 02-23-2012 |
| 20120043983 | INSPECTION DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT, INSPECTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND CONTROL PROGRAM OF INSPECTION DEVICE OF SEMICONDUCTOR INTEGRATED CIRCUIT - An inspection device of a semiconductor integrated circuit includes a drive unit that moves a probe card back and forth and from side to side, a storage unit that stores arrangement of the semiconductor integrated circuit and a shape of the pads, and a control unit that controls the drive unit. The control unit controls the drive unit, performs an apex detection processing pressing the probe pin to the semiconductor integrated circuit, detecting positions of the probe pin where conduction is detected or not detected, and calculating coordinates of one apex of a inspection pad from detected positions, and calculates central coordinates of the inspection pad from information of the shape of the inspection pad based on the coordinates of the apex of the inspection pad. The drive unit presses the probe pin to the calculated central coordinates of the inspection pad to perform inspection. | 02-23-2012 |
| 20120043656 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE - An improvement is achieved in the mounting reliability of a semiconductor device. A semiconductor chip is mounted over an upper surface of a wiring substrate. A plurality of solder balls are disposed individually over a plurality of lands formed on a lower surface of the wiring substrate. The plural lands include a first land group arranged in a plurality of rows and arranged along a peripheral edge portion of the lower surface of the wiring substrate, and a second land group arranged inside the first land group in the lower surface of the wiring substrate. The lands in the first land group are arranged with a first pitch, and the lands in the second land group are arranged with a second pitch higher than the first pitch. | 02-23-2012 |
| 20120043648 | Electronic component and method of manufacturing electronic component - In order to solve the above problem, provided is an electronic component having an authentication pattern formed on an exposed surface, in which the authentication pattern includes a base section including a resin and colored particles having a hue that can be identified in the base section, and the colored particles are dispersed so as to form dotted pattern in the base section. | 02-23-2012 |
| 20120043604 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof. | 02-23-2012 |
| 20120043603 | Method of manufacturing semiconductor device, and semiconductor device - A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench. | 02-23-2012 |
| 20120038621 | Display device, signal line driver, and data transfer method - A liquid crystal display device includes a timing controller, a liquid crystal display panel, multiple data drivers, and gate drivers. The timing controller supplies control data to specified drivers among the data drivers. The specified drivers generate gate driver control signals to control gate drivers in response to the control data, and supply gate driver control signals to the gate drivers. | 02-16-2012 |
| 20120038611 | Level shifter circuit and display driver circuit - A level shifter circuit according to the present invention includes a first voltage conversion circuit and a second voltage conversion circuit. The first voltage conversion circuit receives an input signal having an amplitude ranging between a power supply potential GND and a power supply potential VDDL, a power supply potential VDDH which is higher than the power supply potential VDDL is supplied. Further, a current limiting circuit is provided that limits a current supplied from a power supply line of the power supply potential VDDH, and outputs a voltage signal with a larger amplitude than that of the input signal according to the input signal. The second voltage conversion circuit is supplied with the power supply potential VDDH, and outputs an output signal with an amplitude ranging between the power supply potential GND and the power supply potential VDDH. | 02-16-2012 |
| 20120038498 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF OPERATING THE SAME - To improve resolution of a built-in A/D converter by reducing the area occupied by a chip of the built-in A/D converter in a semiconductor integrated circuit that is mounted in an on-vehicle millimeter wave radar device and which incorporates an A/D converter and an MPU. In the semiconductor integrated circuit, a plurality of reception signals of the radar device is A/D-converted by a single digital correction type A/D converter. The digital correction type A/D converter of the single A/D converter is a foreground digital correction type A/D converter that sequentially A/D-converts the reception signals output from a multiplexer of a receiving interface. The single A/D converter includes a pipeline type A/D converter having a plurality of cascade-coupled converters. The semiconductor integrated circuit comprises a correction signal generating unit, a digital correction D/A converter, and a digital correction unit for digital correction. | 02-16-2012 |
| 20120038003 | Semiconductor device - A second conduction-type MIS transistor in which a source is coupled to a second power source over the surface of a first conduction-type well and a drain is coupled to the open-drain signal terminal is provided. A second conduction-type first region is provided at both sides of the MIS transistor in parallel with a direction where the electric current of the MIS transistor flows and coupled to the open-drain signal terminal. The whole these components are surrounded by a first conduction-type guard ring coupled to the second power source and the outside surrounded by the first conduction-type guard ring is further surrounded by a second conduction-type guard ring coupled to a first power source. Thereby, the semiconductor device is capable of achieving ESD protection of an open-drain signal terminal having a small area and not providing a protection element between power source terminals. | 02-16-2012 |
| 20120037959 | SEMICONDUCTOR DEVICE WITH LESS POWER SUPPLY NOISE - A semiconductor device includes a first power supply line; a second power supply line; a first cell arrangement area in which a first cell is arranged; and a switch area in which a switching transistor and a decoupling capacitance are arranged. The first cell is provided in a first well of a first conductive type, the switching transistor is provided in a second well of the first conductive type, and the decoupling capacitance is provided in a separation area of a second conductive type to separate the first well and the second well from each other. The switching transistor connects the first power supply line and the second power supply line in response to a control signal, the first cell operates with power supplied from the second power supply line, and the decoupling capacitance is connected with the first power supply line. | 02-16-2012 |
| 20120037874 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film. | 02-16-2012 |
| 20120032939 | OUTPUT CIRCUIT, DATA DRIVER AND DISPLAY DEVICE - An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit. The third power supply voltage is intermediate between the first and second power supply voltages. The differential amplifier circuit includes, between the first and second power supplies, a differential input stage, first and second current mirror and first and second junction circuits. The output amplifier circuit includes first and second transistors connected between the first and third power supplies. The control circuit includes a third transistor connected between the output of the second current mirror and an end of the second junction circuit and supplied with a bias signal having a voltage in accordance with the third power supply voltage. | 02-09-2012 |
| 20120032726 | POWER SUPPLY SELECTION/DETECTION CIRCUIT - A power supply selection/detection circuit to select one main power supply from a plurality of external power supplies includes a resistance element with one end connected to an external power supply and another end connected to the main power supply, a first voltage detector to receive a voltage of the external power supply and detect a voltage of the external power supply, a second voltage detector to detect a voltage between the ends of the resistance element, and a switch connected between the external power supply and a ground to short-circuit or open-circuit between the external power supply and the ground according to an output of the second voltage detector. The resistance element and the first voltage detector are disposed for each of the plurality of external power supplies, and the second voltage detector and the switch are disposed for at least one of the plurality of external power supplies. | 02-09-2012 |
| 20120032707 | Load driving device - A load driving device includes a power supply terminal, a ground terminal, an output terminal coupled to a load, an output transistor coupled between the power supply and output terminals, a driver circuit supplying a first control signal to turn on the output transistor and a second control signal to turn off the output transistor, a discharge circuit coupled between the control terminal of the output transistor and the output terminal, a compensation circuit that turns on when a potential of the ground terminal is at least a predetermined value to maintain a non-conductive state of the output transistor when a polarity of a power supply coupled between the power supply and ground terminals is normal, and a reverse connection protection circuit coupled between the control terminal and the ground terminal, which brings the output transistor into a conductive state when a polarity of the power supply is reversed. | 02-09-2012 |
| 20120032357 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - In a semiconductor package, a stamp is provided on at least one of at least a pair of opposed sides on an outer peripheral portion in contact with an edge of the package, which is a blank space up to now. With this configuration, the amount of stamp can be increased even in a narrow stamp area. | 02-09-2012 |
| 20120032316 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, MOLD, AND SEALING DEVICE - A rear surface opposite to one plane of a die pad is formed to be exposed from one plane of a sealing resin. In addition, a concave portion disposed to be parallel with at least a first side of an outermost edge of a central structure and a second side adjacent to the first side, respectively, is formed in the one plane of the sealing resin. Here, a depth of the concave portion is equal to or greater than a height of the outermost edge of the central structure. | 02-09-2012 |
| 20120032298 | SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip is mounted on a first surface of an interconnect substrate, and has a multilayer interconnect layer. A first inductor is formed over the multilayer interconnect layer, and a wiring axis direction thereof is directed in a horizontal direction to the interconnect substrate. A second inductor is formed on the multilayer interconnect layer, and a wiring axis direction thereof is directed in the horizontal direction to the interconnect substrate. The second inductor is opposite to the first inductor. A sealing resin seals at least the first surface of the interconnect substrate and the semiconductor chip. A groove is formed over the whole area of a portion that is positioned between the at least first inductor and the second inductor of a boundary surface of the multilayer interconnect layer and the sealing resin. | 02-09-2012 |
| 20120032242 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a diffusion layer configuring a memory cell, and a diffusion layer configuring a dummy cell formed over the semiconductor substrate, interlayer insulating films formed over the semiconductor substrate, a cylinder layer insulating film including at least one concavity overlapping a diffusion layer and formed over an interlayer insulating film, a contact plug formed over one diffusion layer, a contact plug formed over another diffusion layer, a lower electrode formed over the side surfaces and bottom surface of the concavity and coupled to the diffusion layer by way of the contact plug, a dielectric material film formed over the lower electrode, over the cylinder layer insulating film and over the contact plug, and coupling by way of the contact plug to the diffusion layer, and an upper electrode formed over the inductive film material. | 02-09-2012 |
| 20120032228 | SEMICONDUCTOR DEVICE - A first first-conductivity-type diffusion layer, a first second-conductivity-type diffusion layer, a second first-conductivity-type diffusion layer, and a second second-conductivity-type diffusion layer are arranged in this order. In a region where the second second-conductivity-type diffusion layer and the first-conductivity-type layer are in contact with each other, impurity concentrations thereof are higher in a part in contact with a side face of the second second-conductivity-type diffusion layer than in a part at a bottom surface of the second second-conductivity-type diffusion layer. | 02-09-2012 |
| 20120028456 | ELECTRODE STUCTURE, SEMICONDUCTOR ELEMENT, AND METHODS OF MANUFACTURING THE SAME - According to the present invention, there is provided an electrode structure which includes: a nitride semiconductor layer; an electrode provided over the nitride semiconductor layer; and an electrode protective film provided over the electrode, wherein the nitride semiconductor layer contains a metal nitride containing Nb, Hf or Zr as a constitutive element, the electrode has a portion having a metal oxide containing Ti or V as a constitutive element formed therein, and the electrode protective film covers at least a portion of the electrode, and contains a protective layer having Au or Pt as a constitutive element. | 02-02-2012 |
| 20120028455 | Method of manufacturing a semiconductor device - A method of manufacturing a semiconductor device having a p-type field effect transistor and an n-type field effect transistor includes the steps of: forming an interface insulating layer and a high-permittivity layer on a substrate in the stated order; forming a pattern of a sacrifice layer on the high-permittivity layer; forming a metal-containing film containing metal elements therein on the high-permittivity layer in a first region where the sacrifice layer is formed and a second region where no sacrifice layer is formed; introducing the metal elements into an interface between the interface insulating layer and the high-permittivity layer in the second region by conducting a heat treatment; and removing the sacrifice layer by wet etching, wherein in the removing step, the sacrifice layer is etched easily more than the high-permittivity layer. With this configuration, the semiconductor device excellent in reliability is obtained. | 02-02-2012 |
| 20120028194 | PATTERN FORMATION METHOD USING LEVENSON-TYPE MASK AND METHOD OF MANUFACTURING LEVENSON-TYPE MASK - A method of forming a pattern including a first pattern portion having a first minimum dimension and a second pattern portion having a second minimum dimension includes a first exposure step of performing exposure using a Levenson-type mask and a second exposure step of performing exposure using a half tone-type mask. When second minimum dimension is 1.3 time or more than the first minimum dimension, the exposure amount of the second exposure step is set to be equal to or smaller than the exposure amount of the first exposure step. | 02-02-2012 |
| 20120026810 | SEMICONDUCTOR MEMORY DEVICE AND ANTIFUSE PROGRAMMING METHOD - An antifuse comprised of an NMOS transistor or an NMOS capacitor includes a first terminal coupled to a gate electrode, a second terminal coupled to a diffusion layer, and a gate insulating film interposed between the gate electrode and the diffusion layer. A programming circuit includes a first programming circuit which has first current drive capability and which performs first programming operation and a second programming circuit which has second current drive capability larger than the first current drive capability and which performs second programming operation to follow the first programming operation. In the first programming operation, the first programming circuit breaks down the gate insulating film by applying a first programming voltage between the first terminal and the second terminal. In the second programming operation, the second programming circuit applies a second programming voltage lower than the first programming voltage between the first terminal and the second terminal. | 02-02-2012 |
| 20120025913 | Envelope amplifier - An envelope amplifier includes an amplifier unit, a comparator unit and an output unit. The amplifier unit is made up of a first output section that outputs a first current in response to an amplitude of an input envelope signal, and a second output section. The second output section outputs a second current of a current value proportionate to a current value of the first current. Absolute value of the current value of the second current is greater than that of a current value of the first current. Comparator unit compares the current value of the first current. The output unit sums a current via an inductor derived from a current sustained or broken in response to a compared result of the comparator unit to the second current to deliver the resulting sum current at an output end. The first current is configured to be terminated without being delivered to the output unit (FIG. | 02-02-2012 |
| 20120025892 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device provided with a first circuit block BLK | 02-02-2012 |
| 20120025403 | DESIGN APPARATUS OF SEMICONDUCTOR DEVICE, DESIGN METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A design method of a semiconductor device includes four steps. The first step is of arranging grid wiring which includes a plurality of wiring lines arranged in parallel to each other and a plurality of vias connecting the plurality of wiring lines with each other. The second step is of arranging a plurality of internal circuits connected to the grid wiring. The third step is of calculating a current density of a current flowing in the grid wiring by the plurality of internal circuits. The fourth step is of dividing each of the plurality of wiring lines into portions each having a wiring length such that electromigration corresponding to the current density is suppressed. | 02-02-2012 |
| 20120025395 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO | 02-02-2012 |
| 20120025371 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film. | 02-02-2012 |
| 20120025351 | SEMICONDUCTOR DEVICE - A bipolar transistor of the invention has a second base region | 02-02-2012 |
| 20120025321 | SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode. | 02-02-2012 |
| 20120023308 | PARALLEL COMPARISON/SELECTION OPERATION APPARATUS, PROCESSOR, AND PARALLEL COMPARISON/SELECTION OPERATION METHOD - Provided is a parallel comparison/selection operation apparatus which efficiently executes a search for a maximum value or a search for a minimum value with an index. The parallel comparison/selection operation apparatus includes a vector comparison/selection unit | 01-26-2012 |
| 20120019710 | Autofocus control circuit, autofocus control method, and image pickup apparatus - An autofocus control circuit, includes a focusing unit determining an in-focus location of a subject image based on a contrast evaluation value of a compressed image data under a first environment, and based on a size of the compressed image data under a second environment. | 01-26-2012 |
| 20120019328 | HIGH FREQUENCY SIGNAL PROCESSING DEVICE - A high frequency signal processing device is capable of carrying out high-accuracy modulation by a PLL circuit. A digital loop is configured in addition to an analog loop having, for example, a phase frequency detector, a charge pump circuit, and a loop filter. A digital calibration circuit is provided which searches for the optimal code set to a capacitor bank upon frequency modulation. Upon the search for the optimal code, a calibration controller first sets a division ratio based on a center frequency to a divider and determines the value of a voltage control signal using the analog loop. Then, the loop filter holds the value of the voltage control signal therein, and a division ratio corresponding to a “center frequency+modulated portion” is set to the divider, thereby operating the digital loop. The optimal code is obtained by a convergent value of the digital loop. | 01-26-2012 |
| 20120018859 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To suppress a short circuit between neighboring wires which is caused when the loop of a wire is formed into multiple stages in a semiconductor device in which a wiring board and one semiconductor chip mounted over a main surface thereof are electrically coupled with the wire. In a semiconductor device in which a chip is mounted on an upper surface of a wiring board and a bonding lead of the wiring board and a bonding pad of the chip are electrically coupled with wires, a short circuit between the neighboring wires is suppressed by making larger the diameter of the longest wire arranged in a position closest to a corner part of the chip than the diameter of the other wires. | 01-26-2012 |
| 20120018839 | SEMICONDUCTOR DEVICE - CMOS inverters are included in a standard cell. Power supply lines are electrically connected to CMOS inverters, and include lower layer interconnects and upper layer interconnect. Lower layer interconnects extend along a boundary of standard cells adjacent to each other and on the boundary. Upper layer interconnects are positioned more inside in standard cell than lower layer interconnects, as viewed from a plane. CMOS inverters are electrically connected through upper layer interconnects to lower layer interconnects. Thus, a semiconductor device is obtained that can achieve both higher speeds and higher integration. | 01-26-2012 |
| 20120015517 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The semiconductor device includes an insulating film that is formed using a cyclic siloxane having a six-membered ring structure as a raw material; a trench that is formed in the insulating film; and a interconnect that is configured by a metal film embedded in the trench. In the semiconductor device, a modified layer is formed on a bottom surface of the trench, in which the number of carbon atoms and/or the number of nitrogen atoms per unit volume is larger than that inside the insulating film. | 01-19-2012 |
| 20120015492 | INSULATED GATE TYPE SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer. | 01-19-2012 |
| 20120013497 | A/D conversion circuit and test method - An electric device includes first, second and third selectors. A first node connects to a first input of the first selector, a second node connects to a first input of the second selector, a third node connects to a second input of the first selector, and a fourth node connects to a second input of the second selector. A first switch connects to the first node, and a second switch connects to the second node. A first capacitor connects between the first switch and the third node, and a second capacitor connects between the second switch and the fourth node. A fifth node connects between an output of the first selector and a first input of the third selector, and a sixth node connects between an output of the second selector and a second input of the third selector. An A/D converter connects to an output of the third selector. | 01-19-2012 |
| 20120013019 | SEMICONDUCTOR DEVICE - A signal line is formed in the a-th layer (a≧2) of a multi-layered interconnect layer and a redistribution layer. A plain line is formed in the b-th layer (b| 01-19-2012 | |
| 20120012978 | SEMICONDUCTOR DEVICE - A semiconductor device formed by using semiconductor packages is provided. The semiconductor device includes two semiconductor packages adjacently arranged in opposite directions on an inductive conductor. Terminals of the two semiconductor packages are joined by a third lead. the third lead is arranged substantially in parallel to the inductive conductor. Leads at the joint portions have, for example, a bent structure, and the third lead is arranged to be close to the inductive conductor. | 01-19-2012 |
| 20120012946 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET. | 01-19-2012 |
| 20120011914 | LEAD PROCESSING APPARATUS, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND LEAD PROCESSING DIE SET - A lead processing apparatus includes a first die unit, a second die unit that is movable relative to the first die unit, a load transmitting portion that transmits a load to the second die unit, and a stopper mechanism that stops the movement of the second die unit in a direction in which the second die unit approaches the first die unit. The stopper mechanism includes a plurality of stroke stopper pairs each having a first stroke stopper fixed to the first die unit and a second stroke stopper that is fixed to the second die unit and comes into contact with the stopper to stop the movement of the second die unit. The load transmitting portion distributes a load to a plurality of load transmission positions and transmits a press load to the second die unit. Each load transmission position is arranged coaxially with the stroke stopper pair. | 01-19-2012 |
| 20120011407 | SEMICONDUCTOR DEVICE - A diagnosis circuit | 01-12-2012 |
| 20120009800 | MASS PRODUCTION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD OF ELECTRONIC DEVICE - In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film). | 01-12-2012 |
| 20120009789 | Semiconductor device having seal ring structure and method of forming the same - A method of producing a semiconductor device includes forming, on a first insulating film formed on a substrate, a first groove in an element-forming region to form one of a via and a wiring therein, and a first seal ring groove in a seal ring part, forming one of a via and a wiring in the first groove and a first metal layer in the first seal ring groove, and then removing the metal material in a part exposed to an outside of the first groove and the first seal ring groove, forming a second insulating film on the first insulating film, forming, on the second insulating film, a second groove, and a second seal ring groove in the seal ring part on the first seal ring groove, and forming one of a via and a wiring in the second groove and a second metal layer. | 01-12-2012 |
| 20120009737 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - When chip-scale molding system is employed for QFP, the number of semiconductor devices available from a leadframe decreases because cavities each requires a runner portion. This problem can be overcome by employing MAP system, but use of a laminate tape increases the production cost. In through mold system, each cavity needs an ejector pin, which however makes it difficult to place a support pillar. The present application provides a manufacturing method of a semiconductor device by filling, while sandwiching a leadframe between mold dies having a matrix-state cavity group in which cavity columns obtained by linking mold cavities in series via a through gate have been placed in rows, a sealing resin in the cavities. In this method, the matrix-state cavity group has, at the cavity corner portions thereof, a support pillar having a cross-section striding over all the cavities adjacent to the cavity corner portions when viewed planarly. | 01-12-2012 |
| 20120009695 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present. | 01-12-2012 |
| 20120007759 | TRACK-AND-HOLD CIRCUIT AND A/D CONVERTER - A track-and-hold circuit includes a first sampling circuit that samples an analog input signal, a second sampling circuit that samples the analog input signal, the second sampling circuit and the first sampling circuit being connected in parallel, a first amplifier that amplifies a signal output from the first sampling circuit, and a second amplifier that amplifies a signal output from the second sampling circuit. | 01-12-2012 |
| 20120007225 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 01-12-2012 |
| 20120007224 | SEMICONDUCTOR DEVICE - In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package. | 01-12-2012 |
| 20120007194 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME IN WHICH VARIATIONS ARE REDUCED AND CHARACTERISTICS ARE IMPROVED - A method of manufacturing N-type MOSFET includes: implanting a p-type dopant into in a surface layer of a semiconductor substrate to form a channel region; forming a gate insulating film including High-k material and a gate electrode on said channel region; implanting a p-type dopant into both ends of said channel region in an inner portion of said semiconductor substrate to form halo regions; implanting a p-type dopant into both ends of said channel region in a surface layer of said semiconductor substrate to form extension regions. One of said step of forming said channel region and said step of forming halo regions includes: implanting C into one of said channel region and said halo regions. An inclusion amount of said High-k material is an amount that increase of a threshold voltage caused by said High-k material being included in said gate insulating film compensates for decrease of said threshold voltage caused by said C being implanted. | 01-12-2012 |
| 20120001608 | INTELLIGENT GATE DRIVE - According to an embodiment of the invention, an apparatus includes a microprocessor-based pulse-width modulation controller configured to generate a pulse-width modulation signal, and a synchronous converter including a first transistor, a second transistor, a first driver, and a second driver. The apparatus further includes a drive voltage generator configured to generate a drive voltage for the synchronous converter. The drive voltage generator is further configured to generate the drive voltage based on a measured output current and a measured input voltage. | 01-05-2012 |
| 20120001342 | SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is improved. | 01-05-2012 |
| 20120001257 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A downsized semiconductor device having an excellent reverse characteristic, and a method of manufacturing the semiconductor device is sought to improve. The semiconductor device comprises a semiconductor body having a polygonal contour. An active area is formed in the semiconductor body. An EQR electrode is formed so as to surround the active area and to have curved portions of the EQR electrode along the corners of the semiconductor body. An interlayer insulating film is formed to cover the active area and the EQR electrode. The EQR electrode is embedded in the interlayer insulating film around the active area. EQR contacts are in contact with the curved portions of the EQR electrode and the semiconductor body outside the curved portions, and have at least side walls covered with the interlayer insulating film. | 01-05-2012 |
| 20110318900 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided. | 12-29-2011 |
| 20110318849 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions. | 12-29-2011 |
| 20110317501 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously. | 12-29-2011 |
| 20110316816 | Drive circuit of display device and its driving method - A drive circuit | 12-29-2011 |
| 20110316582 | Semiconductor integrated circuit including a power controllable region - A semiconductor chip includes a first power supply line and a second power supply line. A first switch is coupled between the first power supply line and the second power supply line, and a second switch is coupled between the first power supply line and the second power supply line. A circuit is coupled to the second power supply line. A first control signal line is coupled to the first switch, and a second control signal line coupled to the second switch. A logic gate is coupled to the first and the second control signal lines and a terminal is coupled to the logic gate to output a signal to an outside of the semiconductor chip. | 12-29-2011 |
| 20110316161 | METHOD OF PRODUCING A DUAL DAMASCENE MULTILAYER INTERCONNECTION AND MULTILAYER INTERCONNECTION STRUCTURE - In an insulating film structure having a barrier insulating film, a via interlayer insulating film, a wiring interlayer insulating film, and a hard mask film stacked in this order on an underlayer wiring, a via hole pattern is formed in the insulating film structure, then a groove pattern is formed in the hard mask film, and a grove is formed in the insulating film structure using this as a mask. According to the prior art, the via side wall is oxidized equally severely in the both processes. The trench side wall is oxidized severely in the via first process according to the prior art, whereas, according to the present invention, the oxidation thereof is suppressed to such an extent that an almost non-oxidized state can be created. | 12-29-2011 |
| 20110316137 | METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The semiconductor device includes a semiconductor chip, a chip mounting portion, a suspension lead, and a plurality of leads. Each of the plurality of leads has a first part and a second part, and the suspension lead has a first part and a second part. The first part of each of the plurality of leads and the suspension lead project from the plurality of side surfaces of the sealing body, respectively. Parts of the side surfaces of the plurality of leads and the suspension lead are exposed from the plurality of side surfaces of the sealing body, respectively. An area of the obverse surface of the first part of the suspension lead is larger than an area of the obverse surface of the first part of each of the plurality of leads in a plan view. | 12-29-2011 |
| 20110316124 | SEMICONDUCTOR DEVICE - A semiconductor device having a through electrode excellent in performance as for an electrode and manufacturing stability is provided. There is provided a through electrode composed of a conductive small diameter plug and a conductive large diameter plug on a semiconductor device. A cross sectional area of the small diameter plug is made larger than a cross sectional area and a diameter of a connection plug, and is made smaller than a cross sectional area and a diameter of the large diameter plug. In addition, a protruding portion formed in such a way that the small diameter plug is projected from the silicon substrate is put into an upper face of the large diameter plug. Further, an upper face of the small diameter plug is connected to a first interconnect. | 12-29-2011 |
| 20110316118 | Semiconductor device - A semiconductor device includes a substrate including a diffusion region, a device isolation region, an inductor region, and a guard ring region, a guard ring formed on the substrate to be connected to the diffusion region in the guard ring region, an insulating film formed on the substrate, in which the insulating film includes an interconnect, and an inductor formed in the inductor region, in which the guard ring region surrounds the inductor region and the device isolation region. | 12-29-2011 |
| 20110316062 | SEMICONDUCTOR DEVICE - In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level. | 12-29-2011 |
| 20110316052 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region | 12-29-2011 |
| 20110316050 | SEMICONDUCTOR DEVICE HAVING A HETEROJUNCTION BIOPOLAR TRANSISTOR AND A FIELD EFFECT TRANSISTOR - A semiconductor device with a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) formed over the same substrate; providing improved HBT characteristics and a lowered HBT collector resistance and also satisfactory etching of the FET gate recess, along with low ON-resistance in the FET. The sub-collector layer of a heterojunction bipolar transistor (HBT) is a laminated structure of multiple semiconductor layers, and moreover with a collector electrode formed on a section projecting out from one collector layer. In two of the FET, at least one semiconductor layer on the semiconductor substrate side of the semiconductor layers forming the sub-collector layer of the HBT also serves as at least a portion of a capacitor layer. The total film thickness of the HBT sub-collector layer is 500 nm or more; and the total film thickness of the FET capacitor layer is between 50 nm and 300 nm. | 12-29-2011 |
| 20110313700 | VOLTAGE DETECTION SYSTEM AND CONTROLLING METHOD OF THE SAME - There is a need to solve a possible system malfunction when a power supply voltage decreases steeply. To solve this problem, a control method is provided for a voltage detection system having an interrupt mode and a reset mode. First and second detection levels are configured. When a power supply voltage is higher than the first detection level, a latch circuit is placed in a first state to enable the interrupt mode. When the power supply voltage becomes lower than or equal to the first detection level, an interrupt signal is generated to change the latch circuit from the first state to a second state and enable the reset mode. A system reset is issued when the power supply voltage becomes lower than or equal to the second detection level in the reset mode. | 12-22-2011 |
| 20110310080 | DRIVE CIRCUIT, DRIVE METHOD, AND DISPLAY DEVICE - Provided is a drive circuit including a PDAC and an NDAC that respectively select a positive gray scale voltage and a negative gray scale voltage according to gray scale data, a positive Amp and a negative Amp, an output selection switch that inverts outputs of the positive Amp and the negative Amp, an output switch that makes switching to disconnect an amplifier output from data lines during a switching period, a charge share switch that short-circuits the data lines during the switching period, and data selector circuits that set an amplifier input to a fixed voltage not dependent on a gray scale voltage corresponding to gray scale data for display during the switching period. | 12-22-2011 |
| 20110309889 | Variable-capacitance device - A variable-capacitance device includes a first capacitance element coupled between a first power supply terminal and an output terminal, a capacitance selection switch that is turned on and off in accordance with a capacitance switching signal, a second capacitance element coupled in parallel to the first capacitance element and in series to the capacitance selection switch, and an error correction circuit configured to operate such that in a state in which the capacitance selection switch is in an OFF state, in response to a charge reset signal that causes a voltage at the output terminal to be reset to a reset voltage, the error correction circuit substantially eliminates a difference between the voltage at the output terminal and a voltage at a capacitance switching node at which the second capacitance element is coupled to the capacitance selection switch. | 12-22-2011 |
| 20110309487 | SEMICONDUCTOR DEVICE, A METHOD OF MANUFACTURING THE SAME AND AN ELECTRONIC DEVICE - The semiconductor device is high in both heat dissipating property and connection reliability in mounting. The semiconductor device includes a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member. | 12-22-2011 |
| 20110309428 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of nonvolatile memory cells ( | 12-22-2011 |
| 20110309353 | Semiconductor device and method for manufacturing the same - A semiconductor device includes, in a first region over a semiconductor substrate, a first insulating layer, a first wiring, a second insulating layer, a third insulating layer, and a via and a second wiring embedded in the second insulating layer and the third insulating layer through a barrier metal, and includes, in a second region, the first insulating layer, a gate electrode, the second insulating layer, a semiconductor layer located, the third insulating layer, and a first electric conductor and a second electric conductor embedded in the third insulating layer so as to sandwich the gate electrode in a position overlapped with the semiconductor layer in a plan view through a barrier metal and coupled to the semiconductor layer through the barrier metal. | 12-22-2011 |
| 20110307853 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A path (different power-supply path) in which verification objective paths pass through two or more power domains is searched from a netlist and power-supply information, and delay-coefficient additional determination is performed in the different power-supply path. In this step, from voltage conditions in each power domain, a voltage condition under which the timing analysis result is most negative is detected, it is determined whether or not the delay coefficient is added for the voltage condition, and the delay coefficient is added. When the delay coefficient is added, the delay coefficient obtained in consideration of the power-supply voltage variation for the delay of the cell belonging to the different power-supply path is extracted from the delay-coefficient information, and is added to the delay value calculated based on the library. Then, based on the delay value to which the delay coefficient is added, the static timing verification is performed. | 12-15-2011 |
| 20110307851 | STATIC VERIFICATION PROGRAM, STATIC VERIFICATION DEVICE, AND STATIC VERIFICATION METHOD - A static verification program according to the present invention reads a circuit description and property. In a static verification step, static verification of the circuit description is performed on the basis of the property and the number of states that can be reached and the number of states that is reached are calculated. In a search coverage value calculation step, a search coverage value is calculated on the basis of the number of states that can be reached and the number of states that is reached. In a display step, the search coverage value is displayed in a state in which the search coverage value can be visually checked. | 12-15-2011 |
| 20110305060 | WIRING SUBSTRATE IN WHICH EQUAL-LENGTH WIRES ARE FORMED - In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil. | 12-15-2011 |
| 20110304388 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND WIRELESS COMMUNICATION SYSTEM - Disclosed are a semiconductor integrated circuit device and a wireless communication system that are capable of improving reception sensitivity. The wireless communication system includes, for instance, a first duplexer, a second duplexer, a first low-noise amplifier circuit, and a second low-noise amplifier circuit. A transmission band compliant with a communication standard is split into two segments for use, namely, low- and high-frequency transmission bands. A reception band compliant with the communication standard is split into two segments for use, namely, low- and high-frequency reception bands. The first duplexer uses the low-frequency transmission band and low-frequency reception band as passbands. The second duplexer uses the high-frequency transmission band and high-frequency reception band as passbands. A signal received from the first duplexer and a signal received from the second duplexer are respectively amplified by the first and the second low-noise amplifier circuits, which are respectively provided to handle such signals. | 12-15-2011 |
| 20110304055 | Semiconductor integrated circuit with multi-cut via and automated layout method for the same - A semiconductor integrated circuit includes a first wiring formed on a first wiring layer and prolonged in a first direction, a second wiring formed on a second wiring layer and prolonged in a second direction, a third wiring formed on the first wiring layer and prolonged in the first direction, a fourth wiring formed on the second wiring layer and prolonged in the second direction, a multi-cut via formed to connect the first wiring to the second wiring, the multi-cut via including a first via and a second via formed in the first direction, and a single-cut via formed to connect the third wiring to the fourth wiring. A first overhang is provided in a direction opposite to the first direction, the first overhang being larger than a second overhang, the second overhang being smaller than a third overhang. | 12-15-2011 |
| 20110304033 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE STORAGE METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING APPARATUS - A semiconductor package has a semiconductor chip, a lead frame in which a semiconductor chip is mounted on a die pad, and a resin sealing the semiconductor chip and the die pad from an upper surface and a lower surface, the resin has a concave portion disposed at the surface and a concave portion situated inside the concave portion in a plan view. | 12-15-2011 |
| 20110304017 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase. | 12-15-2011 |
| 20110300672 | SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREFOR - To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device. | 12-08-2011 |
| 20110299598 | MOTION VECTOR DISPLAY CIRCUIT AND MOTION VECTOR DISPLAY METHOD - A motion vector display circuit includes a motion vector detection circuit that detects a motion vector between frame images, and a norm calculation circuit that calculates the length of a motion vector detected by the motion vector detection circuit. The length of the detected motion vector is converted into a luminance component of a display signal, a first component of the motion vector is converted into a first chrominance component of the display signal, a second component of the motion vector is converted into a second chrominance component of the display signal, and the motion vector is displayed using the display signal. | 12-08-2011 |
| 20110298545 | RF POWER AMPLIFIER DEVICE AND OPERATING METHOD THEREOF - An RF power amplifier device includes a driver stage amplifier, a first RF amplifier, a second RF amplifier and a DC voltage converter operated by first, second and third external power supply voltages. The output of the driver stage amplifier is supplied to the inputs of the first and second RF amplifiers. An effective device size of the first RF amplifier is set to a device size larger than that of the second RF amplifier. The third external power supply voltage is supplied to the DC voltage converter, so that the DC voltage converter generates a fourth operating power supply voltage corresponding to a low voltage and supplies it to an output terminal of the second RF amplifier. An output terminal of the first RF amplifier can be supplied with the second external power supply voltage without via the DC voltage converter. | 12-08-2011 |
| 20110298133 | SEMICONDUCTOR DEVICE - The reliability of a porous Low-k film is improved. The mean diameter of first pores and second pores in an interlayer insulation film of a second fine layer including a porous Low-k film is set at 1.0 nm or more and less than 1.45 nm. This prevents the formation of a modified layer over the surface of the interlayer insulation film by process damages. Further, the formation of the moisture-containing modified layer is inhibited to prevent oxidation of a barrier film and a main conductor film forming respective wirings. This prevents deterioration of breakdown voltage between respective wirings. This prevents deterioration of the EM lifetime of wirings formed adjacent to the interlayer insulation film and the inter-wiring TDDB lifetime of the wirings. | 12-08-2011 |
| 20110298070 | Semiconductor Device Having Magnetoresistive Element and Manufacturing Method Thereof - A semiconductor device has a magnetoresistive element, a bit line over the magnetoresistive element, and a yoke cover over the bit line. To form the yoke cover, a laminate film is first formed over the bit line, the laminate film having a first barrier metal layer, a magnetic layer, and a second barrier metal layer which are formed successively over the bit line. Then, the laminate film is subjected to: reactive ion etching with a gas mixture of a carbon tetrafluoride (CF | 12-08-2011 |
| 20110298012 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits. | 12-08-2011 |
| 20110296260 | SEMICONDUCTOR DEVICE - An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result. | 12-01-2011 |
| 20110294445 | Semiconductor Antenna Switch - A semiconductor antenna switch has an antenna terminal, a transmission terminal and a reception terminal. The antenna switch is capable of reducing harmonic distortion even though it includes field effect transistors formed over a silicon substrate. A shunt transistor including a plurality of series-connected field effect transistors is connected between he transmission terminal and a common terminal, such as a common terminal, which may be an electrical ground. Off capacitances and/or gate widths of a plurality of the series-connected field effect transistors increase monotonically in the direction from the common terminal to the transmission terminal, or equivalently, decrease monotonically in the direction from the transmission terminal to the common terminal. | 12-01-2011 |
| 20110294282 | Semiconductor device and method for manufacturing the same - A method for manufacturing a semiconductor device including a vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor includes preparing a semiconductor substrate and injecting a first impurity of a second conductivity type to a first region, injecting a second impurity to a second region that is located inside and is narrower than the first region, and forming an epitaxial layer on the semiconductor substrate and forming the semiconductor layer constituted by the semiconductor substrate and the epitaxial layer, and at a same time, diffusing the first and the second impurities injected in a first impurity injection and a second impurity injection to form a buried layer of the second conductivity type. | 12-01-2011 |
