REALTEK SEMICONDUCTOR CORP. Patent applications |
Patent application number | Title | Published |
20160099689 | TRANSMISSION LINE DRIVER CIRCUIT FOR ADAPTIVELY CALIBRATING IMPEDANCE MATCHING - A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; an internal node; a first divider resistor positioned between the first signal node and the internal node; a second divider resistor positioned between the second signal node and the internal node; a comparing circuit for comparing a divided voltage at the internal node with a reference voltage to generate a comparison signal; and an adjusting circuit for adjusting resistance of at least one of the first and second adjustable resistors according to the comparison signal. | 04-07-2016 |
20160094196 | TRANSMISSION LINE DRIVER CIRCUIT FOR AUTOMATICALLY CALIBRATING IMPEDANCE MATCHING - A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; a first voltage difference generating circuit coupled with two terminals of the first adjustable resistor to generate a first voltage difference value; a second voltage difference generating circuit coupled with two terminals of the second adjustable resistor to generate a second voltage difference value; sample-and-hold circuits for generating sampled signals according to the first voltage difference value and the second voltage difference value; a comparing circuit for comparing the sampled signals; and an adjusting circuit for adjusting resistance of the first and/or second adjustable resistors according to the comparing result. | 03-31-2016 |
20150349794 | SELF-CALIBRATING VCO-BASED ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF - A circuit includes an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance with a selection signal. The circuit also includes N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables and outputting N raw data, and N refined data, respectively. An output dispatch unit receives the N refined data and outputting an output data in accordance with the selection signal, and a calibration controller receives the N raw data and outputting the selection signal, the N control signals, the N mapping tables, and a digital code. A DAC (digital-to-analog converter) receives the digital code and outputting the calibration signal, wherein one of the dispatched signals, as specified by the selection signal is from the calibration signal while the other dispatched signals are from the input signal. | 12-03-2015 |
20150348702 | PARAMETER-VARIABLE DEVICE, VARIABLE INDUCTOR AND DEVICE HAVING THE VARIABLE INDUCTOR - A device having a variable inductor includes an inductor having an inductance, a first conductor having a first grounding property, and a second conductor having a second grounding property. The device further includes a first single-mesh structure including a first grid. The first grid includes a first conducting wire electrically connected to the first conductor, and a second conducting wire electrically connected to the first conducting wire and the first conductor, wherein the first conducting wire, the second conducting wire and the first conductor are configured to form a first loop corresponding to the inductor for tuning the inductance. The first single-mesh structure further includes a second grid. The second grid includes a third conducting wire electrically connected to the first conducting wire and the second conductor, and a fourth conducting wire electrically connected to the third conducting wire and the second conductor, wherein the third conducting wire, the fourth conducting wire and the second conductor are configured to form a second loop corresponding to the inductor for tuning the inductance. | 12-03-2015 |
20150324308 | SOLID STATE DRIVE CONTROLLING CIRCUIT AND RELATED SOLID STATE DRIVE DEVICE AND SOLID STATE DRIVE ACCESS SYSTEM - A solid state drive (SSD) controlling circuit and related SSD device and SSD access system are disclosed. The SSD controlling circuit includes: an AHCI (advance host controller interface) controlling circuit for coupling with a PCIe (peripheral component interconnect express) interface; and a flash memory controlling circuit coupled with the AHCI controlling circuit and configured to operably control accessing operations of one or multiple flash memory arrays of a solid state drive. The AHCI controlling circuit transmits an indication message to a host device through the PCIe interface. The indication message is configured to declare that the AHCI controlling circuit is currently coupled with M solid state drives, wherein M is an integer greater than 1 and less than 32. | 11-12-2015 |
20150296329 | WIRELESS COMMUNICATION SYSTEM AND RELATED WIRELESS DEVICE - A wireless communication system and related wireless devices are disclosed. The wireless communication system includes: a source wireless device configured to operably insert an auto-pairing request and one or more source Bluetooth device addresses into one or more predetermined advertising packets to form one or more target advertising packets, and configured to operably transmit the target advertising packets; and a destination wireless device configured to operably receive and parser the target advertising packets to extract the auto-pairing request and the one or more source Bluetooth device addresses. The destination wireless device performs an auto-pairing procedure with the source wireless device according to the auto-pairing request and the one or more source Bluetooth device addresses to establish a Bluetooth bond with the source wireless device. Each of the predetermined advertising packets is an advertising indication (ADV_IND) packet, a non-connectable advertising indication (ADV_NONCONN_IND) packet, or a discoverable advertisement indication (ADV_DISCOVER_IND) packet. | 10-15-2015 |
20150296073 | BLUETOOTH REMOTE CONTROL SYSTEM AND RELATED DEVICE - A Bluetooth remote control system and related transmitting-end Bluetooth device and receiving-end Bluetooth device are disclosed. The transmitting-end Bluetooth device includes: a Bluetooth transmitting circuit; a receiving interface configured to operably receive a user trigger signal; a packet generating circuit configured to operably insert a power on request into one or more predetermined advertising packets to form one or more target advertising packets; and a Bluetooth control circuit configured to operably control the Bluetooth transmitting circuit to transmit the one or more target advertising packets. Each of the predetermined advertising packets is an advertising indication (ADV_IND) packet, a non-connectable advertising indication (ADV_NONCONN_IND) packet, or a discoverable advertisement indication (ADV_DISCOVER_IND) packet. | 10-15-2015 |
20150295538 | LOW-VOLTAGE AMPLIFIER AND METHOD THEREOF - An amplifier is provided having a first mixed-length MOS device set for receiving an input signal and outputting an output signal, and a first load for providing termination for the output signal, wherein the first mixed-length MOS device set comprises a parallel connection of a plurality of MOS devices having different channel lengths including at least a short channel length MOS device and a long channel length MOS device. In one configuration, a threshold voltage of the short channel length MOS device is greater than a threshold voltage of the long channel length MOS device. A related method is also provided. | 10-15-2015 |
20150280684 | SIGNAL-TRANSMISSION-LINE STRUCTURE AND ELECTRONIC DEVICE USING THE SAME - A signal-transmission-line structure includes a substrate, a through-silicon via (TSV) trench, a conductive substance, at least a conductor wire, and a dielectric layer. The substrate has a first surface and a second surface opposite to each other. The TSV trench is formed in the first surface of the substrate and extends along the first surface. The bottom surface of the TSV trench is located between the first surface and the second surface of the substrate. The TSV trench is filled with the conductive substance to form a transmission line. The conductor wire is located above the transmission line. The dielectric layer is located on the first surface of the substrate, and separates the conductor wire from the transmission line. | 10-01-2015 |
20150244367 | Method and Apparatus for Equalizing a Level Shifted Signal - A method and apparatus are provided for equalizing an output of a level shifter so as to obtain a symmetrical transition. In one implementation, a transition equalizing inverter includes: an NMOS for establishing a high-to-low transition for an equalized signal in response to a low-to-high transition of an asymmetrical signal; a delay circuit for outputting a delayed signal in response to the asymmetrical signal; and a PMOS for establishing a low-to-high transition for the equalized signal in response to a high-to-low transition of the delayed signal, wherein a delay introduced by the delay circuit offsets a timing mismatch between a low-to-high transition and a high-to-low transition of the asymmetrical signal. In an embodiment, the delay circuit comprises a transmission gate. A corresponding method is also provided. | 08-27-2015 |
20150215972 | METHOD FOR ESTABLISHING NETWORKING CONNECTION - A method for establishing a networking connection includes: utilizing a mobile communication device to wirelessly communicate with a wireless access point to establish a networking connection between the mobile communication device and the wireless access point; utilizing the mobile communication device to encode a profile of a wireless local area network (WLAN) corresponding to the wireless access point to generate one or more profile encoded packets; utilizing the mobile communication device to transmit the one or more profile encoded packets; utilizing a wireless communication device to receive the one or more profile encoded packets; utilizing the wireless communication device to parse the one or more profile encoded packets to obtain the profile of the WLAN; and utilizing the wireless communication device to connect to the wireless access point according to the profile of the WLAN to establish a networking connection between the wireless communication device and the wireless access point. | 07-30-2015 |
20150188694 | MULTI-LANE SERIAL DATA LINK RECEIVER AND METHOD THEREOF - A serial data link receiver and method are provided. In one implementation, the receiver includes a first equalizer for receiving a first received signal and outputting a first equalized signal, and a second equalizer for receiving a second received signal and outputting a second equalized signal. The receiver further includes an analog CDR (clock-data recovery) circuit for receiving the first equalized signal and outputting a first recovered bit stream and a first recovered clock generated in accordance with an analog control voltage, and a digital CDR circuit for receiving the second equalized signal and the first recovered clock and outputting a second recovered bit stream and a second recovered clock based on selecting a phase of the first recovered clock in accordance with a digital phase selection signal. | 07-02-2015 |
20150156042 | BINARY SIGNAL DETECTION BASED ON NON-UNIFORM ADC - In an embodiment, a receiver comprises: a linear equalizer for receiving an input signal and outputting a partly equalized signal; a VGA (variable-gain amplifier) for receiving the partly equalized signal and outputting an amplitude-adjusted signal in accordance with a gain control signal; a non-uniform ADC (analog-to-digital converter) for receiving the amplitude-adjusted signal and outputting a digitized signal; and a DSP (digital signal processing) circuit for receiving the digitized signal and outputting a bit stream by performing a signal detection and establishing the gain control signal by performing an amplitude comparison. The non-uniform ADC has a lower precision when the amplitude-adjusted signal lies in a region where the signal detection is of a higher confidence, and has a higher precision when the amplitude-adjusted signal lies in a region where the signal detection is of a lower confidence. In an embodiment, the DSP circuit includes a decision feedback equalizer. | 06-04-2015 |
20150155877 | PHASE LOCK LOOP DEVICE WITH CORRECTING FUNCTION OF LOOP BANDWIDTH AND METHOD THEREOF - A phase lock loop (PLL) device with correcting function of loop bandwidth and method thereof is related to the method including generating an output signal by a PLL circuit according to a reference signal and a feedback signal, modulating a feedback coefficient to unlock the feedback signal and the reference signal, detecting two valid crossovers of a phase difference between the reference signal and the feedback signal, calculating an oscillation frequency according to the two valid crossovers, and setting a control parameter of the PLL circuit according to the oscillation frequency. The feedback signal is related to the output signal, and there is the feedback coefficient between the feedback signal and the output signal. | 06-04-2015 |
20150146481 | METHOD AND APPARATUS FOR SENSING TUNNEL MAGNETO-RESISTANCE - In one embodiment, an apparatus comprises: an MRAM (magnetic random access memory) cell array comprising a plurality of MRAM cells including a calibration cell and a plurality of data cells; a reference MRAM cell controlled by a control signal; and a sensing-amplifier/latch; wherein: said plurality of data cells are used for storing user data; the calibration cell is used for a calibration purpose; the reference MRAM cell serves as a reference for comparison with a MRAM cell selected within the MRAM cell array; the sensing-amplifier/latch outputs a logical signal based on comparing a resistance of the MRAM cell selected within the MRAM cell array and a resistance of the reference MRAM cell; and the control signal is established in a calibration process by comparing a resistance of the calibration cell with the resistance of the reference MRAM cell. | 05-28-2015 |
20150092067 | IMAGE SHARING SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT - A computer program product includes: a receiving module for utilizing a communication circuit to receive a photographing positions distribution information; an option object generating module for utilizing a control circuit to generate multiple option objects; an arranging module for utilizing the control circuit to generate a graphic user interface including the multiple option objects and one or more reference indicators according to the photographing positions distribution information; and a displaying control module for utilizing a display device to display the graphic user interface. When the display device displays the graphic user interface, if an input device receives a shift command inputted by a user, the display controlling module controls the display device to move at least a portion of the option objects on the graphic user interface toward a same side and to change position or content of at least one reference indicator. | 04-02-2015 |
20150081929 | CONTROL CIRCUIT AND CONTROL METHOD FOR ADAPTIVELY ADJUSTING PARAMETER SETTING OF PCI-E DEVICE - A control circuit for a peripheral component interconnect express (PCI-E) device includes a power detecting unit and a parameter adjustment unit. The power detecting unit is coupled to a wireless communication transmitter, and arranged to detect a spectrum intensity value of an output spectrum of the wireless communication transmitter. The parameter adjustment unit is coupled to the power detecting unit, and arranged to produce at least one control signal according to the spectrum intensity value and adaptively adjust a parameter setting of the PCI-E device in accordance with the at least one control signal. | 03-19-2015 |
20150061787 | METHOD AND APPARATUS FOR SUPPRESSING A DETERMINISTIC CLOCK JITTER - A method for generating an output clock comprising: detecting a timing difference between a first input clock and a second input clock to generate a phase error signal; generating a masked phase error signal by masking the phase error signal based on a deterministic jitter indicator signal; generating an oscillator control signal by filtering the masked phase error signal; and generating the output clock in accordance with the oscillator control signal. | 03-05-2015 |
20150050900 | VOLTAGE REGULATING CIRCUIT AND METHOD THEREOF - A voltage regulating circuit and a method thereof are provided. The voltage regulating circuit includes: a tank circuit, an error amplifier, an output circuit, and a feedback circuit. The tank circuit provides a fixed voltage. The error amplifier generates an amplified voltage according to a reference voltage and a feedback voltage. The output circuit converts a supply voltage into an output voltage in response to at least one of the amplified voltage and the fixed voltage. The feedback circuit generates a feedback voltage according to the output voltage. | 02-19-2015 |
20150049620 | METHOD FOR ESTIMATING CABLE LENGTH IN ETHERNET SYSTEM AND RECEIVER THEREOF - A method for estimating cable length in an Ethernet system and a receiver thereof are applicable to an Ethernet system. The method for estimating cable length includes obtaining a channel tap from channel information of a feedback equalizer in the Ethernet system and estimating a cable length according to the channel tap, a first coefficient and a constant. | 02-19-2015 |
20150009904 | CHANNEL MAP GENERATION METHOD AND APPARATUS THEREFOR - A channel map generation method includes: performing a power spectrum density detection on a plurality of channels in a frequency band, to generate a first channel map; and performing a first smoothing operation on the first channel map by a first window size to generate a second channel map. The first smoothing operation includes: grouping channels of the first channel map into a plurality of channel groups according to the first window size; and according to the number of good channels or bad channels in each of the channel group, deciding to retain channel determinations in the first channel map of the channel group, or re-designating all the channels of the channel group, so as to generate the second channel map. | 01-08-2015 |
20140375365 | OVERSAMPLING METHOD FOR DATA SIGNAL AND OVERSAMPLING APPARATUS THEREOF - An oversampling method for data signal includes oversampling data strobe signal and data signal according to sampling phases to generate first and second sampling results, performing edge detection on the first and second sampling results to obtain first and second edge positions where edges are detected, calculating and storing first offset according to the first edge position and the corresponding second edge position when the second edge position are obtained, using first offset obtain in a previous sampling cycle as the first offset in a current sampling cycle when the second edge position aren't obtained, calculating first sampling point according to the first edge position; calculating second sampling point according to the first sampling point and the corresponding first offset, and selecting and outputting the corresponding second sampling results according to the second sampling point. | 12-25-2014 |
20140341263 | CALIBRATION METHOD PERFORMING SPECTRUM ANALYSIS UPON TEST SIGNAL AND ASSOCIATED APPARATUS FOR COMMUNICATION SYSTEM - A calibration method for calibrating a communication system includes: generating a test signal at a transmitter; configuring at least one calibration coefficient at the transmitter; configuring at least one calibration coefficient at the receiver; transmitting the test signal to a receiver via the calibration coefficient; performing a spectrum analysis upon the test signal received by the receiver to generate a spectrum analysis result; and adjusting the calibration coefficient according to the spectrum analysis result to calibrate the transmitter. In addition, a calibration method is also provided for calibrating a receiver of a communication system, and related calibration apparatuses are further provided. | 11-20-2014 |
20140327560 | SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER (SAR ADC) AND METHOD THEREOF - A SAR ADC and a method thereof are provided. Particularly, in each bit determining duration of last several bit determining durations, a comparer is used to consecutively compare a first potential with a second potential on a sampling and digital-to-analog converting circuit a plurality of times to obtain a plurality of comparison results, and then an SAR control circuit generates a corresponding output bit according to the obtained plurality of comparison results. | 11-06-2014 |
20140327472 | FREQUENCY DETECTION APPARATUS WITH INTERNAL OUTPUT VOLTAGE WHICH CHANGES ALONG WITH INPUT SIGNAL FREQUENCY - A frequency detection apparatus includes: a constant current generator, arranged for providing a constant current to a voltage output terminal; a first capacitor, coupled between the voltage output terminal and a first reference voltage; a first transistor, which has a first connection terminal coupled to the voltage output terminal, a control terminal coupled to an input signal; a second connection terminal, coupled between the second connection terminal of the first transistor and the first reference voltage; a second transistor, which has a first connection terminal coupled to the second connection terminal of the first transistor, a second connection terminal coupled to the first reference voltage, a control terminal coupled to an inverted input signal, which is obtained by inverting the input signal; wherein a voltage output of the voltage output terminal changes with an input signal frequency of the input signal. | 11-06-2014 |
20140320330 | SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER FOR PROGRAMMABLY AMPLIFYING AMPLITUDE OF INPUT SIGNAL AND METHOD THEREOF - Disclosed are a successive-approximation-register (SAR) analog-to-digital converter (ADC) for programmably amplifying an amplitude of an input signal and a method thereof. During a sampling phase, a bottom plate of at least one capacitor in a capacitor array is connected electrically to an input signal, so that the capacitor array samples and amplifies the input signal, so as to lower a required sampling capacitor or reduce noise generation. | 10-30-2014 |
20140307867 | ANALOG FRONT-END TRANSMITTER AND A CONNECTION METHOD OF AN X-DIGITAL SUBSCRIBER LINE HAVING A PRE-DISTORTION MECHANISM - A Pre-distortion mechanism for transmit path non-linearity in xDSL AFE is disclosed in the present invention. The AFE includes a line driver and a pre-distortion signal generator. The line driver receives an input differential signal and generates an output differential signal. The input differential signal includes a first input signal and a second input signal. The output differential signal includes a first output signal and a second output signal. The line driver receives the first input signal to generate the first output signal and receives the second input signal to generate the second output signal. The pre-distortion signal generator is coupled to input ends and output ends of the line driver. The pre-distortion signal generator generates a pre-distortion signal according to a first difference between the first input signal and the first output signal, and a second difference between the second input signal and the second output signal so as to adjust an output state of the analog front-end transmitter having a pre-distortion mechanism. | 10-16-2014 |
20140307827 | COMMUNICATION DEVICE AND METHOD FOR CONFIGURING DATA TRANSMISSION - A communication device includes a plurality of host control interfaces, an interface detector, and a transmitter. The plurality of host control interfaces selectively connect to a connection interface of a host. The interface detector is coupled to the plurality of host control interfaces and utilized for determine an interface specification of the connection interface to generate a detection result. The transmitter is coupled to the interface detector and supports a plurality of transmission power levels. The transmitter is utilized for determining a plurality of transmission configurations, and selecting one of the transmission configurations to communicating with a receiver, wherein each of the transmission configurations determines a transmission power level configuration of the transmitter. | 10-16-2014 |
20140307765 | WIRELESS TRANSMISSION SYSTEM, AND METHOD FOR DETERMINING DEFAULT GAIN OF WIRELESS TRANSMISSION SYSTEM - A method for determining a default gain of a wireless transmission system is provided. The wireless transmission system includes a signal transmission path and a signal feedback path coupled to the signal transmission path. The signal transmission path includes a power amplification circuit and a gain stage having a plurality of transmission gains. The method includes the following step: setting a gain of the gain stage as a specific transmission gain of the transmission gains; transmitting a plurality of test signals through the signal transmission path in sequence to generate a plurality of amplified test signals, wherein at least a portion of powers of the test signals correspond to the transmission gains, respectively; receiving the amplified test signals through the signal feedback path in sequence, and accordingly obtaining corresponding signal gains; and determining a default gain of the gain stage according to the signal gains. | 10-16-2014 |
20140300418 | AUTO GAIN ADJUSTING DEVICE AND METHOD THEREOF - An auto gain adjusting device and method is disclosed. The auto gain adjusting device comprises a predistorter, a gain unit, a power amplifier, a receiving unit and a calculation unit. The predistorter generates a plurality of test signals in a calibration mode, wherein the powers between a current test signal and a previous test signal includes a first difference value. The gain unit provides a substantially constant gain value to the current test signal and the previous test signal to generate a current amplified test signal and a previous amplified test signal. The power amplifier amplifies the current amplified test signal and the previous amplified test signal to generate a first transmitting signal and a second transmitting signal. The receiving unit converts the first transmitting signal and the second transmitting signal into a first baseband signal and a second baseband signal respectively. The calculation unit calculates a second difference value between powers of the first baseband signal and the second baseband signal, and compares the second difference value with the first difference value to determine whether the substantially constant gain value causes the plurality of test signals to be operated in a linear region and a compression region of the power amplifier. | 10-09-2014 |
20140300397 | CLOCK GENERATOR AND METHOD THEREOF - A clock generation device includes a first delay unit, a frequency divider, an angle delay unit and a first calculating unit. The first delay unit receives an input clock and delays the input clock by a first preset period to generate an input delay clock. The frequency divider divides a frequency of the delay clock to generate a first frequency-divided clock and a second frequency-divided clock. A frequency of each of the first frequency-divided clock and the second frequency-divided clock is a preset multiple of the input delay clock. The angle delay unit delays the first frequency-divided clock by a second preset period to generate a first delay clock. The first calculating unit determines a trigger time of a first edge of a first output clock with reference to voltage levels of the first frequency-divided clock and the first delay clock and determines a falling time of a second edge of the first output clock with reference to voltage levels of the input clock and the first delay clock. | 10-09-2014 |
20140288773 | Automotive Electronic System and Power Supply Method Thereof - An automotive electronic system and a power supply method thereof is related to the power supply method including outputting an interface signal to an automotive network, enabling a first switching regulator according to a first control signal from a control chip and/or the interface signal on the automotive network, supplying power to a network switch based on a first voltage by the first switching regulator when the first switching regulator is enabled, enabling a second switching regulator according to a second control signal from an electronic application module and/or the interface signal on the automotive network, and supplying power to the electronic application module based on the first voltage by the second switching regulator when the second switching regulator is enabled. The network switch and the electronic application module are connected to each other by the automotive network. | 09-25-2014 |
20140284763 | INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD - The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, an inductor, and a redistribution layer (RDL). The inductor is formed above the semiconductor substrate. The RDL is formed above the inductor and has a specific pattern to form a patterned ground shield (PGS). The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming an inductor above the semiconductor substrate; and forming redistribution layer (RDL) having a specific pattern above the inductor to form a patterned ground shield (PGS). | 09-25-2014 |
20140284762 | INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD - The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of deep trenches, and an inductor. The deep trenches are formed in the semiconductor substrate and arranged in a specific pattern, and the deep trenches are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of deep trenches in the semiconductor substrate and arranging the deep trenches in a specific pattern; filling the deep trenches with a metal material to form a patterned ground shield (PGS); and forming an inductor above the semiconductor substrate. | 09-25-2014 |
20140284761 | INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD - The present invention provides an integrated inductor and an integrated inductor fabricating method. The integrated inductor comprises: a semiconductor substrate, a plurality of through silicon vias (TSVs), and an inductor. The TSVs are formed in the semiconductor substrate and arranged in a specific pattern, and the TSVs are filled with a metal material to form a patterned ground shield (PGS). The inductor is formed above the semiconductor substrate. The integrated inductor fabricating method comprises: forming a semiconductor substrate; forming a plurality of TSVs in the semiconductor substrate and arranging the TSVs in a specific pattern; filling the TSVs with a metal material to form a PGS. forming an inductor above the semiconductor substrate. | 09-25-2014 |
20140269504 | METHOD AND MOBILE DEVICE FOR AUTOMATICALLY CHOOSING COMMUNICATION NETWORK - A method for automatically choosing a communication network is applicable to a mobile device. When receiving a communication request for a contact from a user interface, a processing unit determines a status of a network card module according to the communication request. When the network card module is enabled, the network card module sends a network packet and receives a corresponding response packet to determine whether the network card module is connected to the Internet. When the network card module is connected to the Internet, the network card module sends an inquiry packet to a voice over internet protocol (VoIP) proxy server and receives a corresponding response packet to determine whether the contact is online. When the contact is online, the network card module carries out the communication request through the VoIP proxy server. Otherwise, the communication request is carried out by a cellular phone module. | 09-18-2014 |
20140266350 | SIGNAL GENERATING CIRCUIT AND METHOD THEREOF - A signal generating circuit comprises a signal synchronizing module and a control circuit. The signal synchronizing module includes: a first delay path for delaying a target signal to generate a first delayed target signal by utilizing a first delay amount; a second delay path for delaying the target signal to generate a second delayed target signal by utilizing a second delay amount larger than the first delay amount; and a logic module, for gating the target signal to generate a first output signal according to the first delayed target signal, or gating the target signal to generate a second output signal according to the second delayed target signal. The control circuit controls the signal synchronizing module to output one of the first output signal and the second output signal according to phase difference between the target signal and a reference signal. | 09-18-2014 |
20140258575 | MASTER-SLAVE DETECTION METHOD AND MASTER-SLAVE DETECTION CIRCUIT - A master-slave detection method includes: every single time period, utilizing a random manner for determining whether a first device is used to transmit a specific pulse signal to a second device; every single time period, utilizing a random manner for determining whether the second device is used to transmit the specific pulse signal to the first device; when the first device receives at least one portion of the specific pulse signal earlier than the second device, setting the first device as a master device, stopping the master device from sending the specific pulse signal and utilizing the master device to start transmitting a specific sequence; and setting the second device as a slave device when the second device receives the specific sequence. The at least one portion of the specific pulse signal includes continuous single pulses. | 09-11-2014 |
20140258567 | DATA TRANSMISSION CIRCUIT AND DATA TRANSMISSION METHOD USING CONFIGURABLE THRESHOLD AND RELATED UNIVERSAL SERIAL BUS SYSTEM - A data transmission circuit applied to a universal serial bus (USB) system includes a memory, a direct memory access (DMA) engine and a USB controller. The memory is arranged for receiving and storing external data. The DMA engine is coupled to the memory, and arranged for controlling data retrieved from the memory. The USB controller is coupled to the DMA engine, and arranged for receiving data from the DMA engine and for transmitting the received data to a host. When the memory the stored data volume reaches a first threshold, the DMA engine starts continuously fetching data from the memory and transmitting it to the USB controller, until the data volume fetched by the DMA engine reaches a second threshold, or there is no data left in the memory. The second threshold is greater than the first threshold. | 09-11-2014 |
20140223398 | METHOD FOR DETERMINING INTERFACE TIMING OF INTEGRATED CIRCUIT AUTOMATICALLY AND RELATED MACHINE READABLE MEDIUM THEREOF - A method for determining an interface timing of an integrated circuit includes: reading a netlist file and a timing constraint file of the integrated circuit, and determining a first interface port of the netlist file according to the netlist file and the timing constraint file; determining a first transmission path and a load on the first transmission path between the first interface port and a specific circuit element in the netlist file; generating an interface circuit file according to the first transmission path and the load on the first transmission path; and calculating a first signal transmission time of the first transmission path out according to the interface circuit file. | 08-07-2014 |
20140210673 | DUAL-BAND ANTENNA OF WIRELESS COMMUNICATION APPARATUS - A dual-band antenna of a wireless communication apparatus includes a first radiation part for receiving or transmitting signals at a first frequency band; a second radiation part for generating a coupling effect together with the first radiation part to receive or transmit signals at a second frequency band having a center frequency lower than a center frequency of the first frequency band, wherein the second radiation part comprises multiple radiation sections, and at least one of the multiple radiation sections is positioned on a first plane; a feeding element for coupling with a signal receiving terminal of the wireless communication apparatus; and a shorting element for coupling with a fixed-voltage region of the wireless communication apparatus. The first radiation part does not physically contact with the second radiation part, and at least a portion of the first radiation part is not positioned on the first plane. | 07-31-2014 |
20140210562 | SINGLE-ENDED RING OSCILLATOR WITH FULLY DIFFERENTIAL SIGNAL - A single-ended ring oscillation device for generating a fully differential signal is provided. The single-ended oscillation device includes a single-ended ring oscillator and a phase processing unit. The single-ended ring oscillator includes an odd number of inverting delay units. The inverting delay units sequentially generate a first signal, a second signal and a third signal. The phase processing unit generates an intermediate signal according to the first signal and the third signal, and outputs the intermediate signal and a delayed version of the second signal as a fully differential signal. The intermediate signal and the second signal are opposite to each other in phase. | 07-31-2014 |
20140210560 | TRIPLE CASCODE POWER AMPLIFIER - A triple cascode power amplifier is provided. The triple cascode power amplifier includes a first-stage transistor pair, a second-stage transistor pair and a third-stage transistor pair. The first-stage transistor pair comprises two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities. The second-stage transistor pair is coupled with the first-stage transistor pair to form a first node and comprise two second-stage transistors coupled with each other to form a second node. The third-stage transistor pair is coupled with the second-stage transistor pair and comprises two third-stage transistors for outputting a differential signal. The first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component. The power amplifier transforms the differential signal into a single-ended signal for output. | 07-31-2014 |
20140203861 | CONTROL CIRCUIT FOR CONTROLLING A PUSH-PULL CIRCUIT AND METHOD THEREOF - A control circuit for generating a first control signal and a second control signal includes: an inverter, used for generating an inverted clock according to an input clock; a first delay circuit, used for generating a first delay control signal; a second delay circuit, used for generating a second delay control signal; a first mask circuit, used for generating a first mask signal according to the input clock; a second mask circuit, used for generating a second mask signal according to the inverted input clock; a first logic determining circuit, used for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; and a second logic determining circuit, used for generating the second control signal to the second delay circuit according to the first mask signal and the inverted clock. | 07-24-2014 |
20140198985 | IMAGE PROCESSING APPARATUS FOR PERFORMING COLOR INTERPOLATION UPON CAPTURED IMAGES AND RELATED METHOD THEREOF - An image processing method includes: receiving image data from a frame buffer, wherein each pixel of the image data has only one color information; estimating four second color information corresponding to up, down, left, and right sides of the target pixel respectively according to a first color information of the target pixel per se and color information of the neighboring pixels for a target pixel of the image data; calculating four color difference gradients corresponding to up, down, left, and right sides of the target pixel respectively according to the four second color information of the target pixel; determining an edge texture characteristic of the target pixel according to the four color difference gradients of the target pixel; and determining whether to modify the bit value of the first color information of the target pixel stored in a frame buffer according to an edge texture characteristic of the target pixel. | 07-17-2014 |
20140193079 | IMAGE CORRECTION METHOD USING APPROXIMATELY NON-LINEAR REGRESSION APPROACH AND RELATED IMAGE CORRECTION CIRCUIT - An image correction method arranged for processing an original image to obtain a corrected image includes steps: receiving the original image from an image sensor; regarding each pixel of the original image, calculating a horizontal distance and a vertical distance between the pixel and a reference point in the original image; determining a horizontal ratio parameter and a vertical ratio parameter according to the horizontal distance and the vertical distance between the pixel and the reference point in the original image; and performing an approximately non-linear regression calculation on the horizontal ratio parameter, the vertical ratio parameter and a coordinate of the pixel to obtain a position of the pixel in the corrected image. | 07-10-2014 |
20140192032 | OVERDRIVING CONTROL METHOD WITH IMAGE COMPRESSION CONTROL AND RELATED CIRCUIT - An overdriving control method includes: receiving an input image; determining whether the input image is a moving image or a still image, and generating a determining signal; dynamically using image compression process according to the determining signal; and dynamically using overdriving process according to the determining signal. An overdriving control circuit includes a receiving unit, arranged for outputting an input image; a determining unit, arranged for generating a determining signal by determining whether the input image is a moving image or a still image; an image compression processing unit, arranged for dynamically performing image compression process upon the input image according to the determining signal, and generating an image compression processing unit output; and an overdriving processing unit, arranged for dynamically performing an overdriving process upon the image compression processing unit output according to the determining signal, and generating an overdriving processing unit output. | 07-10-2014 |
20140184459 | DUAL BAND ANTENNA - A dual-band antenna, disposed in a substrate, is provided. The dual-band antenna includes: a feeding part and a slot antenna. The feeding part, disposed on a first side of the substrate, is used for feeding electromagnetic signals with a first resonance frequency and a second resonance frequency, wherein the second resonance frequency is substantially equal to twice the first resonance frequency. The slot antenna includes: a rectangular part with two long edges and two short edges, and a funnel part with a bottom edge, a top edge, and two side edges, wherein the bottom edge is shorter than the top edge, and the two side edges are equal in length substantially, the bottom edge of the funnel part is next to a short edge of the rectangular part, and a center line of the slot antenna corresponds to wavelength of the first frequency. | 07-03-2014 |
20140169766 | METHOD AND COMPUTER PROGRAM PRODUCT FOR ESTABLISHING PLAYBACK TIMING CORRELATION BETWEEN DIFFERENT CONTENTS TO BE PLAYBACKED - A method and a computer program product for controlling a timing correlation establishing device to establish playback timing correlation between different contents to be playbacked are disclosed. The method includes displaying a main event block corresponding to a main video clip; displaying an auxiliary event block corresponding to an auxiliary video clip; displaying a time marker on a location of a first time point on a timeline according to an editor's manipulation to an input device; and when the time marker is positioned on the location of the first time point, if the editor perform a set of predetermined manipulations to the input device, utilizing a control circuit to establish a first trigger timing data for indicating that an auxiliary display device has to begin playbacking the auxiliary video clip when the main video clip playbacked by a main display device reaches the first time point. | 06-19-2014 |
20140167993 | HYBRID DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF - Hybrid digital-to-analog converter and method thereof are provided. The hybrid digital-to-analog converter (DAC) includes a data processor, at least one first type DAC, at least one second type DAC, and an output circuit. The data processor processes an input digital signal to output at least one of first and second digital signals which are related to a higher bit portion and a lower bit portion of the input digital signal, respectively. If the data processor outputs the first digital signal to the first type DAC, the first type DAC converts the first digital signal. The at least one second type DAC receives and converts the second digital signal outputted from the data processor. The output circuit receives at least one output signal of the first and the second type DACs to output an output analog signal. | 06-19-2014 |
20140159985 | CURRENT BREAKER AND WIRELESS COMMUNICATION DEVICE HAVING THE SAME - A current breaker comprises a multi-layer printed circuit board (PCB), a ground plane, a metal component and a conductive via hole. The ground plane is disposed in a first metal layer of the multi-layer PCB and comprises a slot forming inductive impedance. The slot comprises an extended portion. The metal component is disposed in a second metal layer of the multi-layer PCB. Capacitive impedance is formed between the metal component and the ground plane. The projection of the metal component on the ground plane and the extended portion of the slot partially overlap. The conductive via hole penetrates the multi-layer PCB to connect metal component with the ground plane. The first and the second metal layers are any two metal layers of the multi-layer PCB. The inductive impedance formed by the slot and the capacitive impedance formed between the metal component and the ground plane create a parallel LC equivalent circuit. | 06-12-2014 |
20140145702 | CONSTANT CURRENT GENERATING CIRCUIT USING ON-CHIP CALIBRATED RESISTOR AND RELATED METHOD THEREOF - A constant current generating circuit and constant current generating method applied to a chip are provided, where the chip includes a first current generating circuit and a second current generating circuit, the second current generating circuit includes a transistor and an adjustable resistor. The constant current generating method includes: connecting an external resistor to the first current generating circuit to make the first current generating circuit use the external resistor to generate a first current; utilizing the second current generating circuit to generate a second current; adjusting the adjustable resistor in accordance with the first current and the second current to make the second current substantially equal to the first current, where the second current serves as a constant current of the chip. | 05-29-2014 |
20140129885 | SCAN CLOCK GENERATOR AND RELATED METHOD THEREOF - An exemplary scan clock generator for providing a plurality of on-chip scan clocks to a plurality of cells under test includes: a receiving circuit, arranged for receiving an off-chip scan clock; and a clock processing circuit, coupled to the receiving circuit and arranged for generating the on-chip scan clocks according to the received off-chip scan clock; wherein clock edges of the on-chip scan clocks are staggered from each other, and the scan clock generator and the cells under test are set in a same chip. | 05-08-2014 |
20140118047 | Method and Apparatus for Clock Transmission - Apparatus and methods are provided for an extraction circuit. In one configuration, an apparatus includes: an edge extraction circuit for receiving a first clock signal and outputting a second clock signal, wherein a duty cycle of the second clock is substantially smaller than a duty cycle of the first clock; a transistor for receiving the second clock signal and outputting a current signal; a transmission line for receiving the current signal on a first end and transmitting the current signal to a second end; a termination circuit for receiving the current signal at the second end and converting the current signal into a voltage signal; and an edge detection circuit for outputting a third clock by detecting an edge of the voltage signal. In one embodiment, the edge detection circuit comprises an inverter. In another embodiment, the edge detection circuit comprises a comparator. | 05-01-2014 |
20140118044 | DUTY CYCLE TUNING CIRCUIT AND METHOD THEREOF - A duty cycle tuning circuit and a method thereof are provided, in which the duty cycle tuning circuit includes multiple interpolation circuits, an edge detection circuit, and a delay chain. Each interpolation circuit receives multiple phase clocks, and interpolates an interpolation clock from two of the phase clocks. The phase clocks have the same frequency but different phases. The edge detection circuit is connected electrically to the delay chain, and generates an output clock according to an edge of the interpolation clock. | 05-01-2014 |
20140118030 | SAMPLING CIRCUIT AND SAMPLING METHOD - A sampling circuit and a sampling method are provided, where the sampling circuit includes a first delay chain, a second delay chain, and a half-speed binary-phase detector. The first delay chain is used to delay an input signal according to an up signal and a down signal, so as to generate a first delay signal; and the second delay chain is used to delay the first delay signal according to a preset delay value, so as to generate a second delay signal. The half-speed binary-phase detector is used to sample a data signal according to edge trigger of the first delay signal and that of the second delay signal, and generate an output signal, an up signal, and a down signal according to a sampling result of the data signal. | 05-01-2014 |
20140118006 | COMMUNICATION APPARATUS AND ASSOCIATED ESTIMATION METHOD - A communication apparatus and an associated estimation method are provided. The communication apparatus is electrically connected to a loading terminal and operates at a common bias voltage. The communication apparatus includes a transmitter, a connector, and a receiver. The connector includes a bridging circuit and a measurement circuit. The bridging circuit has a positive measurement end and a negative measurement end. The transmitter transmits an analog output signal. The receiver receives a common bias voltage during an estimation process. During the estimation process, the measurement circuit estimates a positive loading resistance and a negative loading resistance corresponding to the loading terminal according to a voltage difference between the common bias voltage and voltage at one of the positive measurement end and the negative measurement end. | 05-01-2014 |
20140097698 | MULTI-MODE POWER AMPLIFYING CIRCUIT, AND MULTI-MODE WIRELESS TRANSMISSION MODULE AND METHOD THEREOF - A multi-mode power amplifying circuit, and a multi-mode wireless transmission module and method thereof are provided. The multi-mode wireless transmission module includes the multi-mode power amplifying circuit and an antenna. In the multi-mode power amplifying circuit and the antenna, a first power amplifier is electrically connected between a signal input end and a first impedance matching circuit, and an output end of the first impedance matching circuit is electrically connected to the antenna. A second power amplifier is electrically connected to the signal input end, and a second impedance matching circuit is electrically connected between the second power amplifier and the first impedance matching circuit. A switching circuit is electrically connected to an input end of the second impedance matching circuit. The switching circuit switches on-off corresponding to an operation of the first power amplifier and an operation of the second power amplifier. | 04-10-2014 |
20140091812 | METHOD OF INTEGRATED CIRCUIT SCAN CLOCK DOMAIN ALLOCATION AND MACHINE READABLE MEDIA THEREOF - A method for deciding a scan clock domain allocation of an integrated circuit includes: utilizing a circuit netlist file and a timing constraints file of the integrated circuit to find out the amount of crossing paths between any two function clock domains of a plurality of function clock domains, and generate a clock domain report file; and grouping the plurality of function clock domains and allocating the plurality of function clock domains after being grouped into a plurality of scan clock domains according to the clock domain report file. | 04-03-2014 |
20140085118 | SUCCESSIVE APPROXIMATION ANALOG TO DIGITAL CONVERTER AND METHOD THEREOF - A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N−1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N−2)-th conversion unit includes a capacitor. The (N−1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N−1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N−2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N−1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N−1)-th conversion unit to generate the value of other bits to perform self linear compensation. | 03-27-2014 |
20140078391 | MOBILE HIGH-DEFINITION LINK DATA CONVERTER AND MOBILE HIGH-DEFINITION LINK DATA CONVERTING METHOD - An exemplary Mobile High-Definition Link (MHL) data converter includes: a data decoding circuit, arranged for decoding an input data according to an MHL specification, and outputting a decoded data; and a data parsing circuit, coupled to the data decoding circuit, arranged for parsing out a plurality of output data from the decoded data. An MHL data converting method includes: decoding an input data according to an MHL specification, and outputting a decoded data; and parsing out a plurality of output data from the decoded data. | 03-20-2014 |
20140073269 | WIRELESS TRANSCEIVER APPARATUS HAVING CIRCUIT UNIT FORMING FREQUENCY RESONANCE MODE WHEN OPERATED UNDER RECEPTION MODE - A wireless transceiver apparatus is provided. The wireless transceiver apparatus includes a signal transmitting circuit comprising an output port for outputting a transmission signal in a transmission mode, the signal transmitting circuit further comprising an inductive component. The wireless transceiver apparatus also includes a circuit unit coupled to the output port of the signal transmitting circuit, the circuit unit comprising a capacitive component and a signal receiving circuit comprising a receiving port for receiving a wireless communication signal in a reception mode. The output port is coupled to the receiving port, and the capacitive component in the circuit unit and the inductive component in the signal transmitting circuit form a resonator structure configured to operate in a frequency resonance mode during the reception mode. | 03-13-2014 |
20140070842 | ADJUSTABLE IMPEDANCE CIRCUIT AND IMPEDANCE SETTING METHOD FOR PROVIDING DIFFERENTIAL-MODE IMPEDANCE MATCHING AND COMMON-MODE IMPEDANCE MATCHING - An adjustable impedance circuit includes a calibration module, an impedance module, a first switch module and a second switch module. The calibration module is arranged to generate a calibration signal. The impedance module has a plurality of impedance elements. The first switch module is coupled to the calibration module, and is arranged to receive the calibration signal and make a first portion of the impedance elements be selectively coupled between a differential input port and at least one reference voltage according to the calibration signal. The second switch module is coupled to a common-mode voltage output node, and is arranged to receive a control signal and make a second portion of the impedance elements be selectively coupled between the common-mode voltage output node and the differential input port according to the control signal. | 03-13-2014 |
20140064423 | CLOCK AND DATA RECOVERY CIRCUIT SELECTIVELY CONFIGURED TO OPERATE IN ONE OF A PLURALITY OF STAGES AND RELATED METHOD THEREOF - An exemplary clock and data recovery circuit includes a serial data input node arranged for receiving a serial data; a reference clock input node arranged for receiving a reference clock; a control circuit arranged for generating a control signal to selectively configure the clock and data recovery to operate in one of a plurality of phases; a detective circuit arranged for generating a first adjusting signal while the clock and data recovery operates in a frequency locking phase, and for generating a second adjusting signal while the clock and data recovery circuit operates in a clock and data recovery phase; and a controllable oscillator arranged for generating a recovered clock according to the first adjusting signal in the frequency locking phase, and for generating the recovered clock according to the second adjusting signal in the clock and data recovery phase. | 03-06-2014 |
20140064115 | BANDWIDTH SELECTION METHOD - A bandwidth selection method includes capturing at least one first quality information corresponding to a first bandwidth, computing at least one first threshold value according to the at least one first quality information and at least one first weighting index, capturing at least one second quality information corresponding to a second bandwidth, comparing the first threshold value with the second quality information to obtain a first comparison result, and selecting one of the first bandwidth and the second bandwidth as a used bandwidth of a filter according to the first comparison result. | 03-06-2014 |
20140062550 | PHASE LOCKED LOOP - A phase locked loop comprises a loop filter and a charge pump circuit. The loop filter comprises a parallel capacitor, a serial resistor and a serial capacitor. A first terminal of the serial resistor is electrically connected to a first terminal of the parallel capacitor. A first terminal of the serial capacitor is electrically connected to the second terminal of the serial resistor, and a second terminal of the serial capacitor is electrically connected to a second terminal of the parallel capacitor. The charge pump circuit comprises a first charge pump and a second charge pump. The first charge pump is electrically connected to the first terminal of the serial resistor, and the second charge pump is electrically connected to the second terminal of the serial resistor. The phase lock loop can reduce output jitter and therefore increases the performance of the phase lock loop. | 03-06-2014 |
20140061881 | INTEGRATED CIRCUIT - An integrated circuit (IC) includes a packaging body, multiple interface connectors, a functional chip, and an electrostatic discharge (ESD) protection chip. The interface connectors are located on an outer surface of the packaging body. The functional chip has an electronic functional circuit, and the ESD protection chip has an ESD protection circuit. The ESD protection circuit is connected electrically to an interface connector serving as a data exchange path. | 03-06-2014 |
20140059418 | MULTIMEDIA ANNOTATION EDITING SYSTEM AND RELATED METHOD AND COMPUTER PROGRAM PRODUCT - A multimedia annotation editing system includes: a web server for providing an annotation editing page; and a webpage display device for communicating with the web server via internet, and for receiving and displaying the annotation editing page. If the webpage display device received an annotation template selection command, the webpage display device displays a preview of a target annotation template in an annotation preview area. The webpage display device modifies parameters of the target annotation template according to a user's manipulation and displays a modified preview of the target annotation template in the annotation preview area. The webpage display device transmits modified parameters of the target annotation template to the web server so that the web server generates a multimedia annotation according to the modified parameters of the target annotation template. | 02-27-2014 |
20140059254 | MODE SWITCHING METHOD OF ELECTRONIC DEVICE AND ASSOCIATED ELECTRONIC DEVICE - A mode switch method of an portable electronic device includes: when the electronic device is electrically connected to a host, setting the electronic device to start to be operated under a first mode; when the host has installed a operating system, detecting whether the host has a driver of the electronic device or not; when the host has the driver of the electronic device, the electronic device continues to be operated under the first mode; and when the host does not have the driver of the electronic device, switching the electronic device to be operated under a second mode. | 02-27-2014 |
20140059134 | MULTIMEDIA DELIVERY SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT FOR PROVIDING STATISTICAL GRAPH RELATED TO AUXILIARY MULTIMEDIA DATA - A multimedia delivery system includes a target data provider device for transmitting a target multimedia data; an auxiliary data provider device for transmitting an auxiliary multimedia data related to the target multimedia data, and for generating a related data distribution information; a first multimedia playback device for receiving the target multimedia data and the data distribution information, generating a statistical graph according to the data distribution information, playing the target multimedia data, and synchronously displaying at least a portion of the statistical graph; and a second multimedia playback device for receiving the auxiliary multimedia data and synchronously displaying related auxiliary multimedia data while the first multimedia playback device plays the target multimedia data. | 02-27-2014 |
20140054801 | ELECTRONIC DEVICE - An electronic device includes a core circuit and multiple pad units. The core circuit includes multiple core MOS and the multiple pad units are respectively electrically connected to the core circuit. Each pad unit includes at least one pad MOS. A core gate in each core MOS and a pad gate in each pad MOS extend along the same direction or extend parallel with each other. | 02-27-2014 |
20140035772 | SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER USING CAPACITOR ARRAY WITH SUB-CAPACITORS CONFIGURED BY CAPACITOR DISASSEMBLING AND RELATED METHOD THEREOF - A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2 | 02-06-2014 |
20140035771 | PREDICTIVE SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERSION DEVICE AND METHOD - A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to 1/2 of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits. | 02-06-2014 |
20140035767 | Successive-Approximation-Register Analog-to-Digital Converter and Method Thereof - A main ADC (analog-to-digital converter) for converting an analog input signal into a digital data, and an auxiliary ADC for converting the same analog input signal into an auxiliary digital data, wherein: the main ADC is a successive-approximation-register (SAR) ADC of a first resolution with a first conversion speed; the auxiliary ADC is of a second resolution with a second conversion speed; the second resolution is lower than the first resolution but the second conversion speed is higher than the first conversion speed; and the main ADC generates the digital data by undergoing a process of successive approximation comprising a plurality of steps including a fast-track step that is based on a value of the auxiliary digital data. | 02-06-2014 |
20140029691 | Communication System and Method for Cancelling Timing dependence of Signals - In a communication system, a timing-dependence cancelling module is included for cancelling timing-dependence of a transmission signal, so as to render a timing-dependent signal be capable of being utilized on communication systems. Besides, updating an echo cancelling parameter by applying an error difference variable and a data difference variable, or by directly decreasing a step-size coefficient, may also fulfill the purpose of reducing or eliminating timing dependence in a transmission signal of a communication system. | 01-30-2014 |
20140029657 | METHOD AND CIRCUIT OF CLOCK AND DATA RECOVERY WITH BUILT IN JITTER TOLERANCE TEST - A clock and data recovery circuit with built in jitter tolerance test is disclosed. Imposing jitter on a filter inside a CDR loop to cause phase disturbances to the clock and data recovery circuit, thereby to test the jitter tolerance of the clock and data recovery circuit. Accordingly, IC test cost is significantly reduced by increasing few circuit sizes. | 01-30-2014 |
20130342579 | MULTIMEDIA INTERACTION SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT CAPABLE OF AVOIDING UNEXPECTED INTERACTION BEHAVIOR - A multimedia interaction system includes: multiple electronic devices and a location detection circuit. The location detection circuit dynamically detects respective electronic device's spatial position and orientation. When an user instructs a source electronic device of the multiple electronic devices to transmit a target image object toward a selected direction, the source electronic device decides a target direction according to a location of a first candidate electronic device and the selected direction if a relative position between the first candidate electronic and the selected direction satisfies a first predetermined condition. The source electronic device transmits a target command corresponding to the target image object to a second candidate electronic device to perform corresponding multimedia interaction operations only if a relative position between the second candidate electronic and the target direction satisfies a second predetermined condition. | 12-26-2013 |
20130342515 | OVER-DRIVE CONTROLLER APPLIED TO A DISPLAY PANEL AND METHOD FOR OVER-DRIVE CONTROL THEREIN - An over-drive controller applied to a display panel and a method for over-drive control are provided. The over-drive controller includes an analyzing unit and an over-drive delta value determining unit. The analyzing unit is arranged for analyzing information of a current pixel in order to generate an over-drive information. The over-drive delta value determining unit is coupled to the analyzing unit, and is arranged for determining an over-drive delta value according to the over-drive information. Herein the over-drive information includes a position information or a field information of the current pixel. | 12-26-2013 |
20130328630 | POWER AMPLIFIER - A power amplifier is provided. The power amplifier includes a loading circuit, a first stage amplifying circuit, an analog pre-distorter, a loading circuit and a second stage amplifying circuit. The first stage amplifying circuit is coupled to the loading circuit to receive a first signal and output a second signal accordingly. The analog pre-distorter is coupled to the first stage amplifying circuit to detect the envelope of the second signal and generates a third signal according to the envelope. The second stage amplifying circuit is coupled to the first stage amplifying circuit to receive the second signal. The loading circuit is biased on the third signal. The gain of the first stage amplifying circuit is related to the third signal. | 12-12-2013 |
20130308731 | WIRELESS LAN COMMUNICATION DEVICE, RELEVANT SIGNAL PROCESSING CIRCUIT, AND METHOD THEREOF - A wireless LAN communication device includes an amplifying circuit, an interference detection circuit, a false alarm counting circuit, and a control circuit. The amplifying circuit is configured to operably provide a gain to wireless signals. The interference detection circuit is configured to operably detect adjacent channel interference signals to generate a detection result. The false alarm counting circuit is configured to operably calculate a number of false alarms incurred by the adjacent channel interference signals. The control circuit is configured to operably configure the gain of the amplifying circuit according to the detection result and the number of false alarms. | 11-21-2013 |
20130298095 | METHOD FOR CHECKING I/O CELL CONNECTIONS AND ASSOCIATED COMPUTER READABLE MEDIUM - A computer readable medium includes a program code for checking whether an I/O cell of a chip design has a connection error or not, where the chip design includes a plurality of I/O cells and a plurality of blocks, and when the program code is executed by a processor, the program code executes following steps: checking a connection between the I/O cell and a block by utilizing a check item corresponding to an attribute of the I/O cell to generate a checking result; and determining whether the I/O cell has a connection error according to the checking result. | 11-07-2013 |
20130290535 | APPARATUS AND METHOD FOR MANAGING AN ACCESS CONTROL LIST IN AN INTERNET DEVICE - An executing apparatus coupled to a main control unit for managing an access control list (ACL) is provided. The executing apparatus is utilized for receiving a specific command transmitted from the main control unit and managing a plurality of rule information of the ACL stored in a storage circuit according to the specific command received. | 10-31-2013 |
20130285630 | VOLTAGE REGULATING APPARATUS WITH ENHANCEMENT FUNCTIONS FOR TRANSIENT RESPONSE - A voltage regulating apparatus is disclosed. The voltage regulating apparatus includes: a power transistor having a control terminal, a first terminal for receiving a power supply, and a second terminal for providing an output voltage; a feedback circuit coupled to the second terminal, configured for providing a feedback voltage according to the output voltage; an amplifier having a source current unit and a sink current unit, configured for driving the power transistor through the control terminal by use of the source and sink current units according to a reference voltage and the feedback voltage; and a transient enhancement unit configured for monitoring the source and sink current units, and regulating a voltage at the control terminal according to the monitored result. | 10-31-2013 |
20130281144 | CHANNEL SELECTION METHOD USING CHANNEL QUALITY INFORMATION OF NEIGHBORING CHANNELS AND RELATED CHANNEL SELECTION DEVICE - A channel selection method includes steps of generating a plurality of test carriers on a plurality of different candidate channels, respectively; obtaining a plurality of channel quality information corresponding to the plurality of test carriers, respectively; generating a test result according to the plurality of channel quality information; and selecting a target channel from the plurality of candidate channels according to the test result. | 10-24-2013 |
20130271200 | SWITCHED CAPACITOR CIRCUIT UTILIZING DELAYED CONTROL SIGNAL AND INVERTING CONTROL SIGNAL FOR PERFORMING SWITCHING OPERATION AND RELATED CONTROL METHOD - A switched capacitor circuit includes an inverter, a first capacitor, and a first switch unit. The inverter is arranged to receive a control signal to generate an inverting control signal corresponding to the control signal. The first capacitor is coupled between a first output port and a first node. The first switch unit is arranged to receive a first input signal and a second input signal, and selectively couple the second input signal to the first node according to the first input signal. The first input signal is determined by one of the control signal and the inverting control signal, and the second input signal is determined by the other of the control signal and the inverting control signal. | 10-17-2013 |
20130268857 | MULTIMEDIA CONTENT PROVIDING DEVICE, MULTIMEDIA CONTENT PROVIDING METHOD, AND RELEVANT COMPUTER PROGRAM PRODUCT - A multimedia providing device includes a communication device, an access link generating device, a play control device, and an information display control device. The communication device receives a multimedia content, a multimedia information, a display time code, and an identification number of a recipient. The access link generating device generates the access link of the multimedia content and transmits it to the recipient. The play control device receives a play instruction corresponding to the multimedia content and configures the multimedia content to be transmitted to a multimedia content display device. The information display control device configures a multimedia information providing device to transmit the multimedia information to a portable information display device according to the display time code and the identification number of the recipient. Therefore, the portable information display device displays the multimedia information when the multimedia content display device displays a predetermined image frame of the multimedia content. | 10-10-2013 |
20130267185 | TRANSCEIVER HAVING AN ON-CHIP CO-TRANSFORMER - A transceiver formed on an integrated-circuit substrate is disclosed. The transceiver includes: a co-transformer comprising first, second and third windings which wrap each other but are separated from each other; a power amplifier coupled to the co-transformer; and a low-noise amplifier coupled to the co-transformer; wherein the co-transformer is configured for converting a first signal from the power amplifier into a second signal to be transmitted by an antenna when the transceiver is in its transmitter mode, and for converting a third signal from the antenna into a fourth signal to be outputted to the low-noise amplifier when the transceiver is in its receiver mode. | 10-10-2013 |
20130266286 | MULTI-SCREEN VIDEO PLAYBACK SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT FOR DYNAMICALLY GENERATING SCALED VIDEO - A multi-screen video playback system includes: a video playback device having a main display, a portable communication device having a screen, and a multi-screen display controlling server. The multi-screen display controlling server transmits a target video to the video playback device via a network so that the video playback device utilizes the main display to display the target video. While the main display displays the target video, if the multi-screen display controlling server received a selection message corresponding to a position of a partial region of the main display, the multi-screen display controlling server dynamically generates a scaled video corresponding to images displayed on the partial region and transmits the scaled video to the portable communication device via a network so that the portable communication device simultaneously displays the scaled video on the screen. | 10-10-2013 |
20130266285 | VIDEO PLAYBACK SYSTEM FOR ENHANCING DRAMA EFFECT AND RELATED COMPUTER PROGRAM PRODUCT - A video playback system for enhancing drama effect is disclosed, including: a video playback device having a main display to playback a target video; a first portable communication device having a first screen for displaying a first auxiliary image; and a drama effect enhancing server configured to operably transmit content of the target video to the video playback device via a network and to operably transmit content of the first auxiliary image to the first portable communication device via a network. When the target video playbacked on the main display reaches a first target point of time, the drama effect enhancing server instructs the first portable communication device to utilize the first screen to begin displaying the first auxiliary image. | 10-10-2013 |
20130266284 | MULTIMEDIA SYSTEM, RELEVANT MULTIMEDIA INFORMATION DISPLAY DEVICE AND MULTIMEDIA INFORMATION TRANSMISSION METHOD - A multimedia system is disclosed, having a multimedia playback device and a multimedia information display device. The multimedia playback device is used to provide the multimedia content received from a multimedia transmission device. The multimedia information display device has a display device, a wireless communication device, and a signal processing device for cooperating with the multimedia playback device. The wireless communication device of the multimedia information display device receives the multimedia information. The signal processing device configures the display device to display the multimedia information pertinent to the multimedia content played on the multimedia playback device. | 10-10-2013 |
20130265492 | MULTIMEDIA SYSTEM, RELEVANT MULTIMEDIA INFORMATION DISPLAY DEVICE AND MULTIMEDIA INFORMATION TRANSMISSION METHOD - A multimedia system includes a multimedia content providing device, a multimedia information providing device, and a multimedia information display device. The multimedia content providing device and the multimedia information providing device respectively provide the multimedia content and the related multimedia information. The multimedia information display device comprises a display device, a wireless communication device, and a signal processing device. The wireless communication device receives the multimedia content and the related multimedia information. The signal processing device configures the display device to display the multimedia content and the related multimedia information synchronously. Moreover, the signal processing device may also configure a multimedia content display device to display the multimedia content and configure the display device of the multimedia information display device to synchronously display the related multimedia information. | 10-10-2013 |
20130265488 | MULTI-SCREEN VIDEO PLAYBACK SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT - A multi-screen video playback system includes: a video playback device having a main display to playback a target video; a portable communication device having a screen; and a multi-screen display controlling server configured to operably establish a device group relationship between the video playback device and the portable communication device, to transmit the target video to the video playback device via a network, and to transmit an auxiliary video to the portable communication device via the network. The multi-screen display controlling server receives a notice information generated by the video playback device while the video playback device playbacks the target video, and instructs the portable communication device to begin displaying the auxiliary video on the screen according to the notice information. | 10-10-2013 |
20130265487 | VIDEO PLAYBACK SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT FOR JOINTLY DISPLAYING VIDEO WITH MULTIPLE SCREENS - A video playback system for jointly displaying video with multiple screens, includes multiple portable communication devices each comprises at least one screen; a location detection circuit for dynamically detecting respective portable communication device's spatial location and orientation; and a multi-screen display controlling server for dynamically generate multiple partitioned videos respectively corresponding to multiple non-overlap image areas of a target video according to detection results of the location detection circuit. The multi-screen display controlling server respectively transmits the multiple partitioned videos to the multiple portable communication devices. The multi-screen display controlling server controls the multiple portable communication devices to respectively display the multiple partitioned videos on the multiple screens to jointly display at least a portion of a visible area of the target video. | 10-10-2013 |
20130265132 | ON-CHIP TRANSFORMER HAVING MULTIPLE WINDINGS - An on-chip transformer formed on an integrated-circuit substrate is disclosed. The on-chip transformer includes: a multi-winding structure comprising first, second and third windings which are spatially separated from each other; and a guard ring surrounding the multi-winding structure; wherein the first and second windings function as a first transformer, and the second and third windings function as a second transformer. | 10-10-2013 |
20130265056 | APPARATUS AND METHOD OF LED SHORT DETECTION - An apparatus and method for detecting a status of at least one of a plurality of light emitting diodes (LEDs), is disclosed in embodiments of the invention. The apparatus includes a first node, a second node, a voltage generator, a current source and a first comparator. The voltage generator generates an output voltage to the first external circuit via the second node. The current source provides a current to the first external circuit via the first node to generate a first node voltage. The first comparator generates a first comparison result according to the first node voltage and a reference voltage, wherein the first comparison result indicates whether the status of at least one of the LEDs is short or not. | 10-10-2013 |
20130249506 | Integrated Switch-Capacitor DC-DC Converter and Method Thereof - An integrated switch-capacitor DC-DC converter and method are disclosed. In an embodiment, a converter includes a switch-capacitor network for receiving a source voltage and outputting a load voltage to a load circuit in accordance with a N-bit control code and a plurality of phase clocks, wherein N is an integer greater than 1, a load capacitor for holding the load voltage, a feedback network for generating a feedback voltage proportional to the load voltage, and a controller for receiving the feedback voltage and a reference voltage and outputting the N-bit control code in accordance with a clock phase of the plurality of phase clocks. | 09-26-2013 |
20130234755 | IMPEDANCE CALIBRATION DEVICE AND METHOD - An impedance calibration device includes: a variable impedance, an operational unit, an analog-digital converter, and a controller. The operational unit receives a first analog signal and a second analog signal, and performs a difference operation to generate an output voltage. The analog-digital converter generates an adjustment code according to the output voltage. The controller is coupled to the analog-digital converter and the variable impedance, and adjusts a resistance value of the variable impedance according to the adjustment code. | 09-12-2013 |
20130232422 | MULTIMEDIA INTERACTION SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT CAPABLE OF FILTERING MULTIMEDIA INTERACTION COMMANDS - A multimedia interaction system is disclosed, including: a plurality of member electronic devices; a plurality of deplays respectively arranged on the member electronic devices; and a location detection circuit configured to operably detect respective member electronic device's spatial position and orientation dynamically and to transmit detection results to at least one of the member electronic devices. When an user instructs a source electronic device of the member electronic devices to transmit a target image object toward a target direct, a candicate electronic device of the member electronic devices would execute a target command corresponding to the target image object to utilize a corresponding display to perform a multimedia operation corresponding to the target image object only if a relative position between the candicate electronic and the target direct satisfies a predetermined condition. | 09-05-2013 |
20130232223 | CROSS-PLATFORM MULTIMEDIA INTERACTION SYSTEM WITH MULTIPLE DISPLAYS AND DYNAMICALLY-CONFIGURED HIERARCHICAL SERVERS AND RELATED METHOD, ELECTRONIC DEVICE AND COMPUTER PROGRAM PRODUCT - A cross-platform multimedia interaction system with dynamically-configured hierarchical servers is disclosed, including: a central relay server (CRS); multiple electronic devices; and multiple displays respectively arranged in the multiple electronic devices. The CRS dynamically assigns one of the multiple electronic devices as a local relay server (LRS) and instructs the LRS to active a websocket server, and the CRS notifies the other electronic devices of a network address of the LRS. When the LRS actives the websocket server, other electronic devices establish one or more network sockets with the LRS. The multiple electronic devices communicate control parameters via the websocket server, generate corresponding images according to received control parameters, and respectively display the resulting images on the multiple displays. | 09-05-2013 |
20130229340 | MULTIMEDIA INTERACTION SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT CAPABLE OF AVOIDING UNEXPECTED INTERACTION BEHAVIOR - A multimedia interaction system is disclosed, including: a plurality of member electronic devices; a plurality of displays respectively arranged on the member electronic devices; and a location detection circuit configured to operably detect respective member electronic device's spatial location and orientation dynamically and to transmit detection results to at least one of the member electronic devices. When an user instructs a source electronic device of the member electronic devices to transmit a target image object toward a target direct, the source electronic device transmits a target command corresponding to the target image object to a candidate electronic device of the member electronic devices to perform corresponding multimedia interaction operations only if a relative position between the candidate electronic and the target direct satisfies a predetermined condition. | 09-05-2013 |
20130229325 | MULTIMEDIA INTERACTION SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT CAPABLE OF BLOCKING MULTIMEDIA INTERACTION COMMANDS THAT AGAINST INTERACTIVE RULES - A multimedia interaction system is disclosed, including: a plurality of member electronic devices; a plurality of deplays respectively arranged on the member electronic devices; a forwarding electronic device configured as a command transmission intermedium between the member electronic devices; and a location detection circuit configured to operably detect respective member electronic device's spatial position and orientation dynamically and to transmit detection results to at least one of the member electronic devices. When an user instructs a source electronic device of the member electronic devices to transmit a target image object toward a target direct, the forwarding electronic device transmits a target command corresponding to the target image object to a candidate electronic device of the member electronic devices to perform corresponding multimedia interaction operations only if a relative position between the candidate electronic and the target direct satisfies a predetermined condition. | 09-05-2013 |
20130223439 | ETHERNET COMMUNICATION CIRCUIT WITH AUTO MDI/MDIX FUNCTION - An Ethernet communication circuit includes: a current source; a first transistor coupled between a first node and a third node, and having a control terminal coupled with a first signal pin; a second transistor coupled between the first node and a fourth node, and having a control terminal coupled with a second signal pin; a third transistor coupled between a second node and the fourth node, and having a control terminal coupled with a third signal pin; a fourth transistor coupled between the second node and the third node, and having a control terminal coupled with a fourth signal pin; a first switch coupled between the third node and the current source; a second switch coupled between the fourth node and the current source; and a transconductance circuit for generating an output voltage according to the current passing through the first node and the current passing through the second node. | 08-29-2013 |
20130222023 | DIGITAL PHASE LOCK LOOP AND METHOD THEREOF - An apparatus of digital phase lock loop and method are provided. In one embodiment, an apparatus comprises: an analog-to-digital converter (ADC) for converting a voltage level of an output clock into a first digital word in accordance with a timing defined by a reference clock; a first digital loop filter for receiving the first digital word and outputting a control code; a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of the output clock with respect to a frequency of the reference clock; an adder for generating an offset control code by summing the control code with the offset code; and a digitally controlled oscillator for outputting the output clock in accordance with the offset control code. | 08-29-2013 |
20130215999 | METHOD FOR COMPENSATING MISMATCH OF IN-PHASE SIGNAL AND QUADRATURE SIGNAL OF TRANSMITTER/RECEIVER - A method for compensating mismatches of an in-phase signal and a quadrature signal of a transmitter/receiver is provided. The method includes: receiving a plurality of test signals to generate two groups of factors, respectively, where each group of factors is applied to two multipliers utilized for compensating a gain mismatch and a phase mismatch of the in-phase signal and the quadrature signal of the transmitter/receiver; then calculating a delay mismatch of the in-phase signal and the quadrature signal according to the two groups of factors. | 08-22-2013 |
20130214864 | SIGNAL AMPLIFYING CIRCUIT OF COMMUNICATION DEVICE - A signal amplifying circuit of a communication device is disclosed including: an amplifier comprising a first input terminal, a second input terminal, and an output terminal, wherein the input terminal is coupled with a fixed voltage level; a feedback circuit coupled with the second input terminal and the output terminal of the amplifier; a digital-to-analog converter (DAC); a signal processing circuit; a switch for selectively coupling the second input terminal of the amplifier with the DAC or the signal processing circuit; and a control unit coupled with the switch for controlling the operations of the switch. | 08-22-2013 |
20130203370 | WIRELESS COMMUNICATION RECEIVER AND METHOD THEREOF - A wireless communication receiver includes a circuit, an analog-to-digital converter (ADC) and a processing circuit. The circuit receives a wireless signal and outputs an analog signal according to a gain index. The ADC converts the analog signal to a digital signal. The processing circuit adjusts the gain index according to a clipping number of the ADC. | 08-08-2013 |
20130194040 | Limiting Amplifier And Method Thereof - A method including receiving an input signal; amplifying the input signal to generate an output signal using a cascade of a plurality of amplifier stages including a first amplifier stage and a last amplifier stage; generating a voltage signal by sensing the output signal in a noninvasive manner so that the sensing results in substantially no change to the output signal; generating a current signal from the voltage signal using a transconductance amplifier; and injecting the current signal into an output node of the first amplifier stage in a noninvasive manner so that the injecting results in substantially no change to an amplification function of the first amplifier stage. | 08-01-2013 |
20130188518 | ELECTRONIC DEVICE HAVING NETWORK AUTO-SWITCHING FUNCTIONS AND NETWORK AUTO-SWITCHING METHOD UTILIZED IN ELECTRONIC DEVICE - The disclosure provides an electronic device having network auto-switching functions and a network auto-switching method utilized in an electronic device. The electronic device comprises: a first network connecting unit having a first network transmission specification; and a second network connecting unit having a second network transmission specification different from the first network transmission specification. The network auto-switching method comprises: utilizing a detecting unit for detecting network connecting statuses of the first network connecting unit and the second network connecting unit to generate a detecting result; utilizing a network access unit for determining to select the first network connecting unit or the second network connecting unit to perform a network connecting operation or to not perform the network connecting operation at least according to the detecting result. | 07-25-2013 |
20130188027 | IMAGE DEPTH GENERATION DEVICE AND METHOD THEREOF - An image depth generation device and method thereof is disclosed in the present invention. The device includes at least a processing circuit and at least a calculator. The processing circuit receives an input image and determines a visual distance of a pixel Pi according to a color of the pixel in the input image and at least a reference value to generate a depth offset of each pixel. The calculator is coupled to the processing circuit and uses the depth offset of each pixel and a predetermined depth to generate an output depth value of each pixel in the input image. | 07-25-2013 |
20130187908 | IMAGE PROCESSING DEVICE AND METHOD THEREOF - An image processing device and method is disclosed. The image processing device includes a depth-of-interest (DOI) determining circuit and an image processing circuit. The DOI determining circuit generates a DOI distribution of the input image and corresponding depth information of the input image. The image processing circuit receives the input image and performs a predetermined image processing operation on the input image according to the DOI distribution to generate an output image. | 07-25-2013 |
20130185683 | Method of Generating Integrated Circuit Model - An integrated circuit test model is generated according to a circuit connection net-list, an isolation cell topology, and a pin voltage information spec file, so that the procedure of generating the integrated circuit test model can be time-saving, efficient, and fool-proof. Besides, while tracing a current path of a node of the circuit connection net-list, the generated integrated circuit test model can be more precise if certain limitations are added. | 07-18-2013 |
20130177325 | Method and Apparatus of Automatic Power Control for Burst Mode Laser Transmitter - An apparatus of automatic power control for burst mode laser transmitter and method are provided. In one implementation a method includes: generating an output current with a modulation pattern determined by a transmit data and a transmit enable signal, and a modulation level determined by a first control code and a second control code, wherein a light signal is generated in response to the output current; generating a first decision based on a comparison between a photodiode current and the first reference current, a second decision based on a comparison between the photodiode current and the second reference current, wherein the photodiode current is generated in accordance to the light signal; and generating the first control code and the second control code in response to the first decision and the second decision. | 07-11-2013 |
20130176878 | WIRELESS COMMUNICATION CIRCUIT SUPPORTING ANTENNA DIVERSITY - A wireless communication circuit for a wireless communication device having a plurality of antennas is disclosed. The wireless communication circuit includes: a transceiver for receiving and transmitting network packets; a control circuit for controlling the switching circuit to switch the transceiver among the antennas so that the transceiver receives the preamble of a first network packet; and a receiving signal strength detector for detecting the receiving signal strength value of respective antennas in respective receiving periods during the reception of the preamble conducted by the transceiver. If the receiving signal strength value of each antenna is less than a predetermined threshold, the control circuit selects an antenna with the maximum receiving strength value as a target antenna and controls the switching circuit to couple the transceiver to the selected target antenna so that the transceiver receives the rest of the first network packet through the target antenna. | 07-11-2013 |
20130173862 | METHOD FOR CLEANING CACHE OF PROCESSOR AND ASSOCIATED PROCESSOR - A method for cleaning a cache of a processor includes: generating a specific command according to a request, wherein the specific command includes an operation command, a first field and a second field; obtaining an offset and a starting address according to the first field and the second field; selecting a specific segment from the cache according to the starting address and the offset; and cleaning data stored in the specific segment. | 07-04-2013 |
20130170529 | TRANSMITTING METHOD AND TRANSMISSION SYSTEM USING THE SAME - A transmitting method and transmission system using the same is applied to selectively use a space block-coding module to transmit a transmitted data. Each data stream of the transmission data is transmitted using the transmitting paths, and the transmission qualities of the transmitting paths are detected to decide whether the space-block encoding module works or not. | 07-04-2013 |
20130169053 | DETECTION CONTROL DEVICE AND METHOD THEREOF - The present invention provides an auto-detection control apparatus, which receives an electric power from one of a system power source signal and an external device and performs a detection when coupled to the external device. The apparatus comprises a detection module, a power management module and a control module. The detection module generates a first result based on whether a first power signal from the external device exists, wherein the first result is related to whether the external device provides an electricity to itself. The power management module prevents a conflict between the system power source signal and the first power signal. The control module determines whether the electric power is supplied to the external device by the power management module based on the first result. | 07-04-2013 |
20130162454 | HIGH-SPEED SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF - In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data. | 06-27-2013 |
20130162337 | CHARGE PUMP CIRCUIT AND POWER-SUPPLY METHOD FOR DYNAMICALLY ADJUSTING OUTPUT VOLTAGE - A charge pump circuit and power-supply method for dynamically adjusting output voltage is related to the charge pump circuit having three power-supply modes with different power conversion efficiencies. When supplying power, a pump unit controls the electrical connecting relations of a first flying capacitor, second flying capacitor, first storage capacitor and second storage capacitor through a first clock and second clock with non-overlapping working phases, to convert a source voltage into a positive output voltage and negative output voltage, thereby providing one of the three power-supply modes. | 06-27-2013 |
20130162229 | CHARGE PUMP FEEDBACK CONTROL DEVICE AND METHOD USING THE SAME - Charge pump feedback control device and method are provided. The device is coupled to the charge pump unit which receives an input voltage so as to generate an output voltage and has switches and at least one capacitor, the device includes: a compensation unit, a modulation unit, and a phase control unit. The compensation unit receives the output voltage, compensates the output voltage for stability, and generates an error signal. The modulation unit receives the error signal, modulates the error signal, and correspondingly generates a modulation signal. The phase control unit receives the modulation signal so as to generate phase signal, and controls the plurality of switches of the charge pump unit according to the plurality of phase signal so as to generate the output voltage through the input voltage charging/discharging at least one capacitor of the charge pump unit. | 06-27-2013 |
20130128642 | Signal Level Detector and Method Thereof - A signal level detector and detecting method are provided. In one implementation a method includes receiving a differential input signal; incorporating two configurable rectifiers of the same circuit topology; configuring a first one of the two configurable rectifiers as a inverting rectifier to generate an inverting end of an output signal in response to an absolute value of the differential input signal; and configuring a second one of the two configurable rectifiers as a non-inverting rectifier to generate a non-inverting end of the output signal. | 05-23-2013 |
20130128401 | NETWORK COMMUNICATION DEVICE AND PRINTED CIRCUIT BOARD WITH TRANSIENT ENERGY PROTECTION THEREOF - A network communication device and printed circuit board are provided with transient energy protection. The network communication device includes a transceiver, a transformer, a connector, a spark gap, and a transient energy trigger circuit. The transformer is coupled between the transceiver and the connector. The spark gap and the transient energy trigger circuit are coupled in parallel, between the transformer and a ground end. Alternatively, the spark gap and the transient energy trigger circuit are coupled in parallel, between any two of differential signal lines of the transformer. The spark gap and the transient energy trigger circuit provide a multi-path structure for conducting away the transient energy. A first transient energy is conducted to the ground end through the transient energy trigger circuit, while a second transient energy is conducted to the ground end through the spark gap. | 05-23-2013 |
20130117586 | NETWORK ACCESS DEVICE WITH FLEXIBLE PRECISE LOW-POWER REMOTE WAKE-UP MECHANISM APPLICABLE IN VARIOUS APPLICATION LAYER HANDSHAKE PROTOCOLS - A network access device is disclosed, having a transceiving circuit, a demodulation circuit, and a control circuit. The transceiving circuit is used to receive network signals. The demodulation circuit is coupled with the transceiving circuit and used to generate data frames according to the network signals. The control circuit is coupled with the demodulation circuit and used to wake up one or more components of an electronic device when at least two fields of the data frame match predetermined values, or when the data frames are received in a predetermined order. | 05-09-2013 |
20130106525 | SINGLE-STAGED BALANCED-OUTPUT INDUCTOR-FREE OSCILLATOR AND METHOD THEREOF | 05-02-2013 |
20130106516 | Fast Settling Reference Voltage Buffer and Method Thereof | 05-02-2013 |
20130106515 | METHOD AND APPARATUS OF COMMON MODE COMPENSATION FOR VOLTAGE CONTROLLED DELAY CIRCUITS | 05-02-2013 |
20130099974 | SWITCHED BEAM SMART ANTENNA APPARATUS AND RELATED WIRELESS COMMUNICATION CIRCUIT - A switched beam smart antenna apparatus is disclosed including: a first, a second, a third, and a fourth beam adjusting elements substantially perpendicular to a substrate; a radiation strip positioned within an area surrounded by the first to fourth beam adjusting elements and substantially perpendicular to the substrate; a first beam control module positioned between the first beam adjusting element and the substrate; a second beam control module positioned between the second beam adjusting element and the substrate; a third beam control module positioned between the third beam adjusting element and the substrate; and a fourth beam control module positioned between the fourth beam adjusting element and the substrate. When the first beam control module turns on the first beam adjusting element, at least one of the second through the fourth beam control modules turns off corresponding beam adjusting element. | 04-25-2013 |
20130088274 | PHASE INTERPOLATOR, MULTI-PHASE INTERPOLATION DEVICE, INTERPOLATED CLOCK GENERATING METHOD AND MULTI-PHASE CLOCK GENERATING METHOD - A phase interpolator, multi-phase interpolation device, interpolated clock generating method and multi-phase clock generating method is related to a phase interpolator with a differential to single-ended converter, a load circuit, two differential pairs, a current source and at least a switch pair. By using the switch pair to control the current providing for the two differential pairs from the current source, and through regulating the load of the load circuit and/or the reference current of the current source, the intersection of a first signal and a second signal is in the overlap duration between a first input clock and a second input clock, so that uniform multi-phase output clock signal can be interpolated. | 04-11-2013 |
20130077668 | ADAPTIVE FILTER WITH REDUCED COMPUTATIONAL COMPLEXITY - An adaptive filter is disclosed, having a plurality of computation groups, a plurality of computation circuits, a summation circuit, a slicer circuit, an updating circuit, and a control circuit. Each computation group corresponds to an equalization parameter and has a plurality of memory cells. When the corresponding equalization parameter of a computation group is greater than a predetermined value, the control circuit configures the computation group and the computation circuit to collaboratively generate an output of the computation group. The summation circuit sums up the outputs of the computation groups to produce a filter output. The slicer circuit generates a slicer output according to the filter output. The updating circuit updates the equalization parameters according to the filter output and the slicer output. | 03-28-2013 |
20130076739 | METHOD AND APPARATUS FOR TRANSMITTING THREE-DIMENSIONAL IMAGE - A method for transmitting a three-dimensional (3D) image is provided. The 3D image is transmitted via an image transmission interface according to a 2D image data format. The method includes steps of: receiving a 2D image data and an image depth data; down-sampling the 2D image data to generate an image sampling data; and transmitting the 3D image comprising the image sampling data and at least one part of the image depth data via the image transmission interface. | 03-28-2013 |
20130076439 | Limiting Amplifier And Method Thereof - A limiting amplifier and method are provided. In one implementation an apparatus includes a plurality of amplifier stages including a first amplifier stage and a last amplifier stage configured in a cascade arrangement, and a transconductance amplifier, wherein the first amplifier stage is configured to receive an input signal; the last amplifier stage outputs an output signal; the transconductance amplifier is configured receive a voltage signal from the last amplifier stage via a first resistor; and the transconductance amplifier is configured to output a current signal to an output node of the first amplifier stage via a second resistor in a negative feedback manner. | 03-28-2013 |
20130073890 | SIGNAL SYNCHRONIZING DEVICE - A signal synchronizing device includes a trigger module for capturing an input signal according to a first clock signal which corresponds with the input signal so as to generate a trigger signal, a storage unit for forming a first pulse signal by pulling an output thereof to a first logic level according to the trigger signal, and by pulling the output thereof to a second logic level according to a feedback reset signal, and a synchronizing module for performing synchronous transfer according to the first pulse signal so as to output an output signal corresponding with frequency of a second clock signal, and for generating the feedback reset signal according to the output signal. | 03-21-2013 |
20130069727 | Transimpedance Amplifier and Method Thereof - A transimpedance method and apparatus are provided. In one implementation an apparatus includes a common-gate amplifier for receiving a first current from a first circuit node and outputting a second current to a second circuit node, and a load circuit coupled to the second circuit node, the load circuit comprising a diode-connected MOS (metal-oxide semiconductor field effect transistor), wherein a gate terminal of the MOS is coupled to a drain terminal of the MOS via a resistor. In one embodiment, a current-mode input is injected to the first circuit node and the apparatus further comprises a biasing circuit for outputting a substantially constant current to the first circuit node. | 03-21-2013 |
20130063193 | CALIBRATION DEVICE AND RELATED METHOD FOR PHASE DIFFERENCE BETWEEN DATA AND CLOCK - A calibration device and related method for a phase difference between data signal and clock signal are disclosed. An apparatus of the invention includes: an adjustable delay circuit for delaying at least one of a first input signal and a second input signal according to a delay control signal, and generating a first signal and a second signal; a phase detection circuit for detecting a phase difference between the first signal and the second signal to output a phase difference signal; a charge pump and a capacitor for outputting a control signal according to the phase difference signal; a comparison circuit for outputting a comparison result according to the control signal; and, a digital control circuit for outputting the delay control signal according to the comparison result. | 03-14-2013 |
20130044839 | WIRELESS APPARATUS AND PROCESSING METHOD THEREOF - The present invention relates to a wireless apparatus and the processing method thereof. The wireless apparatus according to the present invention comprises a demodulating circuit, a computing circuit, and a compensating circuit. The demodulating circuit receives and demodulates an input signal for producing a baseband signal. The computing circuit is coupled to the demodulating circuit and receives the baseband signal. It performs inner product on the baseband signal for producing an output signal. The compensating circuit is coupled to the computing circuit, and produces and transmits a compensation signal to the demodulating circuit according to the output signal for adjusting the demodulating circuit. Accordingly, by means of the computing circuit according to the present invention, erroneous outputs sent to the compensation circuit due to erroneous judgment of a signal received with large frequency deviation can he avoided effectively, and hence enhancing the efficiency of the wireless apparatus. | 02-21-2013 |
20130042076 | CACHE MEMORY ACCESS METHOD AND CACHE MEMORY APPARATUS - A cache memory access method is to be implemented by a cache memory apparatus that includes a data storage unit which includes a plurality of storage sets each including a plurality of storage elements corresponding respectively to a plurality of access ways. The method includes: receiving from a processer a target address; determining whether the data storage unit stores target data corresponding to the target address; receiving the target data from a main memory if negative; selecting a chosen way from the plurality of access ways according to whether the storage elements of the storage set which corresponds to the target address store valid data and whether the target address corresponds to a predefined lock range in the main memory; and writing the target data in the data storage unit based on the chosen way. | 02-14-2013 |
20130028507 | 2D to 3D IMAGE CONVERSION APPARATUS AND METHOD THEREOF - A 2D to 3D image conversion apparatus includes a data queue, a conversion unit and an offset calculation unit. The data queue receives and temporarily stores an input data value corresponding to a current pixel. The conversion unit outputs a current offset table corresponding to a current depth parameter of the current pixel. The current offset table includes (m+1) reference offsets corresponding to the current pixel and neighboring m pixels. The offset calculation unit selects one of the reference offsets corresponding to the current pixel in the current offset table and multiple previous offset tables as a data offset corresponding to the current pixel. The data queue selects and outputs an output data value corresponding to the current pixel according to an integer part of the data offset and the input data value. | 01-31-2013 |
20120326701 | Configurable Process Variation Monitoring Circuit of Die and Monitoring Method Thereof - The present invention discloses a configurable process variation monitoring circuit of a die and monitoring method thereof. The monitoring method includes a ring oscillator, a frequency divider and a frequency detector. The ring oscillator includes a plurality of first standard cells, a plurality of second standard cells and a plurality of multiplexers. The ring oscillator generates an oscillation signal in a first mode or a second mode according to a selection signal. The frequency divider is coupled to the ring oscillator and divides the oscillation signal by a value to generate a divided signal. The frequency divider is coupled to the frequency divider and counts periods of the divided signal by a base clock to generate an output value where the output value is related to the process variation. | 12-27-2012 |
20120304144 | Power Mesh Managing Method - The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer. | 11-29-2012 |
20120293155 | MULTI-CHANNEL POWER SUPPLY AND CURRENT BALANCING CONTROL METHOD THEREOF - The multi-channel power supply comprises a first channel, a second channel, a current sensing module, a current average control circuit, and a modulator. The first channel and the second channel respectively transform an input voltage into an output voltage according to a first pulse width modulation (PWM) signal and a second PWM signal. The current sensing module respectively sense a first channel current and a second channel current to output a first sensing current and a second sensing current. The current average control circuit generates a first error current and a second error current according to the first sensing current and the second sensing current and an average current thereof. The modulator generates the first PWM signal and the second PWM signal according to the first error current, the second error current and the output voltage. | 11-22-2012 |
20120278636 | REMOTE WAKE MECHANISM FOR A NETWORK SYSTEM AND REMOTE WAKE METHOD THEREOF - A network system with wake-up on LAN (WOL) mechanism and a wake-up on LAN method are disclosed. The network system includes: a first network device in a first local area network; a second network device in a second local area network, wherein the first local area network and the second local area network are different; and, a match server in a wide area network, wherein the first network device and the second network device perform data transmission through the match server. | 11-01-2012 |
20120265861 | METHOD FOR SHARING ACCESS TO A WIRELESS LAN ACCESS POINT - A method for sharing access to a wireless LAN access point is applicable between a target client device and a host device which is coupled to the wireless LAN access point, and includes the steps of: configuring the host device to send an invite request to the target client device, configuring the host device to receive an invite response sent by the target client device, and configuring the host device to exchange connection information with the target client device, such that the target client device may connect to the wireless LAN access point according to the connection information. | 10-18-2012 |
20120263374 | DEVICE AND METHOD FOR TRANSFORMING 2D IMAGES INTO 3D IMAGES - A device for transforming 2D images into 3D images includes a position calculation unit and an image processing block. The position calculation unit generates multiple start points corresponding to multiple pixel lines of a panel according to a display type of the panel. The image processing block reshapes multiple input enable signals into multiple output enable signals according to the start points. The pixel lines of the panel displays the output data signal as multiple image signals respectively according to the output enable signals. The image signals include multiple left-eye image signals and multiple right-eye image signals. | 10-18-2012 |
20120243133 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit is for protecting an internal circuit electrically coupled to an input/output (I/O) pad. The ESD protection circuit comprises an ESD protection unit, to be electrically coupled to the I/O pad, for enabling release of an electrostatic charge at the I/O pad to a ground terminal. The ESD protection circuit also comprises a voltage detecting unit, electrically coupled to the ESD protection unit and to be electrically coupled to the I/O pad, for detecting the presence of an ESD voltage at the I/O pad and for controlling the ESD protection unit to establish a conduction path between the I/O pad and the ground terminal when the ESD voltage is detected. | 09-27-2012 |
20120239870 | FIFO APPARATUS FOR THE BOUNDARY OF CLOCK TREES AND METHOD THEREOF - A FIFO apparatus uses a first clock signal in a first clock domain to receive an input signal and uses a second clock signal in a second clock domain to output an output signal. An example apparatus includes: at least three write registers belonging to the first clock domain for receiving the input signal. Each of the write registers has a first output. A first controller belonging to the first clock domain enables the registers, in accordance with an order, to generate an initial signal. A multiplexer receives the first outputs. A second controller belonging to the second clock domain, receives the initial signal through an asynchronous interface and controls the multiplexer to output the first outputs in accordance with the order to be the output signal, wherein the second clock domain is a clock tree generated based on the first clock domain. | 09-20-2012 |
20120238231 | Dynamic AC-Coupled DC Offset Correction - A method, using an AC-coupled filter, reduces DC offset in a downconverted signal in a wireless receiver receiving a signal including a preamble, the method including: changing the corner frequency of the AC-coupled filter a plurality of times during reception of the preamble. In another implementation, a receiver includes a DC offset correction system. The receiver includes a mixer downconverting a received signal to form a downconverted signal; a first AC-coupled high pass filter having an input in at least one-way data communication with the mixer, the first AC-coupled high pass filter having a switchable corner frequency dependent on a frame state of a received signal; and a plurality of second AC-coupled high pass filters coupled to an output of the first AC-coupled high pass filter, each of the plurality of second AC-coupled high pass filters have a switchable corner frequency. | 09-20-2012 |
20120229184 | All Digital Serial Link Receiver with Low Jitter Clock Regeneration and Method Thereof - An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus. | 09-13-2012 |
20120226846 | HDMI DEVICE AND ASSOCIATED POWER MANAGEMENT METHOD - An HDMI device and an associated power management method are provided for use in the case with an HDMI Ethernet Channel implemented. The HDMI device can acquire an external power source by connecting to another HDMI device through an HDMI interface. Thus, when the internal power source of the HDMI device is disabled, the external power source can be used as a backup power source for the internal Ethernet circuit of the HDMI device. | 09-06-2012 |
20120223686 | VOLTAGE REGULATING APPARATUS WITH SWITCHING AND LINEAR OPERATIONAL MODES - The invention discloses a voltage regulating apparatus which includes: an output stage providing the apparatus with an output voltage and producing a partial voltage of the output voltage; an error amplifier coupled to the output stage and comparing the partial voltage with a reference to produce a first voltage; a PWM unit coupled to the error amplifier and comparing the first voltage with a voltage signal to produce second and third voltages; a selection unit coupled to the error amplifier and the PWM unit and outputting a fourth voltage equalling either the first or the second voltage; a first transistor coupled to the selection unit and receiving the fourth voltage and a DC voltage; and a second transistor coupled to the PWM unit, the first transistor, and a ground and receiving the third voltage; wherein a connection point of the first and second transistors is connected to the output stage. | 09-06-2012 |
20120223685 | VOLTAGE REGULATING APPARATUS - The invention discloses a voltage regulating apparatus, which includes: a linear regulator generating a first error signal; a switching regulator generating a first and a second PWM signals; a selecting unit coupled to the linear and switching regulators, receiving the first error signal and the second PWM signal, and outputting a regulating signal; a first power transistor coupled to the switching regulator and receiving the first PWM signal; and a second power transistor coupled to the selecting unit and receiving the regulating signal; wherein the voltage regulating apparatus can be put either in a linear mode of operation if the first error signal is selected as the regulating signal, or in a switching mode of operation if the second PWM signal is selected as the regulating signal. | 09-06-2012 |
20120220249 | Dynamic AC-Coupled DC Offset Correction - Systems are disclosed that utilize AC-coupled filtering to reduce DC offset, with aspects dynamically correcting instantaneous DC offset generated from the AC-coupled filtering. A DC offset correction circuit for an radio frequency (rf) receiver, comprising a switchable high pass filter configured to receive a signal, the switchable high pass filter including a plurality of high pass filters connected in parallel, wherein at least one of the plurality of high pass filters has a tunable corner frequency. | 08-30-2012 |
20120213317 | Receiver for Compensating I/Q Mismatch, Compensation Device, Compensation Module and Compensation Parameter Calculating Module - A receiver for compensating I/Q mismatch includes an analog down-conversion unit for receiving a radio frequency signal and down-converting the RF signal into a set of digital low intermediate frequency (IF) signals, a digital down-conversion unit receiving the set of digital low IF signals and down-converting the set of digital low IF signals into first and second baseband signals, and a compensation unit. The compensation unit receives the first and second baseband signals, calculates a compensation parameter based thereon, and compensates I/Q mismatch effect according to the first and second baseband signals and the compensation parameter so as to output a target signal. | 08-23-2012 |
20120213306 | APPARATUS AND METHOD FOR CROSS CLOCK DOMAIN INTERFERENCE CANCELLATION - An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal. The cancellation signal generator adjusts the cancellation signal according to a phase difference between the interference signal and the cancellation signal. | 08-23-2012 |
20120213104 | APPARATUS FOR ADJUSTING POWER AND METHOD THEREOF - A power adjusting apparatus communicating with a remote terminal is provided. The apparatus includes: a transceiving unit transmitting a plurality of test packets by a plurality of powers; a processing unit coupled to the transceiving unit, and deciding a transmission power for transmitting a subsequent packet according to at least one retransmission number of transmitting the test packets. | 08-23-2012 |
20120207235 | SIGNAL PROCESSING CIRCUIT AND METHOD THEREOF - A signal processing circuit is disclosed, comprising a first node for coupling with a first antenna, a second node for coupling with a second antenna, a third node for receiving a first signal from a transmitting circuit, a fourth node for coupling with a receiving circuit, a signal dividing circuit, a phase shifting circuit, and a signal combining circuit. The signal dividing circuit divides the first signal into a second signal and a third signal, and transmits the second signal to the first antenna. The phase shifting circuit shifts the phase of the third signal to generate a fourth signal for canceling at least part of a coupled signal between the third node and the fourth node. The signal combining circuit combines the fourth signal and a fifth signal received from the second antenna, and transmits the combined signal to the receiving circuit. | 08-16-2012 |
20120170735 | COMMUNICATION APPARATUS FOR RAPIDLY ADJUSTING ANALOG ECHO CANCELLATION CIRCUIT AND RELATED ECHO CANCELLATION METHOD - A communication apparatus is disclosed including: an analog-front-end circuit for receiving and processing an analog input signal; an analog-to-digital converter (ADC) coupled with the analog-front-end circuit for converting processed signal from the analog-front-end circuit into a digital input signal; and a control unit coupled with the ADC for adjusting at least one resistance and/or at least one capacitance in an analog echo cancellation circuit according to the digital input signal before the analog-front-end circuit receives a training sequence that is the first training sequence transmitted from a second communication apparatus after the second communication apparatus begins communicating with the communication apparatus. | 07-05-2012 |
20120169307 | SIDO POWER CONVERTER AND DRIVING METHOD THEREOF - The present invention relates to a Single Inductor Double Output (SIDO) power converter, which comprises a power-stage circuit, a current detector, a slope compensation device, at least two error amplifiers, a comparing unit, a mode exchange circuit, a logical device and a driver. The SIDO current converter achieves an optimal SIDO power converting efficiency by controlling a full-current mode. Furthermore, different power transferring modes, under a variety of loadings, are used to address the issue of cross regulation and at meanwhile solving output voltage ripples and transient response to ensure the SIDO power converter a more flexible usage environment and better output performance. | 07-05-2012 |
20120139792 | DUAL-BAND ANTENNA AND COMMUNICATION DEVICE USING THE SAME - A dual-band antenna is disclosed, comprising a radiating body, a shorting element, and a feeding element. The radiating body comprises a plurality of radiating portions located in a first, a second, a third, and a fourth planes, respectively. The shorting element and the feeding element both extend from the radiating body and are located in the first plane. The radiating portions located in the first, the second, and the third planes transmit and/or receive signals in a first frequency band. The radiating portions located in the first, the second, and the fourth planes transmit and/or receive signals in a second frequency band. A first angle between the first and the second planes, a second angle between the second and the third planes, and a third angle between the second and the fourth planes range between 80 degrees to 100 degrees. | 06-07-2012 |
20120139669 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 06-07-2012 |
20120133439 | Reference Voltage Buffer and Method Thereof - An apparatus comprises: an OTA (operational trans-conductance amplifier) with a positive input terminal coupled to a reference voltage, a negative input terminal coupled to a feedback node, and an output terminal shunt to a ground node via a shunt capacitor; a resistor coupling the output terminal of the OTA to the feedback node; and a load circuit coupled to the feedback node via a switch controlled by a logical signal, wherein: an impedance of the shunt capacitor is substantially smaller than an input impedance of the load circuit. In an embodiment, the load circuit is a switch capacitor circuit. A corresponding method using an OTA is also provided. | 05-31-2012 |
20120117326 | APPARATUS AND METHOD FOR ACCESSING CACHE MEMORY - The present invention relates to an apparatus and a method for accessing a cache memory. The cache memory comprises a level-one memory and a level-two memory. The apparatus for accessing the cache memory according to the present invention comprises a register unit and a control unit. The control unit receives a first read command and a reject datum of the level-one memory and stores the reject datum of the level-one memory to the register unit. Then the control unit reads and stores a stored datum of the level-two memory to the level-one memory according to the first read command. | 05-10-2012 |
20120110419 | Data Structure for Flash Memory and Data Reading/Writing Method Thereof - A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively. | 05-03-2012 |
20120108301 | Apparatus and Method for Power-Saving in Multiple Antenna Communication System - A multiple-antenna transceiver in the present invention includes a frame controller and circuitry for transmitting and receiving. The transmitting component includes a sequence selection circuit, a MIMO modulation and coding circuit, and numerous TX RFE and AFE circuits. The receiving component includes a MIMO demodulation and decoding circuit, a sequence separation circuit, and numerous RX RFE and AFE circuits. The frame controller can enable and disable the TX and RX RFE and AFE circuits individually so as to reduce power consumption of the whole system. | 05-03-2012 |
20120108185 | MULTI-MODE WIRELESS TRANSCEIVER AND MULTI-MODE SWITCHING METHOD THEREOF - A multi-mode wireless transceiver and a multi-mode switching method thereof are disclosed to provide at least one wireless transceiving interface capable of dynamically switching between multiple frequency bands. The wireless transceiver comprises: a first RF transceiving circuit for transceiving RF signals of a first frequency band; a second RF transceiving circuit for transceiving RF signals of a second frequency band; a first frequency synthesizer and a second frequency synthesizer for generating a first carrier of the first frequency band and a second carrier of the second frequency band respectively; and a switching circuit for outputting the first carrier to the first RF transceiving circuit, and for determining to output one of the first and second carriers to the second RF transceiving circuit according to a control signal. | 05-03-2012 |
20120082379 | Image Adjustment Method and Device - An image adjustment method includes the steps of: a) configuring a weight-value generator to receive first image data and specified data and to generate an adaptive weight value according to the first image data and the specified data; and b) configuring an image blender to receive the first image data and second image data, and to generate adjusted image data by blending the first image data and the second image data with reference to the adaptive weight value. The adaptive weight value has a magnitude that corresponds to a difference between the first image data and the specified data. | 04-05-2012 |
20120076173 | Method and Device for Implementation of Adaptive Frequency Hopping by Power Spectral Density - A wireless communication device is disclosed. The wireless communication device includes a frequency hopping communication circuit, a power spectral density circuit and a control circuit. The frequency hopping communication circuit includes a channel map. The frequency hopping communication circuit selects one of channel in a channel map to connect to another frequency hopping communication circuit according to the channel map. The power spectral density circuit for generating a power spectral density signal by measuring spectrums on all channels connected to the frequency hopping communication circuit. The control circuit receives the power spectral density and output statistical distribution data to the frequency hopping communication circuit. The frequency hopping communication circuit updates the channel map according to the statistical distribution data. | 03-29-2012 |
20120057074 | VIDEO PROCESSING METHOD AND CIRCUIT USING THEREOF - A video processing method enlarging and enhancing sharpness of input video data includes following steps. First, N sets of pixel row data of the input video data are respectively buffered in N linear buffers, N is a natural number. Next, I sets of enlarged pixel row data are generated by interpolation according to the buffered N sets of pixel row data in the N linear buffers and a currently inputted set of pixel row data, I is a natural number greater than N. Then, I sets of smoothed and enlarged pixel row data are generated according to the buffered N sets of pixel row data in the N linear buffers and the (N+1) | 03-08-2012 |
20120056687 | VOLTAGE CONTROL OSCILLATOR - A voltage control oscillator implemented in an integrated circuit includes a supply circuit and an oscillating circuit. The supply circuit, implemented with an input/output (I/O) interface element, receives an I/O reference voltage signal and provides a power signal accordingly. The oscillating circuit, implemented with a core circuit element, provides an oscillation signal in response to the power signal. A swing of the oscillation signal is determined according to a level of an I/O reference voltage signal. | 03-08-2012 |
20120056649 | METHOD AND APPARATUS FOR REGENERATING SAMPLING FREQUENCY AND THEN QUICKLY LOCKING SIGNALS ACCORDINGLY - A receiving method and apparatus is disclosed. The method comprising steps of: receiving a plurality of data according to a symbol clock signal, and reading out the plurality of data according to a first clock signal and generating a water level; receiving a second clock signal so as to generate a third clock signal, and adjusting the speed of the third clock signal according to the water level; determining a sampling frequency of the plurality of data according to a data amount of the plurality of data during a unit time period or parameters of the plurality of data; and dividing the third clock signal by a dividing value or multiplying the third clock signal by a multiplying value so as to obtain the first clock signal and adjust the water level by a clock generator. | 03-08-2012 |
20120026404 | SATURATION ADJUSTING APPARATUS AND METHOD THEREOF - A saturation adjusting apparatus for processing a pixel, which has three color components each having a value falling within a range defined by upper and lower extreme values, of a RGB color model includes an extreme value controller and a component adjuster. The extreme value controller determines maximum and minimum extreme value thresholds for ensuring that the values of the color components of the pixel after undergoing linear color correction processing based on a correction indicator fall within the range defined by the upper and lower extreme values. The component adjuster includes a decision-making unit for choosing the correction indicator from a group of values which includes the maximum extreme value threshold, the minimum extreme value threshold, and a saturation setting. The component adjuster further includes a color corrector for performing linear color correction processing on the three color components of the pixel using the correction indicator. | 02-02-2012 |
20120025612 | METHODS AND CIRCUITS FOR POWER SWITCHING - The present invention relates to a method and a circuit for power switching. The method comprises the steps of: providing a operation circuit; receiving a command from a Host and setting up a power mode of the operation circuit; supplying a first rated consuming power source and then a second rated consuming power source to the operation circuit via the power switching circuit according to power mode; detecting the transferring process form the first rated consuming power source to second rated consuming power source; and preventing over current according to detecting result. | 02-02-2012 |
20120019311 | ELECTRONIC DEVICES AND METHODS - The present invention relates to an electronic device, which comprises: a first module, comprising an I/O pad for being an interface between the electronic device and an external device, and receiving a first bias source; a second module, coupled to the first module, comprising a register, and receiving a second bias source; and a signal converter, coupled between the first module and the second module. Wherein when one of the first and second bias sources is stable and the other is unstable, the signal converter outputs a first predetermined bias value to the first or second modules receiving the unstable bias source. | 01-26-2012 |
20120007861 | DEVICE AND METHOD FOR 3-D DISPLAY CONTROL - A representative Device and Method for 3-D Display Control is disclosed. The method for controlling stereo image display is disclosed. That is, to receive an image input signal wherein the image input signal includes a first refresh rate; to convert a frame rate of the image input signal to generate an image output signal, wherein the image output signal includes a second refresh rate which is higher than the first refresh rate, and includes a first image signal, a first VBI (Vertical Blanking Interval), a second image signal, a second VBI, a third image signal and a third VBI; to output a control signal for a left eye shutter of shutter glasses during a duration between the first VBI and a part of the second image signal; and to output a control signal for a right eye shutter of the shutter glasses during a duration between a part of the third image signal and the third VBI. | 01-12-2012 |
20120007675 | POWER AMPLIFIER - A power amplifier is provided. The power amplifier includes a loading circuit, a first stage amplifying circuit, an analog pre-distorter, a loading circuit and a second stage amplifying circuit. The first stage amplifying circuit is coupled to the loading circuit to receive a first signal and output a second signal accordingly. The analog pre-distorter is coupled to the first stage amplifying circuit to detect the envelope of the second signal and generates a third signal according to the envelope. The second stage amplifying circuit is coupled to the first stage amplifying circuit to receive the second signal. The loading circuit is biased on the third signal. The gain of the first stage amplifying circuit is related to the third signal. | 01-12-2012 |
20110316600 | Serial Link Receiver and Method Thereof - A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision. | 12-29-2011 |
20110316517 | ELECTRONIC APPARATUS HAVING STAND-BY MODE AND OPERATION METHOD THEREOF - The present invention relates to an electronic apparatus having stand-by mode. The electronic apparatus comprises: a first circuit, comprising an interface and transferring data to an external device; a second circuit, comprising a processor and setting a first power supplying mode of the first circuit; and a third circuit, setting a second circuit power supplying mode of the second circuit and setting a second power supply mode of the first circuit when the second circuit is disabled; wherein the processor selects a first circuit power supplying mode from power supplying modes of a plurality of first circuits as the second power supplying mode before the second circuit is disabled. | 12-29-2011 |
20110310095 | THREE DIMENSIONAL PROCESSING CIRCUIT AND PROCESSING METHOD - A three dimensional processing circuit and processing method is disclosed. In the present invention, a key depth is obtained to change an OSD location by analyzing the key image information in the 3D image. Therefore, the disadvantages of the conventional 3D processing circuit and processing method are fixed so as to decrease fatigue of user's eyes. | 12-22-2011 |
20110302434 | METHOD AND DEVICE OF POWER SAVING FOR TRANSMITTING SIGNALS - A method and device of the power saving for transmitting a signal is provided. The method comprises the steps of: transmitting a test signal with a first test amplitude from a local terminal, wherein the first test amplitude is selected from a plurality of preset amplitudes; acknowledging that the test signal with the first test amplitude has been received by a remote terminal if an acknowledgement signal is transmitted from the remote terminal for a response to the test signal; and transmitting a data signal having a data amplitude based on the first test amplitude. The device can transmit the data signal with a small data signal amplitude by the method to achieve the saving power. | 12-08-2011 |
20110299578 | DATA TRANSMITTING AND RECEIVING METHOD AND DEVICE FOR COMMUNICATION AND SYSTEM THEREOF - A data transmitting and receiving device and method are used for saving powers and maintaining the connection quality, stability and continuous link. The method includes the step of gradually adjusting the de-emphasis of the signal transmitted from the data transmitting and receiving device according to the setting value thereof. The method also includes the steps of transmitting training sequence signal with an amplitude and the default de-emphasis by the data transmitting and receiving device to the remote device, receiving the training sequence signal from the remote device, thereby the channel attenuation is estimated using the method, and a better de-emphasis is set up. Then, the data transmitting and receiving device gradually increases the amplitude of the training sequence signal and re-transmits it until the remote device receives the training sequence signal transmitted therefrom. | 12-08-2011 |
20110296365 | EXTRACTING METHODS FOR CIRCUIT MODELS - The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path. | 12-01-2011 |
20110283068 | MEMORY ACCESS APPARATUS AND METHOD - A memory access apparatus is coupled to a memory unit and includes a header access circuit and a payload access circuit. The header access circuit includes a header fetching unit used to fetch a header descriptor in the memory unit, and the payload access circuit includes a payload fetching unit used to fetch a payload descriptor in the memory unit. The header access circuit and the payload access circuit perform fetching with respect to the memory unit in a non-sequenced manner. | 11-17-2011 |
20110278743 | LAYOUT STRUCTURE AND VERSION CONTROL CIRCUIT FOR INTEGRATED CIRCUITS - The present invention relates to a layout structure and a version control circuit for integrated circuits. The layout structure for integrated circuits according to the present invention comprises a signal-supplying unit and at least a transfer cell. The signal-supplying unit is used for supplying a first signal and a second signal. The transfer cell has a plurality of metal layers interconnected. One of metal layers receives and transfers the first signal or the second signal. When changing the transfer cell to transfer the second signal instead of the first signal, the metal layers interrupt transferring the first signal but receive and output the second signal. When the circuit is revised and multiple sub-circuits as well as the transferred signal are changed, the fewest metal layers commonly adopted are used. Accordingly, the present invention can reduce effectively the number of masks, and thus reducing costs. | 11-17-2011 |
20110276158 | AUDIO DATA TRANSMITTING APPARATUS FOR WEBCASTING AND AUDIO REGULATING METHODS THEREFOR - A webcasting system and the audio data regulating methods to be used in the webcasting system are presented. The webcasting system includes a host and an audio playing apparatus. The host, which is loaded with an operating system and drivers, determines the audio data output according to an expected data received by the operating system. The drivers provide the expected data according to the audio data received and transform the audio data for network transmission. The audio playing apparatus receives the network data and processes the network data for audio playing. | 11-10-2011 |
20110261911 | RECEIVER CAPABLE OF REDUCING LOCAL OSCILLATION LEAKAGE AND IN-PHASE/QUADRATURE-PHASE (I/Q) MISMATCH AND AN ADJUSTING METHOD THEREOF - An adjusting method for reducing local oscillation leakage or I/Q mismatch in a receiver includes the steps of: (a) detecting a current extent of local oscillation leakage or I/Q mismatch; (b) determining if an adjusting direction is correct with reference to the current extent of local oscillation leakage or I/Q mismatch thus detected, maintaining the adjusting direction if correct, and reversing the adjusting direction upon determining that the adjusting direction is incorrect; and (c) adjusting a control signal according to the adjusting direction. | 10-27-2011 |
20110254633 | METHOD AND APPARATUS FOR ALLEVIATING CHARGE LEAKAGE OF VCO FOR PHASE LOCK LOOP - Methods and apparatuses for alleviating charge leakage of VCO for phase lock loop are disclosed. The method comprises: receiving an input signal; generating an error signal representing a timing difference between the input signal and an output signal; filtering the error signal into a control signal; buffering the control signal into a buffered control signal; and generating the output signal in accordance with the buffered control signal. Buffering the control signal comprising using a high input resistance and low output resistance buffer circuit. | 10-20-2011 |
20110254631 | REFERENCE ASSISTED CONTROL SYSTEM AND METHOD THEREOF - A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal. | 10-20-2011 |
20110239024 | Low Power Consumption Network Device and Communication Method Thereof - A low power consumption network device includes: a data rate meter for detecting a data rate of the network device; a state machine unit for determining a state of the network device according to the data rate and for generating an instruction signal; and a power control unit for controlling a power consumption state of the network device according to the instruction signal. According to the data rate, the state machine unit controls whether the network device transmits a pause frame to a link partner, so that the link partner stops transmitting data to the network device during a pause period. During the pause period, the power control unit controls the network device into a power saving mode. | 09-29-2011 |
20110194588 | WIRELESS COMMUNICATION SYSTEM AND METHOD OF PROCESSING A WIRELESS SIGNAL - A wireless communication system includes: a frequency down-converting circuit for receiving a wireless signal and for performing frequency down-conversion on the wireless signal to output a frequency down-converted signal; a first training circuit for performing frequency comparison between the frequency down-converted signal and a plurality of candidate carrier signals having different frequencies so as to determine a plurality of selected carrier signals from the candidate carrier signals; a second training circuit for performing phase comparison between the frequency down-converted signal and phases of a pseudo-noise sequence at each of the selected carrier signals so as to determine a matching phase and a matching carrier; and a demodulator for demodulating the frequency down-converted signal according to the matching carrier and the matching phase so as to generate a demodulated signal. | 08-11-2011 |
20110179323 | Memory with Self-Test Function and Method for Testing the Same - The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources. | 07-21-2011 |
20110163828 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 07-07-2011 |
20110158291 | Automatic Gain Control for Frequency-Hopped OFDM - An automatic gain control method and system for use in signal processing of OFDM symbols at a receiver. Two stages of coarse and fine automatic gain control are implemented that adjust different gains in an analog RF processing stage of the receiver. Gain of a low noise amplifier and a mixer are adjusted during a first and coarse automatic gain control stage based on feedback from a digital baseband stage. During a subsequent fine gain control period, the gain of a programmable gain amplifier is adjusted separately for each frequency band used by the OFDM symbols based on a histogram bin that counts the number of output samples of an analog to digital converter whose magnitude falls within certain ranges. Coarse and fine gains are updated after each OFDM symbol. | 06-30-2011 |
20110142178 | DEVICE AND METHOD FOR CONTROLLING FREQUENCY RESONANCE POINT OF AN ANTENNA - The present invention disclosed an apparatus and method for receiving a plurality of broadcasting signals. The apparatus comprises: a control circuit for generating an analog control voltage signal according to a frequency-voltage look-up table and a desired frequency; an antenna module comprising an antenna and an antenna resonant control circuit comprising a voltage-controlled capacitor being controlled by the analog control voltage signal, wherein the antenna resonant control circuit comprises a voltage-controlled capacitor to control the bandwidth received by the antenna according to the analog control voltage signal; a tuner for tuning a broadcasting signal received by the antenna to generate an output signal; and a demodulator for demodulating the output signal of the tuner. | 06-16-2011 |
20110140767 | Method and Apparatus for Charge Leakage Compensation for Charge Pump with Leaky Capacitive Load - An apparatus comprises a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. A comparable method is also disclosed. | 06-16-2011 |
20110140676 | Mismatch-Free Charge Pump and Method Thereof - The charge-pump apparatus is disclosed having a substantially fixed current source for outputting a first current of a first polarity; a variable current source for outputting a second current of a second polarity opposite to the first polarity; a first current steering network for steering the first current into either an output node or a termination node in accordance with a first control signal; a second current steering network for steering the second current into either the output node or the termination node in accordance with a second control signal; a voltage follower for receiving a first voltage associated with the output node and outputting a second voltage at an internal node; a current sensor inserted between the termination node and the internal node for sensing a current flowing between the termination node and the internal node; and a feedback network for adjusting the variable current source in accordance with an output of the current sensor. | 06-16-2011 |
20110111717 | CURRENT-MODE WIRELESS RECEIVER AND RECEPTION METHOD THEREOF - A current-mode wireless receiver includes a pre-processor to receive a voltage-mode input signal and output a current-mode pre-processed signal corresponding to the voltage-mode input signal, a mixer to perform frequency down-conversion upon the current-mode pre-processed signal to generate a current-mode frequency down-converted signal, and an amplifier to amplify the current-mode frequency down-converted signal to generate a current-mode output signal. A method of wireless reception is also disclosed. | 05-12-2011 |
20110089988 | Self-Calibrating R-2R Ladder and Method Thereof - A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N−1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word. When the first logical signal is 0, the apparatus operates in a normal mode and the output signal follows the N control bits; when the first logical signal is 1, the apparatus operates in a calibration mode and the output signal follows the second logical signal. When the apparatus operates in the calibration mode, the tuning word is adjusted in a closed loop manner so as to make the output signal substantially the same regardless of a value of the second logical signal. | 04-21-2011 |
20110078289 | NETWORK CONFIGURATION METHOD FOR NETWORKING DEVICE AND ASSOCIATED NETWORK CONFIGURATION MODULE - A network configuration method for a networking device and an associated network configuration module are provided to simplify the network configuration process of the networking device, thereby increasing user's convenience. The method connects a storage device to another networking device, so as to obtain network configuration information thereof and store it into the storage device. Next, the method connects the storage device to the networking device, and configures the networking device according to the network configuration information stored in the storage device. | 03-31-2011 |
20110043221 | Method and Device for Dynamic Adjustment of Network Operating Voltage - The present invention is to provide a method and device of dynamically adjusting the operating voltage of a network integrated circuit including the steps of detecting and ranking the signal-to-noise ratio of N ports to single out a port for arbitration, dynamically controlling the operating voltage according to the signal-to-noise ratio of the port for arbitration, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a first threshold, increasing the operating voltage to a default operating voltage when the signal-to-noise ratio of the port for arbitration is smaller than the first threshold, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a second threshold, and increasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is smaller than the second threshold. | 02-24-2011 |
20110037525 | CRYSTAL OSCILLATOR - This invention discloses a crystal oscillator, in which by appropriately designing the gain of an amplifier to achieve high trans-conductance and low power consumption. This crystal oscillator includes a first pad, coupled to a first node of a crystal, for receiving a crystal oscillating signal outputted from the crystal; an amplifier, coupled to the first pad, for amplifying the crystal oscillating signal to generate an amplifying signal; an inverter, coupled to the amplifier, for inverting the amplifying signal; and a second pad, coupled to a second node of the crystal, for outputting an oscillating signal to the crystal. | 02-17-2011 |
20110012683 | METHOD AND APPARATUS OF PHASE LOCKING FOR REDUCING CLOCK JITTER DUE TO CHARGE LEAKAGE - a phase lock loop is disclosed, the phase lock loop comprising: a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal. | 01-20-2011 |
20110012657 | DIGITALLY CONTROLLED OSCILLATOR - A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell. | 01-20-2011 |