| REALTEK SEMICONDUCTOR CORP. Patent applications |
| Patent application number | Title | Published |
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| 20120026404 | SATURATION ADJUSTING APPARATUS AND METHOD THEREOF - A saturation adjusting apparatus for processing a pixel, which has three color components each having a value falling within a range defined by upper and lower extreme values, of a RGB color model includes an extreme value controller and a component adjuster. The extreme value controller determines maximum and minimum extreme value thresholds for ensuring that the values of the color components of the pixel after undergoing linear color correction processing based on a correction indicator fall within the range defined by the upper and lower extreme values. The component adjuster includes a decision-making unit for choosing the correction indicator from a group of values which includes the maximum extreme value threshold, the minimum extreme value threshold, and a saturation setting. The component adjuster further includes a color corrector for performing linear color correction processing on the three color components of the pixel using the correction indicator. | 02-02-2012 |
| 20120025612 | METHODS AND CIRCUITS FOR POWER SWITCHING - The present invention relates to a method and a circuit for power switching. The method comprises the steps of: providing a operation circuit; receiving a command from a Host and setting up a power mode of the operation circuit; supplying a first rated consuming power source and then a second rated consuming power source to the operation circuit via the power switching circuit according to power mode; detecting the transferring process form the first rated consuming power source to second rated consuming power source; and preventing over current according to detecting result. | 02-02-2012 |
| 20120019311 | ELECTRONIC DEVICES AND METHODS - The present invention relates to an electronic device, which comprises: a first module, comprising an I/O pad for being an interface between the electronic device and an external device, and receiving a first bias source; a second module, coupled to the first module, comprising a register, and receiving a second bias source; and a signal converter, coupled between the first module and the second module. Wherein when one of the first and second bias sources is stable and the other is unstable, the signal converter outputs a first predetermined bias value to the first or second modules receiving the unstable bias source. | 01-26-2012 |
| 20120007861 | DEVICE AND METHOD FOR 3-D DISPLAY CONTROL - A representative Device and Method for 3-D Display Control is disclosed. The method for controlling stereo image display is disclosed. That is, to receive an image input signal wherein the image input signal includes a first refresh rate; to convert a frame rate of the image input signal to generate an image output signal, wherein the image output signal includes a second refresh rate which is higher than the first refresh rate, and includes a first image signal, a first VBI (Vertical Blanking Interval), a second image signal, a second VBI, a third image signal and a third VBI; to output a control signal for a left eye shutter of shutter glasses during a duration between the first VBI and a part of the second image signal; and to output a control signal for a right eye shutter of the shutter glasses during a duration between a part of the third image signal and the third VBI. | 01-12-2012 |
| 20120007675 | POWER AMPLIFIER - A power amplifier is provided. The power amplifier includes a loading circuit, a first stage amplifying circuit, an analog pre-distorter, a loading circuit and a second stage amplifying circuit. The first stage amplifying circuit is coupled to the loading circuit to receive a first signal and output a second signal accordingly. The analog pre-distorter is coupled to the first stage amplifying circuit to detect the envelope of the second signal and generates a third signal according to the envelope. The second stage amplifying circuit is coupled to the first stage amplifying circuit to receive the second signal. The loading circuit is biased on the third signal. The gain of the first stage amplifying circuit is related to the third signal. | 01-12-2012 |
| 20110316600 | Serial Link Receiver and Method Thereof - A method and apparatus of clock recovery is disclosed. The apparatus comprising: a first delay circuit for receiving an input data signal and outputting a delayed data signal; an edge extraction circuit for outputting an edge signal by detecting a transition in the input data signal; an clock generator for generating a first clock signal based on an injection of the edge signal, wherein the first clock signal comprises a plurality of phase signals; a second delay buffer for outputting a second clock signal according to the first clock signal; a sampler for outputting a plurality of samples based on sampling the delayed data signal in accordance with the phase signals; and a decision circuit for generating a decision in accordance with the second clock signal based on the three samples and a previous decision. | 12-29-2011 |
| 20110316517 | ELECTRONIC APPARATUS HAVING STAND-BY MODE AND OPERATION METHOD THEREOF - The present invention relates to an electronic apparatus having stand-by mode. The electronic apparatus comprises: a first circuit, comprising an interface and transferring data to an external device; a second circuit, comprising a processor and setting a first power supplying mode of the first circuit; and a third circuit, setting a second circuit power supplying mode of the second circuit and setting a second power supply mode of the first circuit when the second circuit is disabled; wherein the processor selects a first circuit power supplying mode from power supplying modes of a plurality of first circuits as the second power supplying mode before the second circuit is disabled. | 12-29-2011 |
| 20110310095 | THREE DIMENSIONAL PROCESSING CIRCUIT AND PROCESSING METHOD - A three dimensional processing circuit and processing method is disclosed. In the present invention, a key depth is obtained to change an OSD location by analyzing the key image information in the 3D image. Therefore, the disadvantages of the conventional 3D processing circuit and processing method are fixed so as to decrease fatigue of user's eyes. | 12-22-2011 |
| 20110302434 | METHOD AND DEVICE OF POWER SAVING FOR TRANSMITTING SIGNALS - A method and device of the power saving for transmitting a signal is provided. The method comprises the steps of: transmitting a test signal with a first test amplitude from a local terminal, wherein the first test amplitude is selected from a plurality of preset amplitudes; acknowledging that the test signal with the first test amplitude has been received by a remote terminal if an acknowledgement signal is transmitted from the remote terminal for a response to the test signal; and transmitting a data signal having a data amplitude based on the first test amplitude. The device can transmit the data signal with a small data signal amplitude by the method to achieve the saving power. | 12-08-2011 |
| 20110299578 | DATA TRANSMITTING AND RECEIVING METHOD AND DEVICE FOR COMMUNICATION AND SYSTEM THEREOF - A data transmitting and receiving device and method are used for saving powers and maintaining the connection quality, stability and continuous link. The method includes the step of gradually adjusting the de-emphasis of the signal transmitted from the data transmitting and receiving device according to the setting value thereof. The method also includes the steps of transmitting training sequence signal with an amplitude and the default de-emphasis by the data transmitting and receiving device to the remote device, receiving the training sequence signal from the remote device, thereby the channel attenuation is estimated using the method, and a better de-emphasis is set up. Then, the data transmitting and receiving device gradually increases the amplitude of the training sequence signal and re-transmits it until the remote device receives the training sequence signal transmitted therefrom. | 12-08-2011 |
| 20110296365 | EXTRACTING METHODS FOR CIRCUIT MODELS - The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path. | 12-01-2011 |
| 20110283068 | MEMORY ACCESS APPARATUS AND METHOD - A memory access apparatus is coupled to a memory unit and includes a header access circuit and a payload access circuit. The header access circuit includes a header fetching unit used to fetch a header descriptor in the memory unit, and the payload access circuit includes a payload fetching unit used to fetch a payload descriptor in the memory unit. The header access circuit and the payload access circuit perform fetching with respect to the memory unit in a non-sequenced manner. | 11-17-2011 |
| 20110278743 | LAYOUT STRUCTURE AND VERSION CONTROL CIRCUIT FOR INTEGRATED CIRCUITS - The present invention relates to a layout structure and a version control circuit for integrated circuits. The layout structure for integrated circuits according to the present invention comprises a signal-supplying unit and at least a transfer cell. The signal-supplying unit is used for supplying a first signal and a second signal. The transfer cell has a plurality of metal layers interconnected. One of metal layers receives and transfers the first signal or the second signal. When changing the transfer cell to transfer the second signal instead of the first signal, the metal layers interrupt transferring the first signal but receive and output the second signal. When the circuit is revised and multiple sub-circuits as well as the transferred signal are changed, the fewest metal layers commonly adopted are used. Accordingly, the present invention can reduce effectively the number of masks, and thus reducing costs. | 11-17-2011 |
| 20110276158 | AUDIO DATA TRANSMITTING APPARATUS FOR WEBCASTING AND AUDIO REGULATING METHODS THEREFOR - A webcasting system and the audio data regulating methods to be used in the webcasting system are presented. The webcasting system includes a host and an audio playing apparatus. The host, which is loaded with an operating system and drivers, determines the audio data output according to an expected data received by the operating system. The drivers provide the expected data according to the audio data received and transform the audio data for network transmission. The audio playing apparatus receives the network data and processes the network data for audio playing. | 11-10-2011 |
| 20110261911 | RECEIVER CAPABLE OF REDUCING LOCAL OSCILLATION LEAKAGE AND IN-PHASE/QUADRATURE-PHASE (I/Q) MISMATCH AND AN ADJUSTING METHOD THEREOF - An adjusting method for reducing local oscillation leakage or I/Q mismatch in a receiver includes the steps of: (a) detecting a current extent of local oscillation leakage or I/Q mismatch; (b) determining if an adjusting direction is correct with reference to the current extent of local oscillation leakage or I/Q mismatch thus detected, maintaining the adjusting direction if correct, and reversing the adjusting direction upon determining that the adjusting direction is incorrect; and (c) adjusting a control signal according to the adjusting direction. | 10-27-2011 |
| 20110254633 | METHOD AND APPARATUS FOR ALLEVIATING CHARGE LEAKAGE OF VCO FOR PHASE LOCK LOOP - Methods and apparatuses for alleviating charge leakage of VCO for phase lock loop are disclosed. The method comprises: receiving an input signal; generating an error signal representing a timing difference between the input signal and an output signal; filtering the error signal into a control signal; buffering the control signal into a buffered control signal; and generating the output signal in accordance with the buffered control signal. Buffering the control signal comprising using a high input resistance and low output resistance buffer circuit. | 10-20-2011 |
| 20110254631 | REFERENCE ASSISTED CONTROL SYSTEM AND METHOD THEREOF - A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal. | 10-20-2011 |
| 20110239024 | Low Power Consumption Network Device and Communication Method Thereof - A low power consumption network device includes: a data rate meter for detecting a data rate of the network device; a state machine unit for determining a state of the network device according to the data rate and for generating an instruction signal; and a power control unit for controlling a power consumption state of the network device according to the instruction signal. According to the data rate, the state machine unit controls whether the network device transmits a pause frame to a link partner, so that the link partner stops transmitting data to the network device during a pause period. During the pause period, the power control unit controls the network device into a power saving mode. | 09-29-2011 |
| 20110194588 | WIRELESS COMMUNICATION SYSTEM AND METHOD OF PROCESSING A WIRELESS SIGNAL - A wireless communication system includes: a frequency down-converting circuit for receiving a wireless signal and for performing frequency down-conversion on the wireless signal to output a frequency down-converted signal; a first training circuit for performing frequency comparison between the frequency down-converted signal and a plurality of candidate carrier signals having different frequencies so as to determine a plurality of selected carrier signals from the candidate carrier signals; a second training circuit for performing phase comparison between the frequency down-converted signal and phases of a pseudo-noise sequence at each of the selected carrier signals so as to determine a matching phase and a matching carrier; and a demodulator for demodulating the frequency down-converted signal according to the matching carrier and the matching phase so as to generate a demodulated signal. | 08-11-2011 |
| 20110179323 | Memory with Self-Test Function and Method for Testing the Same - The present invention relates to a memory with a self-test function and a method for testing the same. The memory comprises a testing unit, a memory unit, and a comparison module. The method for testing the memory comprises steps of the testing unit producing a pattern signal; a first storage block of the memory unit storing storage data, and outputting the storage data according to the pattern signal; a second storage block of the memory storing a compare signature corresponding to the storage data; and the compare module producing a test signature according to the storage data output by the memory unit, and comparing the test signature to the compare signature and outputting a testing result for judging validity of the memory unit. Thereby, the memory unit according to the present invention is partitioned into two storage blocks for storing the storage data and the compare signature, respectively, and thus achieving the purposes of saving the testing time, costs, and hardware resources. | 07-21-2011 |
| 20110163828 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 07-07-2011 |
| 20110158291 | Automatic Gain Control for Frequency-Hopped OFDM - An automatic gain control method and system for use in signal processing of OFDM symbols at a receiver. Two stages of coarse and fine automatic gain control are implemented that adjust different gains in an analog RF processing stage of the receiver. Gain of a low noise amplifier and a mixer are adjusted during a first and coarse automatic gain control stage based on feedback from a digital baseband stage. During a subsequent fine gain control period, the gain of a programmable gain amplifier is adjusted separately for each frequency band used by the OFDM symbols based on a histogram bin that counts the number of output samples of an analog to digital converter whose magnitude falls within certain ranges. Coarse and fine gains are updated after each OFDM symbol. | 06-30-2011 |
| 20110142178 | DEVICE AND METHOD FOR CONTROLLING FREQUENCY RESONANCE POINT OF AN ANTENNA - The present invention disclosed an apparatus and method for receiving a plurality of broadcasting signals. The apparatus comprises: a control circuit for generating an analog control voltage signal according to a frequency-voltage look-up table and a desired frequency; an antenna module comprising an antenna and an antenna resonant control circuit comprising a voltage-controlled capacitor being controlled by the analog control voltage signal, wherein the antenna resonant control circuit comprises a voltage-controlled capacitor to control the bandwidth received by the antenna according to the analog control voltage signal; a tuner for tuning a broadcasting signal received by the antenna to generate an output signal; and a demodulator for demodulating the output signal of the tuner. | 06-16-2011 |
| 20110140767 | Method and Apparatus for Charge Leakage Compensation for Charge Pump with Leaky Capacitive Load - An apparatus comprises a charge pump to receive a phase signal representing a result of a phase detection and to output a current flowing between an internal node of the charge pump and an output node of the charge pump; a capacitive load coupled to the output node; a current source controlled by a bias voltage to output a compensation current to the output node; a current sensor coupled between the internal node and the output node to sense the current; and a feedback network to generate the bias voltage in accordance with an output of the current sensor. A comparable method is also disclosed. | 06-16-2011 |
| 20110140676 | Mismatch-Free Charge Pump and Method Thereof - The charge-pump apparatus is disclosed having a substantially fixed current source for outputting a first current of a first polarity; a variable current source for outputting a second current of a second polarity opposite to the first polarity; a first current steering network for steering the first current into either an output node or a termination node in accordance with a first control signal; a second current steering network for steering the second current into either the output node or the termination node in accordance with a second control signal; a voltage follower for receiving a first voltage associated with the output node and outputting a second voltage at an internal node; a current sensor inserted between the termination node and the internal node for sensing a current flowing between the termination node and the internal node; and a feedback network for adjusting the variable current source in accordance with an output of the current sensor. | 06-16-2011 |
| 20110111717 | CURRENT-MODE WIRELESS RECEIVER AND RECEPTION METHOD THEREOF - A current-mode wireless receiver includes a pre-processor to receive a voltage-mode input signal and output a current-mode pre-processed signal corresponding to the voltage-mode input signal, a mixer to perform frequency down-conversion upon the current-mode pre-processed signal to generate a current-mode frequency down-converted signal, and an amplifier to amplify the current-mode frequency down-converted signal to generate a current-mode output signal. A method of wireless reception is also disclosed. | 05-12-2011 |
| 20110089988 | Self-Calibrating R-2R Ladder and Method Thereof - A method and apparatus are provided for calibrating a ladder circuit. The apparatus includes: a logic unit for receiving a first logical signal, a second logical signal, and N control bits and for outputting N alternative control bits and an additional control bit, where N is an integer greater than 1; a core circuit for receiving the N alternative control bits, the additional control bit, and a tuning word, and for outputting an output signal, wherein the core circuit comprises N−1 series elements, N shunt elements with a connectivity controlled by the N alternative control bits, respectively, and a termination element with a connectivity controlled by the additional control bit; and a calibration circuit for receiving the first logical signal, the second logical signal, and the output signal and for outputting the tuning word. When the first logical signal is 0, the apparatus operates in a normal mode and the output signal follows the N control bits; when the first logical signal is 1, the apparatus operates in a calibration mode and the output signal follows the second logical signal. When the apparatus operates in the calibration mode, the tuning word is adjusted in a closed loop manner so as to make the output signal substantially the same regardless of a value of the second logical signal. | 04-21-2011 |
| 20110078289 | NETWORK CONFIGURATION METHOD FOR NETWORKING DEVICE AND ASSOCIATED NETWORK CONFIGURATION MODULE - A network configuration method for a networking device and an associated network configuration module are provided to simplify the network configuration process of the networking device, thereby increasing user's convenience. The method connects a storage device to another networking device, so as to obtain network configuration information thereof and store it into the storage device. Next, the method connects the storage device to the networking device, and configures the networking device according to the network configuration information stored in the storage device. | 03-31-2011 |
| 20110043221 | Method and Device for Dynamic Adjustment of Network Operating Voltage - The present invention is to provide a method and device of dynamically adjusting the operating voltage of a network integrated circuit including the steps of detecting and ranking the signal-to-noise ratio of N ports to single out a port for arbitration, dynamically controlling the operating voltage according to the signal-to-noise ratio of the port for arbitration, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a first threshold, increasing the operating voltage to a default operating voltage when the signal-to-noise ratio of the port for arbitration is smaller than the first threshold, decreasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is greater than a second threshold, and increasing the operating voltage by a voltage unit when the signal-to-noise ratio of the port for arbitration is smaller than the second threshold. | 02-24-2011 |
| 20110037525 | CRYSTAL OSCILLATOR - This invention discloses a crystal oscillator, in which by appropriately designing the gain of an amplifier to achieve high trans-conductance and low power consumption. This crystal oscillator includes a first pad, coupled to a first node of a crystal, for receiving a crystal oscillating signal outputted from the crystal; an amplifier, coupled to the first pad, for amplifying the crystal oscillating signal to generate an amplifying signal; an inverter, coupled to the amplifier, for inverting the amplifying signal; and a second pad, coupled to a second node of the crystal, for outputting an oscillating signal to the crystal. | 02-17-2011 |
| 20110012683 | METHOD AND APPARATUS OF PHASE LOCKING FOR REDUCING CLOCK JITTER DUE TO CHARGE LEAKAGE - a phase lock loop is disclosed, the phase lock loop comprising: a first phase detector configured to receive a first clock and a second clock and output a first detector output signal; a second phase detector configured to receive the first clock and the second clock and output a second detector output signal; a summing circuit to sum the first detector output signal and the second detector output signal into a control signal; a loop filter to filter the control signal into a refined control signal; and a controllable oscillator to generate the output clock in accordance with a control by the refined control signal. | 01-20-2011 |
| 20110012657 | DIGITALLY CONTROLLED OSCILLATOR - A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell. | 01-20-2011 |
| 20110001568 | INTEGRATED CIRCUIT WITH LOW TEMPERATURE COEFFICIENT AND ASSOCIATED CALIBRATION METHOD - An integrated circuit (IC) with a low temperature coefficient and an associated calibration method are provided to lower the effect of the environmental temperature on the IC and at the same time to maintain the small area and low power consumption of the IC. The IC includes a first circuit, a second circuit and a calibration control circuit. The first circuit has a low temperature coefficient and generates a first output. The second circuit has a high temperature coefficient and generates a second output. The calibration control circuit detects the first and second outputs, and compares the first and second outputs according to a predefined relationship therebetween so as to generate an adjusting signal. The adjusting signal is for adjusting the second circuit such that the second circuit can have the characteristic of the low temperature coefficient. | 01-06-2011 |
| 20100310021 | METHOD FOR COMPUTING CORRELATION OF PN SEQUENCE AND CIRCUIT THEREOF - The present invention relates to a method for computing correlation of a PN sequence and a circuit thereof. A plurality of input values of an input sequence is summed up to give a first sum. A PN sequence comprising a plurality of first values and a plurality of second values, which correspond to the plurality of input values, are received. Summing up the plurality of input values corresponding to the plurality of first input values in the PN sequence gives a second sum. According to the first sum and the second sum, a correlation value is given. The present invention uses a simple method for computing correlation of a PN sequence. Hence, the operation efficiency is enhanced and the time to give the correlation of the PN sequence is shortened. | 12-09-2010 |
| 20100289952 | Method and Apparatus for Synchronizing Multimedia Data Stream - A method and an apparatus for synchronizing a data stream are disclosed. The method comprises: decoding the data stream to generate a decoded data stream and program clock references; generating a local clock reference; generating a simulated clock reference according to the program clock references and the local clock reference; comparing the local clock reference with the simulated clock reference; adjusting a processing timing of the decoded data stream according to the comparison result; and processing the decoded data stream according to the processing timing. | 11-18-2010 |
| 20100289680 | Self-Calibrated Current Source and DAC Using the Same and Operation Method Thereof - A background self-calibrated DAC is presented. In the present invention, a virtual-short theory, applicable to input/output terminals of an operational amplifier, is periodically employed so as to self-calibrate a current source serially connected with an equivalent resistor, and the DAC using the same. The aforesaid DAC does not require an additional self-calibration period, and digital-to-analog conversion thereof can be realized in merely a small amount of die area. Correspondingly, a compact and high-speed current steering DAC can be realized. | 11-18-2010 |
| 20100272217 | Power Consumption Control Methods Applied to Communication Systems, and Related Devices - A power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a transmission distance between the communication system and another communication system. Another power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a signal index of the communication system. | 10-28-2010 |
| 20100262789 | Methods and Devices for Accessing a Memory and a Central Processing Unit Using the Same - A memory accessing method including the following steps is provided. Firstly, two instructions are fetched. Next, the two instructions are respectively decoded to obtain two operation fields and two address fields. The two operation fields indicate the type of operation in accessing the memory. One of the address fields includes a first upper address corresponding to the first memory block and a first lower address corresponding to a first memory unit of the first memory block. The other one of the two address fields includes a second upper address corresponding to the second memory block and a second lower address corresponding to a second memory unit of the second memory block. Then, whether two instructions are performing the same type of operation on the same memory block is determined. If yes, the type of operation indicated by the two operation fields is performed on the corresponding memory block parallelly. | 10-14-2010 |
| 20100238159 | DIFFERENTIAL SIGNAL GENERATING DEVICE - A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode. | 09-23-2010 |
| 20100233982 | RECEIVING DEVICE AND METHOD THEREOF - A receiving device is disclosed. The receiving device includes a receiving module and a processing module. The receiving module includes a plurality of parameters. The receiving module is used for setting the parameters according to a control signal, receiving a wireless signal according to settings of the different parameters, and outputting a first output signal and a second output signal separately. The processing module couples the receiving module and generates the control to set the parameters according the first output signal and the second output signal. | 09-16-2010 |
| 20100231283 | METHOD AND APPARATUS FOR PREVENTING PHASE INTERPOLATION CIRCUIT FROM GLITCH DURING CLOCK SWITCHING - The present invention relates to a method and an apparatus, during a phase switching process, for choosing all of outputted phases upon the clock phases devoid of phase switching so as to avoid glitches during clock switching. Compared with the conventional approach for removing glitches by controlling a clock switching sequence, an improvement of a phase rotator is further disclosed in the present invention, which eliminates the glitches of the outputted phase clock so as to realize a glitch-less phase switching in a phase interpolation circuit. | 09-16-2010 |
| 20100188574 | DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT - A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock. | 07-29-2010 |
| 20100185834 | Data Storing Method and Processor Using the Same - A data storing method applied to a processor having a pipelined processing unit is provided. The pipelined processing unit includes stages. The stages include a source operand fetch stage and a write-back stage. The method includes the following steps. Firstly, a storing instruction is fetched and decoded. Next, the storing instruction is entered to the source operand fetch stage, and whether there is a late-done instruction in the pipelined processing unit is determined. The late-done instruction not lagged behind the storing instruction generates a late-coming result before entering the write-back stage. If it is determined that there is a late-done instruction in the pipelined processing unit, then the late-coming result is fetched before the storing instruction is entered to the write-back stage. Thereafter, the storing instruction is entered to the write-back stage, and the late-coming result is stored to a target memory which the storing instruction corresponds to. | 07-22-2010 |
| 20100166009 | VARIABLE-FREQUENCY NETWORK DEVICE AND VARIABLE-FREQUENCY NETWORK CONNECTION ESTABLISHING METHOD - A variable-frequency network connection establishing method is adapted for establishing a connection between a local network device and a remote network device. The variable-frequency network connection establishing method includes the steps of: providing a plurality of local communications protocols including a local standard communications protocol and a local variable-frequency communications protocol to the remote network device; receiving a remote communications protocol provided by the remote network device; generating an indicator signal in accordance with the remote communications protocol and the plurality of local communications protocols; and operating in one of a standard mode and variable-frequency mode according to the indicator signal. | 07-01-2010 |
| 20100127774 | DISTORTION CORRECTION DEVICE AND METHOD FOR POWER AMPLIFIER - A distortion correction device and method for power amplifier are provided. The power amplifier receives an input signal and generates a first output signal. The distortion correction device includes a self-mixing mixer and an adaptive calculator. The method includes steps of: utilizing the self-mixing mixer to receive the first output signal and generate a second output signal based on the first output signal, wherein the second output signal includes a plurality of baseband components corresponding to signal spectrum of the input signal; and utilizing the adaptive calculator to perform an adaptation algorithm to generate a look-up table based on the baseband components. | 05-27-2010 |
| 20100125769 | PARITY-CHECK-CODE DECODER AND RECORDING CONTROLLER - A parity-check-code decoder includes: a verifying device that multiplies (N) bit nodes by a matrix provided with (N) columns so as to obtain a plurality of check nodes; a reliability generator that generates a reliability index for each of the bit nodes in accordance with a channel; a reliability-updating device that uses the bit nodes and the check nodes to exchange message iteratively, and following each iteration, updates (N) exchange results corresponding to the (N) columns; and a recording controller that includes a separator, a quantizing determiner and a quantizer. The separator divides the matrix into at least one column group based on the characterizing signals. The quantizing determiner determines a shift signal for each column group based on the characterizing signals. The quantizer quantizes the characterizing signals according to the shift signals for subsequent output. | 05-20-2010 |
| 20100122139 | PARITY-CHECK-CODE DECODER AND RECEIVING SYSTEM - A parity-check-code decoder is adapted for receiving a channel quality ratio and at least (N) bits that are to be decoded. The parity-check-code decoder treats each of the bits as a bit node, and includes: a verifying circuit that multiplies (N) bit nodes by a matrix to obtain (N-K) check nodes; a reliability-generating circuit that generates a reliability index that serves as an extrinsic check index for each of the bit nodes to transmit to the check nodes; a bit exchange circuit that generates an extrinsic bit index for each of the check nodes to transmit to the bit nodes; a check-exchange circuit that updates a plurality of the extrinsic check indices based on the extrinsic bit indices for the bit nodes to transmit to the check nodes; and a reliability-updating circuit that updates the reliability index of and determines an updated value for each of the bit nodes. | 05-13-2010 |
| 20100122122 | WIRED NETWORK CONNECTION ESTABLISHING METHOD AND NETWORK DEVICE FOR PERFORMING THE METHOD - A wired network connection establishing method includes the steps of: configuring two network devices to exchange connection capacity information with each other through first and second twisted pair cables of a network cable, the connection capacity information including at least a first connection mode using four of the twisted pair cables, a second connection mode using three of the twisted pair cables, and a third connection mode using two of the twisted pair cables; configuring the two network devices to detect a number of the twisted pair cables in the network cable capable of supporting a normal connection; and configuring the two network devices to determine which one of the first, second, and third connection modes is to be used for establishing a connection based on the number of the twisted pair cables capable of supporting a normal connection. | 05-13-2010 |
| 20100117736 | LINE DRIVER CAPABLE OF AUTOMATIC ADJUSTMENT OF OUTPUT IMPEDANCE - A line driver includes an output terminal set for outputting an output signal, a differential amplifier for amplifying an input signal, a series resistor set coupled between the differential amplifier and the output terminal set, a negative-feedback resistor set coupled to the differential amplifier, a feedback variable resistor set coupled between the differential amplifier and the output terminal set, and an adjusting unit coupled to the feedback variable resistor set. The adjusting unit is operable to adjust resistances of the feedback variable resistor set according to the output signal. | 05-13-2010 |
| 20100098140 | NETWORK COMMUNICATIONS DEVICE CAPABLE OF PROMOTING CONNECTION QUALITY AND METHOD THEREOF - A network communications device is capable of promoting connection quality, and includes: a plurality of transmitting units for outputting a plurality of analog transmit-signals to another network communications device based on a plurality of digital transmit-signals; a plurality of receiving units for outputting a plurality of digital receive-signals based on a plurality of analog receive-signals sent from the another network communications device; an echo canceller for providing a signal for canceling an echo in one of the digital receive-signals; a near end crosstalk canceller for providing a signal for canceling near end crosstalk in one of the digital receive-signals; a decoding circuit for generating a decoded signal based on one of the digital receive-signals subsequent to cancellation of the echo and the near end crosstalk therein; and a power-increasing control circuit for increasing operating power so as to promote connection quality. | 04-22-2010 |
| 20100092044 | Image Processing Apparatus and Method - An image processing apparatus includes: a pixel difference calculator for calculating a difference value between each first pixel of a previous image and a second pixel of a present image and at a position corresponding to said each first pixel, and outputting a plurality of pixel differences; a counter counting a number of positive pixel differences and a number of negative pixel differences in the pixel differences of a sampling window; a motion level determining unit calculating a motion level of a pixel in the sampling window according to the numbers of the positive and negative pixel differences; a blending value determining unit determining a blending value according to the motion level; and an output unit adding together weights of the present and previous images according to the blending value to generate and output an output image. An image processing method is also disclosed. | 04-15-2010 |
| 20100086148 | APPARATUS AND METHOD FOR PROCESSING AUDIO SIGNAL - An apparatus for processing an audio input signal is provided and includes an audio processing circuit and an audio compressing circuit. The audio processing circuit receives the audio input signal, and enhances a first frequency part of the audio input signal to output a bass-enhancement signal. The audio compressing circuit is coupled to the audio processing circuit, and reduces a gain of a second frequency part of the bass-enhancement signal to output an audio output signal. | 04-08-2010 |
| 20100086147 | HARMONICS GENERATION APPARATUS AND METHOD THEREOF - A harmonic generating apparatus and the method are provided, which are used to enhance the quality of the bass audio signals. The method includes the steps of: providing a frequency signal having a present level and a preceding level; comparing the present level with the preceding level to generate a compared result; and generating the plurality of harmonics based on the compared result. | 04-08-2010 |
| 20100083074 | Block Code Decoding Method And Device Thereof - A block code decoding method and device thereof are provided. The procedure of the bounded distance decoding is simplified and the number of correlation calculating is reduced via a set of pre-established XOR masks. The decoding method includes: picking up the source code part of the received message; executing a XOR calculating for the source code part with the XOR masks, and encoding the results thereof to produce a set of compared codes; executing a correlation calculating for the set of compared codes and the received message; and determining a compared code having the maximum correlation result as the decision. | 04-01-2010 |
| 20100080273 | SIGNAL RECEIVING DEVICE AND FREQUENCY DETERMINING CIRCUIT - A signal receiving device is adapted for receiving a multi-bit signal-under-test that supports one of first and second base frequency types, and outputting a type indicator for indicating which one of the first and second base frequency types is supported by the signal-under-test. The signal receiving device includes a counter and a frequency determining circuit. The counter includes an accumulating unit for counting cycles of an operating clock so as to obtain a bit count. The frequency determining circuit is coupled to the counter for comparing the bit count to one of first and second preset values in accordance with a previous value of the type indicator so as to obtain a comparison result, and determining whether to update a value of the type indicator based on the comparison result. | 04-01-2010 |
| 20100074376 | SPHERE DECODING METHOD APPLIED TO MULTI-INPUT MULTI-OUTPUT (MIMO) CHANNEL - A sphere decoding method applied to a MIMO channel is provided. Multiple constellation points of an n | 03-25-2010 |
| 20100074375 | SPHERE DECODING METHOD APPLIED TO MULTI-INPUT MULTI-OUTPUT (MIMO) CHANNEL - A sphere decoding method applied to a MIMO channel is provided. Multiple constellation points of an n | 03-25-2010 |
| 20100074361 | SPHERE DECODING METHOD APPLIED TO MULTI-INPUT MULTI-OUTPUT (MIMO) CHANNEL - A sphere decoding method applied to a MIMO channel is provided. T signals transmitted via the MIMO channel are received. A first triangular matrix corresponding to a channel matrix is generated and mapped from the complex domain into the real domain to obtain a second triangular matrix. A first zero-forcing soft-output solution corresponding to a first estimation layer is found, and multiple preferred points P(1) are obtained. Multiple n-th zero-forcing soft-output solutions corresponding to an n-th estimation layer are obtained according to multiple preferred points P(n−1), and multiple preferred points P(n) are obtained according to PEDs of multiple n-th constellation points. Multiple 2T-th zero-forcing soft-output solutions are obtained according to the preferred points P(2T−1) and multiple preferred points P(2T) are obtained correspondingly. The preferred point P(2T) corresponding to the least PED is mapped from the real domain into the complex domain to generate an optimal solution of the T signals. | 03-25-2010 |
| 20100074352 | SPHERE DECODING METHOD APPLIED TO MULTI-INPUT MULTI-OUTPUT (MIMO) CHANNEL - A sphere decoding method applied to a MIMO channel is provided. Multiple constellation points of an n | 03-25-2010 |
| 20100067539 | Single Network Interface Circuit with Multiple-Ports and Method Thereof - The invention discloses a single network interface device with multi-ports, the network interface device supports two or more physical network transmission routes to transmit and receive data, and upload the received data into a host through a host interface or download the data waiting to be transmitted to network from the host through the host interface. Therefore, the present invention increases network communication speed and improves host interface bandwidth. | 03-18-2010 |
| 20100067277 | Content-Addressable Memory - A CAM includes first and second memory units. The first memory unit includes: a first data memory cell for storing a first data bit; a first comparison circuit for comparing a first search bit with the first data bit to determine if there is a match, and outputting a first comparison result; and a first CMOS logic circuit for performing a logic operation on the first comparison result and outputting a first matching result. The second memory unit includes: a second data memory cell for storing a second data bit; a second comparison circuit for comparing a second search bit with the second data bit to determine if there is a match, and outputting a second comparison result; and a second static CMOS logic circuit for performing a logic operation on the first matching result and the second comparison result, and outputting an output matching result. | 03-18-2010 |
| 20100061495 | APPARATUS FOR PERFORMING CHANNEL ESTIMATION IN A RECEIVING DEVICE - An apparatus for performing channel estimation includes a time-domain estimating circuit to perform a channel estimation on a time-domain received signal to output a time-domain estimated signal, a second frequency-domain converting circuit to convert the time-domain estimated signal into a frequency-domain estimated signal, an error computing circuit to produce an error signal based on the frequency-domain estimated signal and a frequency-domain received signal, and a compensation circuit to compensate the frequency-domain estimated signal using the error signal so as to produce a final channel estimation signal. The apparatus is located in a receiving device that includes a first frequency-domain converting circuit to convert the time-domain received signal into the frequency-domain received signal, and an equalizer to generate a frequency-domain recovered signal based on the frequency-domain received signal and the final channel estimation signal. | 03-11-2010 |
| 20100060348 | BANDWIDTH-ADJUSTABLE FILTER - A bandwidth-adjustable filter includes an operational amplifier, a first resistor, a first capacitor and a first resistor ladder circuit. The operational amplifier has a negative input terminal and a positive input terminal The first resistor is coupled to one of the input terminals of the operational amplifier. The first capacitor is coupled to the first resistor. The first resistor ladder circuit is coupled in parallel to the first resistor for changing the resistance of the first resistor so as to adjust the bandwidth of the filter. | 03-11-2010 |
| 20100058085 | Power-Saving Device and Method - A power-saving device and method are applicable to a first electronic device having at least one connection interface, and the first electronic device is coupled to a second electronic device via a bus. The power-saving device includes a detection circuit, a power control circuit, and a connection control circuit. The detection circuit is coupled to the connection interface, to detect a load state of the connection interface and generate a detection signal. The power control circuit controls power supplied to the first electronic device via the bus in response to a state of the detection signal. The connection control circuit controls a connection state of the bus according to the detection signal. | 03-04-2010 |
| 20100054315 | Apparatus and Method for Start-up in Communication System - A transceiver in a communication system and a start-up method thereof are provided. The transceiver comprises an auto-negotiation circuit, a timing recovery circuit, an interference cancellation circuit and an equalizer. The auto-negotiation circuit performs an auto-negotiation procedure to determine whether the transceiver operates as a master or slave transceiver. If the transceiver operates as a slave transceiver, it executes a first stage and a second stage during the start-up process. In the first stage, the transceiver performs channel estimation to generate a channel estimation value, presets the parameters of the equalizer according to the channel estimation value, and trains the timing recovery circuit and the equalizer; in the second stage, the transceiver trains the interference cancellation circuit. | 03-04-2010 |
| 20100046408 | Apparatus and Method for Power-Saving in Multiple Antenna Communication System - A multiple-antenna transceiver in the present invention includes a frame controller and circuitry for transmitting and receiving. The transmitting component includes a sequence selection circuit, a MIMO modulation and coding circuit, and numerous TX RFE and AFE circuits. The receiving component includes a MIMO demodulation and decoding circuit, a sequence separation circuit, and numerous RX RFE and AFE circuits. The frame controller can enable and disable the TX and RX RFE and AFE circuits individually so as to reduce power consumption of the whole system. | 02-25-2010 |
| 20100036513 | AUDIO MIXING DEVICE AND METHOD - An audio mixing device and method are provided. The audio mixing device includes an analog to digital converter (ADC), a converting module, a mixing module, and a down-sample filter. The ADC is adapted to receive an analog signal, and convert the analog signal into a first digital signal. The converting module receives the second digital signal, and adjusts a data rate of the second digital signal according to a data rate of the first digital signal to generate a third digital signal. The mixing module mixes the first digital signal and the third digital signal to output a mixed signal. The down-sample filters down-samples the mixed to output a down-sampled signal. | 02-11-2010 |
| 20100014621 | Synchronization Determining Circuit, Receiver Including the Synchronization Determining Circuit, and Method of the Receiver - A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed. | 01-21-2010 |
| 20100003927 | APPARATUS AND METHOD FOR POWER-SAVING AND WAKE-UP - Disclosed is an apparatus and method of power-saving and wake-up, which is not only used to reduce the power consumption of a system of electronic equipment, but also allow the system to immediately return to normal operation according to the requirement. The apparatus for power-saving and wake-up includes a first detector, a second detector, a decoder and a third detector. The method for power-saving and wake-up includes detecting a cable signal, a clock pair signal and a differential pair signal. When one of the detected signals is unusual, the system soon turns off the unusual channel power and implement the procedures for power saving and operates under the power saving mode, which can realize the effect of power saving and low power consumption. The method for power-saving and wake-up includes detecting the cable signal, the toggling and frequency of the clock signal and the synchronizing signals of the system. | 01-07-2010 |
| 20100001818 | MEMORY CELL BASED ARRAY OF TUNING CIRCUIT - A method applied in a tuning circuit comprising a plurality of turning cells is disclosed. the method comprises: laying out a array of tuning cells in a matrix configuration, the matrix comprising a first dimension and a second dimension; assigning a first index associated with the first dimension and a second index associated with the second dimension to each tuning cell; controlling each tuning cell using a word line and a bit line; and summing up outputs from all tuning cells to form a combined output. The tuning cell provides a first circuit value or a second circuit value according to the logical value of the bit line, and the difference between the first circuit value and the second circuit value is determined such that a turning resolution of the tuning circuit is determined. | 01-07-2010 |
| 20090323566 | ALL-DIGITAL TIMING CONTROL FOR MULTI-CHANNEL FULL-DUPLEX TRANSCEIVER - A multi-channel full-duplex transceiver is disclosed. The transceiver comprises: a clock generator for generating a first clock and a second clock based on a control code; a plurality of transmitters for transmitting a plurality of outgoing signals onto a plurality of channels, respectively; a plurality of receivers for receiving, sampling, and equalizing in parallel a plurality of incoming signals from said plurality of channels, respectively, to generate in parallel a plurality of equalized signals, respectively; a symbol-rate-converters for converting in parallel said equalized signals into a plurality of refined signals, respectively. In a first operation mode, the control code is established by detecting a timing difference between an output clock of the clock generator and a reference clock. In a second operation mode, the control code is established by detecting a timing embedded in one of said refined signals. | 12-31-2009 |
| 20090323532 | NETWORK SYSTEM WITH QUALITY OF SERVICE MANAGEMENT AND ASSOCIATED MANAGEMENT METHOD - A network system with QoS management and an associated management method are provided. The network system comprises a switch network, a target device, and at least a source device for issuing a packet to the target device via the switch network. The switch network comprises a flow control unit, a switch unit and a scheduling unit. The flow control unit determines whether to output a high priority packet according to a target priority level and a high priority bandwidth quota of the source device, and directly outputs a low priority packet. The switch unit determines a packet forwarding sequence according to a packet arbitration policy. The scheduling unit determines the sequence for packets to enter the target device. The scheduling unit updates the target priority level as the priority level of a packet entering the target device, and informs the flow control unit of the updated target priority level. | 12-31-2009 |
| 20090310395 | Content-Addressable Memory - A content-addressable memory (CAM) comprises a first CAM cell and a second CAM cell. The first CAM cell stores a first data bit, and compares the first data bit with a first search bit to determine if they are matched. The second CAM cell stores a second data bit, and compares the second data bit with a second search bit to determine if they are matched. The first CAM cell comprises a first logic circuit, the second CAM cell comprises a second logic circuit, and the first logic circuit and the second logic circuit form a static CMOS logic circuit. | 12-17-2009 |
| 20090307518 | ASYNCHRONOUS COUNTER BASED TIMING ERROR DETECTION - A method for estimating a timing difference between a first clock signal and a second clock signal is disclosed. The estimating method comprising: generating an edge signal by detecting an edge of the second clock signal by sampling the second clock signal using the first clock signal; generating a delayed edge signal by a further sampling of the second clock signal using the first clock signal; generating a first intermediate code by counting a number of clock edges of the first clock signal within a duration defined by the edge signal using an asynchronous counter; generating a second intermediate code to represent a timing difference between the second clock signal and the delayed edge signal using a time-to-digital converter; and generating an output code using a weighted sum of the first intermediate code and the second intermediate code. | 12-10-2009 |
| 20090304140 | ASYNCHRONOUS PING-PONG COUNTER AND THEROF METHOD - An asynchronous ping-pong counter is disclosed. The asynchronous ping-pong counter comprises a first asynchronous counter, a second synchronous counter, and a controller, the asynchronous ping-pong counter operates between a first state and a second state. In the first state, the first asynchronous counter counts a first number of clock edges of a fast clock signal, and the second asynchronous counter holds a first counter output value. In the second state, the second asynchronous counter counts a second number of clock edges of the fast clock signal, and the first asynchronous counter holds a second counter output value. The controller determines a state transition based on a sampling of a slow clock signal by the fast clock signal. | 12-10-2009 |
| 20090292836 | DATA ACCESS DEVICE AND METHOD FOR COMMUNICATION SYSTEM - A data access device for a communication system includes: a write controller controlled by the host and outputting a write pointer; a read controller controlled by the write pointer and outputting a read pointer; a download timing controller comparing the write and read pointers to determine a timing of downloading data from the host, and including a pointer difference calculator and a comparator, the pointer difference calculator calculating a distance between the write and read pointers to obtain a pointer difference, the comparator outputting a download status indication according to the pointer difference and a first predetermined length to provide a basis for changing the write pointer; and a transmit buffer downloading data from the host according to the write pointer and transmitting data to the network interface according to the read pointer. A data access device for a network interface controller and a data access method are also disclosed. | 11-26-2009 |
| 20090290551 | CHANNEL UTILIZING METHOD AND SYSTEM FOR WIRELESS NETWORKS - A channel utilizing method for a wireless network is adapted for channel utilization by a switch node having a number (N) of transceivers in an environment with a number (M) of channels, wherein (N)<(M). The channel utilizing method includes the steps of: calculating a channel weight set, and selecting one of the (M) channels according to the channel weight set; determining a notify mechanism according to a relation between the switch node and a neighbor node; using the notify mechanism to notify the neighbor node of a current state of the switch node; and calculating a channel stay-in period, and causing the switch node to stay in the selected one of the channels for a duration of the channel stay-in period. A channel utilizing system is also disclosed. | 11-26-2009 |
| 20090286577 | Communication System Capable of Adjusting Power Consumed Thereby - A communication system capable of adjusting power consumed thereby is adapted for receiving connection information. The communication system includes first and second transceiving devices. The first transceiving device includes a transmitting end and a service end for receiving the connection information. The second transceiving device includes a receiving end capable of forming a communications link with the transmitting end. A power state of each of the first and second transceiving devices is switchable between a power-supplied mode and a power-saving mode. The power state alters status of the communications link. | 11-19-2009 |
| 20090274049 | NON-BLOCKED NETWORK SYSTEM AND PACKET ARBITRATION METHOD THEREOF - A non-blocked network system and a packet arbitration method thereof are provided to dynamically adjust packet arbitration policy, thereby avoiding the congestion of packet traffic. The non-blocked network system includes a switch network, a source device and a target device. The switch network includes at least a first switch unit and a second switch unit. A first path and a second path connect between the first and second switch units. The target device is coupled to the second switch unit, and the source device is coupled to the first switch unit. Before issuing a first packet to the target device via the first path, the source device issues a corresponding token of the first packet to the second switch unit via the second path, so as to inform the second switch unit that the first packet will pass the first path soon. The second switch unit dynamically adjusts its packet arbitration policy according to the token, so as to determine the forwarding sequence of a second packet to be forwarded on the first path. | 11-05-2009 |
| 20090267698 | DUAL SUPPLY INVERTER FOR VOLTAGE CONTROLLED RING OSCILLATOR - A voltage controlled ring oscillator reduces sensitivity of an oscillation frequency to a control voltage by using a dual supply inverter logic circuit. The dual supply inverter logic circuit includes two inverter circuits coupled in parallel between an input terminal and an output terminal. The first inverter circuit is powered by a variable supply voltage while the second inverter circuit is powered by a substantially fixed supply voltage. The variable supply voltage serves as the control voltage for the voltage controlled ring oscillator and sets the oscillation frequency. The sensitivity of the oscillation frequency to changes in the variable supply voltage is reduced due to the parallel connection of the second inverter circuit powered by a different supply voltage. | 10-29-2009 |
| 20090267668 | METHOD AND APPARATUS FOR CALIBRATING A DELAY CHAIN - Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed. | 10-29-2009 |
| 20090261896 | LEAKAGE CURRENT SUPPRESSING CIRCUIT AND SEMICONDUCTOR CHIP - A leakage current suppressing circuit includes a bias generating unit and a switch unit. The bias generating unit is adapted to be coupled to a power source and an output terminal, and generates a bias voltage substantially equal to a voltage at the power source when the power source is turned on, and substantially equal to a voltage at the output terminal when the power source is turned off. The switch unit includes a first P-type transistor having a first terminal adapted to be coupled to the power source, a second terminal adapted to be coupled to the output terminal, a gate terminal, and a body terminal coupled to the bias generating unit for receiving the bias voltage therefrom. | 10-22-2009 |
| 20090261878 | METHOD AND APPARATUS FOR AMPLIFYING A TIME DIFFERENCE - Various methods and apparatus can be used for amplifying a time interval in a variety of applications. In an embodiment, a feedback device is implemented in a time amplifier in conjunction with an output device of the time amplifier. | 10-22-2009 |
| 20090257752 | NETWORK MEDIA SELECTING METHOD AND DEVICE THEREOF - A method for operating a network device is provided. The method comprises steps of providing a first transceiver to establish a first link via a first medium; providing a second transceiver to establish a second link via a second medium; and enabling one of the first and the second transceivers to establish a corresponding one of the first and second links according to a predetermined order, wherein a media access controller transmits a first datum via the first medium by using the first link, and transmits a second datum via the second medium by using the second link. | 10-15-2009 |
| 20090206962 | INTEGRATED FRONT-END PASSIVE EQUALIZER AND METHOD THEREOF - A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit. | 08-20-2009 |
| 20090193381 | POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh management method utilized in an integrated IC. The integrated circuit includes a macro block including at least a macro block power supplying line growing along a first direction. The management method includes: defining a plurality of first power supplying lines located in a metal layer above the macro block, wherein each of the first supplying lines grows along the first direction; defining a plurality of second power supplying lines located in another metal layer above the macro block, wherein each of the second supplying lines grows along a second direction; defining a partial power supplying line from the plurality of first power supplying lines where the partial power supplying line overlaps the macro block power supplying line; and removing the partial power supplying line from the plurality of first power supplying lines. | 07-30-2009 |
| 20090193271 | POWER MESH MANAGEMENT METHOD - The invention discloses a power mesh managing method utilized in an integrated circuit. The integrated circuit includes a standard cell and a standard-cell power supplying mesh corresponding to a first direction. The power mesh managing method includes: defining a power supplying network including a first plurality of power meshes growing along the first direction and a second plurality of power meshes growing along a second direction, and defining an assistant connecting network on a third metal layer, wherein the assistant connecting network includes a plurality of assistant connecting lines growing along the second direction, the first plurality of power meshes are formed on a first metal layer, the second plurality of power meshes on a second metal layer, the third metal layer is below the first metal layer, and the second metal layer is above the first metal layer. | 07-30-2009 |
| 20090193167 | ARBITRATION DEVICE AND METHOD - An arbitration device receives a plurality of requests from a plurality of circuits, and grants access to one of the plurality of circuits. The arbitration device includes a sorter and an arbitrator. The sorter receives position information of an image signal including a plurality of image layers and determines an access priority including a first group and a second group according to the position information. The arbitrator receives the access priority and at least one of the plurality of requests, and grants the access to one of the plurality of circuits according to the access priority and the at least one of the plurality of requests. In addition, each of the plurality of circuits generates data for each of the image layers correspondingly. | 07-30-2009 |
| 20090167276 | Soft-Start Circuit and Method Thereof - A soft-start circuit and a method thereof are described. The circuit includes an amplifier and a voltage ramp generator. The amplifier has a first input end, a second input end, an output end, and a power source control end. The first input end is coupled to a reference voltage. The second input end is coupled to a feedback voltage. The output end outputs an output voltage, and the feedback voltage corresponds to the output voltage. The voltage ramp generator is coupled to the power source control end, and generates a ramp-up voltage. When the ramp-up voltage is lower than a threshold value, the output voltage rises with the ramp-up voltage. When the ramp-up voltage is not lower than the threshold voltage, the output voltage remains at a stable value. A surge current occurring during smooth soft-start or even in operation is thus prevented. | 07-02-2009 |
| 20090163166 | PHASE LOCK LOOP WITH PHASE INTERPOLATION BY REFERENCE CLOCK AND METHOD FOR THE SAME - The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer. | 06-25-2009 |
| 20090161803 | Receiver and gain control method thereof - An analog and digital auto-gain control method includes the steps of: providing a gain-mapping table; determining an analog gain level according to power of a far-end transmitted signal; obtaining a gain-mapping value from the gain-mapping table according to the analog gain level; obtaining a digital gain value according to the gain-mapping value; and adjusting a gain of a digital signal according to the digital gain value. A receiver that performs the auto-gain control method is also disclosed. | 06-25-2009 |
| 20090154568 | MULTIMEDIA DECODING APPARATUS AND METHOD - A multimedia decoding apparatus and method thereof can accelerate decoding speed. The multimedia decoding apparatus is adapted for decoding a multimedia packet that includes a header portion and a data portion. The multimedia decoding apparatus includes a header parsing module, a storage unit, and a data processing module. The header parsing module receives the multimedia packet and parses the header portion of the multimedia packet to output at least one parameter. The storage unit is coupled to the header parsing module for storing the parameter and the data portion of the multimedia packet. The data processing module is coupled to the storage unit for processing the data portion of the multimedia packet according to the parameter. When the data processing module processes the data portion of the multimedia packet, the header parsing module parses the header portion of another multimedia packet simultaneously. | 06-18-2009 |
| 20090153732 | METHOD AND APPARATUS FOR ADAPTIVE SELECTION OF YC SEPARATION - A method for adaptive selection of YC separation is provided. While a video decoder is re-sampling, a frequency of a re-sampling signal and a pixel rate of an output signal have a fixed relation, which is used to determine if a sampling frequency of the signal is deviated. And, accordingly, an appropriate Y/C separation is selected and then performed to obtain a better image quality. | 06-18-2009 |
| 20090153574 | METHOD AND SYSTEM FOR UPDATING FIRMWARE - A system for updating firmware through a DisplayPort interface includes a source device with a DisplayPort interface, and a sink device with a DisplayPort interface. The source device includes a storage circuit for storing and providing an updated firmware, and a source device auxiliary channel for outputting the updated firmware with an auxiliary channel signal format. The sink device includes a sink device auxiliary channel for receiving the updated firmware with the auxiliary channel signal format and thereby generating an output signal, an I | 06-18-2009 |
| 20090135962 | Digital slicing device - A digital slicing device is provided for making a numerical value determination with respect to an inputted modulated symbol so as to output a corresponding symbol. The digital slicing device includes a demodulating unit, a slicing unit and a re-modulating unit. The demodulating unit is for collecting at least two successive modulated symbols and for demodulating the two modulated symbols according to a modulation algorithm so as to generate two demodulated symbols. The slicing unit is for rounding the two demodulated symbols so as to generate two rounded demodulated symbols. The re-modulating unit is for re-modulating the two rounded demodulated symbols according to the modulation algorithm so as to generate two re-modulated symbols corresponding to the two modulated symbols. The two modulated symbols are generated simultaneously through conversion using the modulation algorithm. | 05-28-2009 |
| 20090135255 | METHOD AND APPARATUS FOR DETECTING A NOISE VALUE OF A VIDEO SIGNAL - A method for detecting a noise value of a video signal comprises the steps of determining a spatial domain difference according to a plurality of pixels of a first frame of the video signal, determining a temporal domain difference according to the pixels of the first frame of the video signal and a plurality of pixels of a second frame of the video signal, and generating a noise value of the first frame of the video signal according to the spatial domain difference and the temporal domain difference. An apparatus for detecting a noise value of a video signal performs the aforementioned method. | 05-28-2009 |
| 20090115527 | OUTPUT STAGE CIRCUIT AND OPERATIONAL AMPLIFIER THEREOF - The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention. | 05-07-2009 |
| 20090115524 | OUTPUT STAGE CIRCUIT AND OPERATIONAL AMPLIFIER THEREOF - The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, extra frequency compensating components for compensating the transistor of the output stage circuit is no longer necessary, and saving circuit layout area and cost can be achieved by the present invention. | 05-07-2009 |
| 20090103752 | DEVICE AND METHOD FOR AUTOMATICALLY ADJUSTING GAIN - A device and method are provided for automatically adjusting gain, including a conversion module for converting an audio time-domain signal to an audio frequency-domain signal, an analysis module for analyzing the audio frequency-domain signal in accordance with an equal-loudness level contour of human hearing so as to generate strength weightings and generating a signal strength in accordance with the weightings, a calculation module for calculating a gain by analysis of the audio frequency-domain signal when the signal strength falls outside a default range, and a control module for generating an audio output signal in accordance with the gain and the audio time-domain signal. | 04-23-2009 |
| 20090094696 | SCANNING CIRCUIT AND METHOD FOR DATA CONTENT - The present invention relates to a data scanning circuit and method. According to the present invention, a memory circuit stores a plurality of codes. Each of the code corresponds to a sub-rule. The memory circuit outputs at least first bit and at least second bit of each code, respectively, according to a first and a second data items. An operational circuit performs logic operations on the first and second bits, and produces an operated result. A decision circuit decides whether the input data satisfies the scanning rule according to the operated result. | 04-09-2009 |
| 20090085681 | HIGH-RESOLUTION DIGITALLY CONTROLLED OSCILLATOR AND METHOD THEREOF - A digitally controlled oscillator provides high resolution in frequency tuning by using a digitally controlled capacitive network that includes a tunable capacitive circuit, a first capacitor and a second capacitor. The tunable capacitive circuit generates a variable capacitance according to a digital control word. The first capacitor is coupled in an electrically parallel configuration with the tunable capacitive circuit. The second capacitor is coupled in an electrically serial configuration with a combination of the first capacitor and the tunable capacitive circuit. The first capacitor and the second capacitor are sized such that an effective capacitance of the digitally controlled capacitor network has a step size that is a fraction of a step size of the variable capacitance in response to an incremental change in the digital control word. | 04-02-2009 |
| 20090074125 | TIME-INTERLEAVED CLOCK-DATA RECOVERY AND METHOD THEREOF - A clock-data recovery (CDR) that employs a time-interleaved scheme is disclosed. the circuit comprises: a time-interleaved sampler/phase-detector circuit for receiving an input voltage signal and a plurality of clock signals and outputting N-bit data and N phase signals, wherein N is an integer greater than 1; a control circuit, coupled to the time-interleaved sampler/phase-detector circuit, for receiving the N phase signals and converting the N phase signals into a control signal; and a controlled oscillator, coupled to the control circuit, for generating the plurality of clock signals under the control of the control signal. The CDR is used to relax circuit speed requirement by time-interleaving phase detection by using a multi-phase lower speed circuit. | 03-19-2009 |
| 20090073012 | SELF-CALIBRATING DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF - A digital-to-analog converter improves differential non-linearity by performing a calibration of at least one weighted cell in response to a calibration command. The digital-to-analog converter includes a group of weighted cells, a tunable cell having a tunable weight controlled by a tuning word, and a calibration cell to generate a combined output signal in response to a digital input word, the calibration command, and a calibration sequence. The digital-to-analog converter also includes a calibration circuit configured to sample and subsequently process the combined output signal to establish the tuning word in accordance with the calibration command and the calibration sequence. | 03-19-2009 |
| 20090066393 | SWITCH CIRCUIT - A switch circuit includes a pair of metal oxide semiconductor (MOS) switches and an adjusting unit. Each of the MOS switches has an input terminal and an output terminal. The MOS switches receive a pair of differential input voltages at the input terminals thereof, and output a pair of differential output voltages at the output terminals thereof when the MOS switches conduct. The adjusting unit changes a difference between common mode levels of the input terminals and the output terminals of the MOS switches so as to adjust linearity of differential mode resistances of the MOS switches. | 03-12-2009 |
| 20090066373 | DEVICE FOR ADJUSTING CHIP OUTPUT CURRENT AND METHOD FOR THE SAME - A device for adjusting chip output current and a method for the same are provided. The device includes: a driving circuit for outputting a driving current according to a control signal, wherein the driving current flows to a reference resistor in another chip so as to generate an output voltage; and a detecting circuit coupled to the driving circuit and adapted for detecting the output voltage and a reference voltage, so as to generate the control signal; wherein the control signal controls the number of parallel connections of NMOS transistors or PMOS transistors in the driving circuit, so as to adjust the magnitude of the driving current. | 03-12-2009 |
| 20090054012 | Transmitter and Transmission Method Thereof - A signal transmission method includes: converting an input signal to generate a first converted signal having a first bandwidth, and a second converted signal having a second bandwidth; mixing the first converted signal with an oscillation signal to generate a first mixed signal, and mixing the second converted signal with the oscillation signal to generate a second mixed signal; and transmitting the first and second mixed signals by different antennas; wherein the input signal has a predetermined bandwidth, the first bandwidth is smaller than the predetermined bandwidth; and the second bandwidth is smaller than the predetermined bandwidth. | 02-26-2009 |
| 20090051040 | POWER LAYOUT OF INTEGRATED CIRCUITS AND DESIGNING METHOD THEREOF - The invention discloses a technique for designing the power layout of an integrated circuit. The power layout design forms a power mesh and a power ring with a plurality of metal trunks with uniform line width. In particular, the power ring includes a plurality of metal rings, which are formed by arranging denser layout of the metal trunks with uniform line width. The power ring serves as a function of receiving and providing a power source to the elements of the integrated circuit. | 02-26-2009 |
| 20090046804 | NETWORK DEVICE AND TRANSMISSION METHOD THEREOF - A network device and a transmission method thereof are disclosed. The network device consists of a first network device and a second network device. According to at least one command, the first network device generates serial command, inserts the serial command into gaps between packet data and transmits the serial command to the second network device while outputting those packet data to the second network device. In accordance with the serial command received, the second network device saves data in a register of the second network device. Therefore, the transmission circuit is simplified, heat dissipation efficiency is improved and accuracy of signal transmission is ensured. Moreover, data in the register is retrieved precisely. | 02-19-2009 |
| 20090040087 | DATA WEIGHTED AVERAGE CIRCUIT AND DYNAMIC ELEMENT MATCHING METHOD - A data weighted average circuit is disclosed which includes a lookup unit and a storage unit. The invention uses a lookup table to speed up the circuit operation. Besides, the operation delay is not affected by various orders of the data weighted average circuit and various bit-widths of input data. | 02-12-2009 |
| 20090029668 | LOW FLICKER NOISE ACTIVE MIXER AND METHOD THEREOF - A low flicker noise active mixer comprises a trans-conductance section, a switching quad, and a load section. The trans-conductance section converts a voltage signal pair into a first current signal pair. The switching quad converts the first current signal pair into a second signal pair in a manner controlled by a LO (local oscillator) signal pair. The load section provides a loading to the second current signal pair using a pair of commutative active loads to convert the second current signal pair into an output voltage signal pair. | 01-29-2009 |
| 20090015319 | VOLTAGE CONTROLLED OSCILLATION CIRCUIT - The present invention provides a voltage controlled oscillator, which includes an amplifier circuit, an amplifier circuit tail current source, a latch circuit, a latch circuit tail current source, a load resistor, and a current modulation circuit. The amplifier circuit is provided with a first node, and an amplifier circuit tail current source having one end coupled to the first node and the other end coupled to the ground voltage (V | 01-15-2009 |
| 20080313451 | DATA RECOVERY METHOD - The present invention provides a data recovery method in a system with storage of default values and prior configuration values, including executing initialization of the system; loading the default values; detecting a status of a first flag to generate a first detection result; and, determining whether a boot-up sequence is complete according to the first detection result. | 12-18-2008 |
| 20080303591 | AMPLIFYING CIRCUIT AND ASSOCIATED LINEARITY IMPROVING METHOD - An amplifying circuit and an associated linearity improving method are provided to correct the AM to PM distortion of an amplifier, thereby improving the amplifier linearity. The amplifying circuit includes an amplifier and a correcting unit. The amplifier has a non-linear input capacitor. The correcting unit generates a correction signal according to an input signal of the amplifier, and performs an AM to PM correction according to the correction signal, thereby making the amplifier have an approximately linear equivalent input capacitor. | 12-11-2008 |
| 20080298721 | APPARATUS AND METHOD THEREOF - The invention discloses a apparatus and related method. The apparatus comprises a front-end circuit, a back-end circuit and a determining unit. The front-end circuit is for measuring an image signal, determining the mode of the image signal according to the data of the image signal, and fetching image signal of the image signal. The back-end circuit is for processing the image signal according to the above-mentioned mode, and generating a feedback signal according to the status of the image signal after fetching there-to-fore. The determining unit is for generating a control signal to the front-end circuit according to the feedback signal for adjusting the setting of the mode. | 12-04-2008 |
| 20080297511 | MODE DETECTING CIRCUIT AND METHOD THEREOF - The invention discloses a mode detection circuit and a method thereof, for detecting an image signal, the image signal includes a horizontal resolution and the vertical resolution. The mode detection circuit includes a measuring unit, a calculation unit, and a decision unit. The measuring unit receives a clock signal and is used to count the clock signal to output a first counting value and the second counting value. The calculation unit is used to perform the calculation with the first counting value and the second counting value and thereby outputting a calculating value, wherein the calculating value outputted by the calculation unit is corresponding to the ratio of the first counting value to the second counting value. The decision unit is used to determine the horizontal resolution or the vertical resolution according to the calculating value. | 12-04-2008 |
| 20080297271 | MULTI-PHASE LAYOUT STRUCTURE AND METHOD - The present invention provides a multi-phase layout structure and method. The layout structure comprises: a first layout layer; a second layout layer substantially parallel to the first layout layer; a plurality of traces, each transmitting a signal, and the plurality of signals having a phase difference between each other; wherein a horizontal coupling capacitance is provided between two neighboring traces configured on the same layer of the first layout layer and the second layout layer, a vertical coupling capacitance is provided between two neighboring traces configured on different layers of the first layout layer and the second layout layer, and the plurality of traces have substantially the same total coupling capacitance wherein the total coupling capacitance is defined by the horizontal coupling capacitance and the vertical coupling capacitance. | 12-04-2008 |
| 20080297254 | CLASS AB AMPLIFIER - A class AB amplifier includes: a voltage amplifier stage operating off a first source voltage, and amplifying a differential input voltage to produce a first amplified voltage; a level shift stage coupled to the voltage amplifier stage and adjusting a direct current level of the first amplified voltage to produce a first shift voltage; and a power amplifier stage coupled to the level shift stage, operating off a second source voltage, and converting the first shift voltage to produce a first output current. The second source voltage is larger than the first source voltage. | 12-04-2008 |
| 20080294965 | Data Writing Method For Flash Memory and Error Correction Encoding/Decoding Method Thereof - A data writing method for flash memory and an error correction encoding/decoding method thereof are disclosed. In an embodiment of the data writing method, a 6-bit ECC scheme using a Reed-Solomon code derived from a Galois Field GF (2 | 11-27-2008 |
| 20080291068 | CURRENT OUTPUT CIRCUIT WITH BIAS CONTROL AND METHOD THEREOF - A current output circuit with bias control and a method thereof are provided. The current output circuit includes a current mirror circuit comprising a first transistor and a second transistor having respectively two drains, and a control circuit coupled to the current mirror circuit. The control circuit receives drain voltages of the first transistor and the second transistor, and adjusts a respective gate bias of the first transistor and the second transistor according to a respective drain voltage thereof. | 11-27-2008 |
| 20080290375 | INTEGRATED CIRCUIT FOR VARIOUS PACKAGING MODES - The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The selection circuit is coupled between the core circuit and the pads for determining the connection state between the core circuit and the pads based on a control signal. When the control signal provides a first value, the core circuit and the pads will be in a first connection state, and the integrated circuit will be applied with a single-die package. However, when the control signal provides a second value, the core circuit and the pads will be in the second connection state, and the integrated circuit will be applied with a multi-die package. | 11-27-2008 |
| 20080285851 | COLOR CORRECTION METHOD AND APPARATUS OF DISPLAY APPARATUS - The invention discloses a color correction method for adjusting the color performance of a display apparatus. The color correction method first displays a plurality of images on a panel of the display apparatus and measures the chromatic value and the luminance of each image so as to obtain the color characteristics of the display apparatus. According to the color characteristics, a corresponding color matrix is generated which is located at the CIE XYZ color space. Next, an output matrix is outputted by performing an operation between the color matrix and a gain matrix. Next, the elements in gain matrix are adjusted in order to have the output matrix be equal to a target matrix substantially. Finally, the display apparatus is set for calibrating the color performance thereof in accordance with the elements of the adjusted gain matrix. | 11-20-2008 |
| 20080284513 | FULLY DIFFERENTIAL AMPLIFIER - A fully differential amplifier includes: an N-stage amplifier including first to Nth amplifier stages, where N is a positive integer greater than or equal to 2, the first to Nth amplifier stages being cascaded in sequence so as to generate a pair of differential output voltages; a common mode feedback circuit coupled to the N-stage amplifier, detecting a common mode level of the differential output voltages, and controlling the first amplifier stage according to the common mode level detected thereby; and a common mode frequency compensation circuit including a pair of capacitors, each having a first terminal coupled to the N-stage amplifier to receive a respective one of the differential output voltages, and a second terminal coupled to a common mode node of the first to (N-1)th amplifier stages of the N-stage amplifier. | 11-20-2008 |
| 20080267277 | DIGITALLY SYNCHRONIZED RECEIVING DEVICE AND ASSOCIATED SIGNAL PROCESSING METHOD - A digitally synchronized receiving device and an associated signal processing method are provided. The digitally synchronized receiving device can receive data transmitted by a transmitter. The transmitter and the receiving device belong to a first clock domain and a second clock domain respectively. The receiving device performs synchronization in a digital manner, so as to deal with the problem of the analog solution in prior arts and the synchronization for interference cancellation. | 10-30-2008 |
| 20080266240 | Apparatus and method for contrast control - An apparatus for contrast control and an associated method are provided. The apparatus can adjust the backlight brightness for a white or black frame to enhance the contrast of a display device, and keep the backlight brightness at a suitable level for other frames to avoid lowering the contrast of a single frame. The apparatus includes a frame detection unit and a backlight control unit. The frame detection unit detects whether an input frame is a white or black frame, and outputs a corresponding detection signal; the backlight control unit generates a backlight control signal according to the detection signal, thereby controlling the brightness of a backlight source of the display device. | 10-30-2008 |
| 20080257960 | CONTROL CHIP OF A CARD READER AND METHOD FOR DETECTING INTERFERENCE THEREOF - A control chip of a card reader providing at least one card detection pin for detecting memory cards connected to corresponding read/write interfaces. The card detection pin is for the prevention of mutual interference caused by the memory cards connected with shared pins of the control chip. The card detection pin of the memory card may be used for the detection of another memory card being inserted into or pulled out from a read/write interface when the control chip of the card reader is accessing a memory card. An interference-acknowledgement signal is generated for the prevention or correction of accessing errors. | 10-23-2008 |
| 20080254842 | TRANSCEIVER WITH POWER-SAVING FUNCTION AND THE METHOD THEREOF - The present invention provides a transceiver with power-saving function and the method thereof, in which when the network is on link-down status, the transmitter will enter the power-saving mode, and with an auxiliary circuit to provide a comfortable common-mode voltage and to present comfortable impedance matching to save the power consumption. | 10-16-2008 |
| 20080253489 | Apparatus and Method for interference cancellation in receiver of communication system - An apparatus and method for interference cancellation is provided to cancel the interference such as echo and cross-talk received by a receiver of a communication system. The apparatus includes a digital cancellation signal generator, a first canceller, and a second canceller. The digital cancellation signal generator can generate a digital cancellation signal, which includes a first and a second portion and represents an interference signal within a received signal. The first canceller can perform an analog cancellation on the received signal to output a partially-interference-canceled received signal according to the first portion of the digital cancellation signal. The second canceller can perform a digital cancellation on the partially-interference-canceled received signal according to the second portion of the digital cancellation signal. | 10-16-2008 |
| 20080252373 | Low Flicker Noise Operational Amplifier - A low flicker noise operational amplifier comprises two circuit branches of the same topology and a plurality of current source pairs. For each current source pair, the two current sources are commutatively steered into the two circuit branches via two sets of differential pair in a manner controlled by a pair of complementary logical signal. | 10-16-2008 |
| 20080246642 | Digital-to-analog signal converter, and digital-to-analog signal converting method - A digital-to-analog signal converter includes a digital-to-analog signal converting unit adapted for converting a digital video signal into a pair of analog differential current signals by current steering, and a driving unit coupled to the digital-to-analog signal converting unit for converting the analog differential current signals into a driving voltage signal that is adapted for driving a display device. A digital-to-analog signal converting method for driving a display device is also disclosed. | 10-09-2008 |
| 20080239147 | DIGITAL DISPLAY CONTROL DEVICE AND METHOD THEREOF - The invention discloses a display control device and method thereof. The display control device and method thereof utilize the phase deviation and the frequency deviation between the output signal and the input signal caused during channel switching to provide converting time acceptable by a display device and to achieve the objective of balancing the data stream transmission. | 10-02-2008 |
| 20080219357 | APPARATUS AND METHOD THEREOF FOR ENCODING/DECODING VIDEO - An apparatus and method for encoding/decoding an input video complied with a fixed frame rate standard and adjusting bit-stream of an encoded/decoded video in real-time. The apparatus comprises a video encoder, a control circuit, an interface, and a buffer. The control circuit is used for monitoring the utility status of the buffer and thereby controlling the operation of the video encoder to achieve real-time adjustable time-varying throughput for various transmission environments. | 09-11-2008 |
| 20080211582 | WIDE-BAND ADJUSTABLE GAIN LOW-NOISE AMPLIFIER - A wide-band adjustable gain low-noise amplifier (LNA) is disclosed. In various embodiments, the LNA includes a first sub-circuit and a second sub-circuit coupled in parallel. In various embodiments, the first sub-circuit includes an amplifier configured to receive power when a logical signal is asserted and de-powered otherwise. In various embodiments, the second sub-circuit includes an amplifier configured to shunt an input node to a reference node using a resistor when the logical signal is de-asserted. Methods according to various embodiments of the invention are also disclosed. | 09-04-2008 |
| 20080198052 | FILTER APPLIED IN SIGMA-DELTA MODULATOR AND FILTERING METHOD THEREOF - A filter applied in a sigma-delta modulator includes an integrator, a signal attenuator and a feedback circuit, in which these components are connected in series sequentially to form a local feedback circuit. The integrator integrates an input signal to output an integral signal. Accordingly, the signal attenuator attenuates the integral signal to output an attenuation signal to the local feedback circuit so as to share a part of attenuation amount to reduce the chip area of the sigma-delta modulator. | 08-21-2008 |
| 20080197907 | DRIVER AMPLIFIER CIRCUIT - A driver amplifier circuit is provided which includes a voltage level shifting circuit and an Op-Amp. A positive power supply terminal and a negative power supply terminal of the Op-Amp receive a first reference voltage and a second reference voltage outputted from the voltage level shifting circuit, causing a DC voltage level of an output signal to be equal to 0V. Meanwhile, the absolute value of a voltage difference between the first reference voltage and the second reference voltage is equal to V | 08-21-2008 |
