| RDC SEMICONDUCTOR CO., LTD. Patent applications |
| Patent application number | Title | Published |
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| 20110191513 | INTERRUPT CONTROL METHOD AND SYSTEM - An interrupt control system comprises: a central processing unit (CPU); a peripheral device; an interrupt controller, and an interrupt preprocessing circuit. The peripheral device optionally issues an interrupt request, and the interrupt controller generates and outputs a first interrupt request signal in response to the interrupt request. The interrupt preprocessing circuit generates and outputs two first interrupt acknowledgement signals to the interrupt controller in response to the first interrupt request signal. An interrupt vector is generated and outputted by the interrupt controller in response to the two first interrupt acknowledgement signals, and the interrupt vector is transmitted to the CPU through the interrupt preprocessing circuit. | 08-04-2011 |
| 20100325400 | MICROPROCESSOR AND DATA WRITE-IN METHOD THEREOF - A microprocessor comprises a register set, a micro operations pool (Uops pool), a hazard detection unit, an execution unit, a dispatch unit, and a mask unit. The Uops pool receives a first micro operation and a second micro operation from a decoder, and reads at least one first operand of the first micro operation and at least one second operand of the second micro operation from the register set. The hazard detection unit detects that the first micro operation is in a write after write hazard state due to the second micro operation. The execution unit executes the first micro operation dispatched from the Uops pool to obtain a first operation result and executes the second micro operation dispatched from the Uops pool to obtain a second operation result. The mask unit protects the first operation result from writing back to the register set according to the write after write hazard state. | 12-23-2010 |
| 20090235210 | ORIENTATION OPTIMIZATION METHOD OF 2-PIN LOGIC CELL - In an orientation optimization, at least one signal chain path starting from a signal source and passing through a series of M 2-pin logic cells is located according to a netlist. An output of the Nth 2-pin logic cell in the series of M 2-pin logic cells, where N| 09-17-2009 | |
| 20090150734 | TRI-STATE I/O PORT - The present invention discloses a tri-state I/O port. The tri-state I/O port comprises a tri-state logic block, a weak buffer and a delay block. The input terminals of the tri-state logic block are connected to data and OE (output enable) signals. When OE signal is enabled, the output terminal of the tri-state I/O block is pulled high when the data is high while the output terminal is pulled low when the data is low. The input terminal and the output terminal of the weak buffer are connected to the output terminal of the tri-state logic block. And the input terminal of the delay block is connected to the output terminal of the tri-state logic block while the output terminal of the delay block is fed back to the tri-state logic block. When the output terminal of the tri-state logic block is low to high/high to low, the weak buffer is active and maintains the output terminal of the tri-state logic block weak high/low while the delay block turns off the pull high/low function of the tri-state logic block. | 06-11-2009 |
