| RAMBUS INC. Patent applications |
| Patent application number | Title | Published |
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| 20120134084 | Memory Modules and Devices Supporting Configurable Core Organizations - Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations. | 05-31-2012 |
| 20120131244 | Encoding Data Using Combined Data Mask and Data Bus Inversion - A data encoding scheme for transmission of data from one circuit to another circuit combines DBI encoding and non-DBI encoding and uses a data mask signal to indicate the type of encoding used. The data mask signal in a first state indicates that the data transmitted from one circuit to said another circuit is to be ignored, and the data mask signal in a second state indicates that the data transmitted from one circuit to said another circuit is not to be ignored. If the data mask signal is in the second state, a first subset of the data is encoded with data bus inversion and a second subset of the data is encoded differently from data bus inversion. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data is transmitted from one circuit to another circuit. | 05-24-2012 |
| 20120117338 | METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES - A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time. | 05-10-2012 |
| 20120117317 | ATOMIC MEMORY DEVICE - In an integrated-circuit memory device having a memory core, a first data value is retrieved from an address-specified location within the memory core in response to a memory access command. The first data value is output from the memory device in response to the memory access command, and a second data value is stored in the address-specified location within the memory core in response to the memory access command. | 05-10-2012 |
| 20120110229 | SELECTIVE SWITCHING OF A MEMORY BUS - A memory bus with a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch between the first bus segment and the second bus segment. The control logic outputs control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in the length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to increase the length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate. | 05-03-2012 |
| 20120087452 | Techniques for Adjusting Clock Signals to Compensate for Noise - A first integrated circuit (IC) has an adjustable delay circuit and a first interface circuit. A first clock signal is provided to the adjustable delay circuit to produce a delayed clock signal provided to the first interface circuit. A second IC has a supply voltage sense circuit and a second interface circuit that transfers data with the first IC. The supply voltage sense circuit provides a noise signal to the first IC that is indicative of noise in a supply voltage of the second IC. The adjustable delay circuit adjusts a delay of the delayed clock signal based on the noise signal. In other embodiments, edge-colored clock signals reduce the effects of high frequency jitter in the transmission of data between integrated circuits (ICs) by making the high frequency jitter common between the ICs. In other embodiments, a supply voltage is used to generate clocks signals on multiple ICs. | 04-12-2012 |
| 20120082203 | SELECTABLE-TAP EQUALIZER - A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval. | 04-05-2012 |
| 20120081146 | SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION - Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver. | 04-05-2012 |
| 20120074983 | Integrated Circuit with Configurable On-Die Termination - Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory. | 03-29-2012 |
| 20120072153 | TECHNIQUE FOR DETERMINING PERFORMANCE CHARACTERISTICS OF ELECTRONIC DEVICES AND SYSTEMS - A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line. | 03-22-2012 |
| 20120069938 | Amplitude Monitor For High-Speed Signals - A serial communication system includes a receiver with an amplitude monitor. The amplitude monitor compares the input signal with a reference level in response to a sample clock. The sample clock is periodically phase shifted with respect to the incoming data so the amplitude monitor is sure to sample an incoming data eye at or near the peak amplitude over a selected sample period. The amplitude detector notes the detection of an input signal if the input signal surpasses the reference level for any sample phase. The amplitude monitor experiments with different sample-clock phases over a number of data symbols, but is capable of measuring amplitude fast enough to resolve amplitude-based signals used for rate negotiation.” | 03-22-2012 |
| 20120057261 | Configurable, Power Supply Voltage Referenced Single-Ended Signaling with ESD Protection - A single-ended data transmission system transmits a signal having a signal voltage that is referenced to a power supply voltage and that swings above and below the power supply voltage. The power supply voltage is coupled to a power supply rail that also serves as a signal return path. The signal voltage is derived from two signal supply voltages generated by a pair of charge pumps that draw substantially same amount of current from a power supply. | 03-08-2012 |
| 20120057260 | Power Supply Shunt - A power supply shunt for an electronic circuit. The power supply shunt includes at least two Field Effect Transistors (FETs), a first of the FETs having its drain coupled to a terminal of an electronic circuit and its source coupled to another of the FETs, and a second of the FETs having its source coupled to ground and its drain coupled to another of the FETs. The first FET has a bulk terminal that floats with respect to ground. | 03-08-2012 |
| 20120044984 | High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 02-23-2012 |
| 20120039139 | Memory Systems and Methods for Dividing Physical Memory Locations Into Temporal Memory Locations - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency. | 02-16-2012 |
| 20120030420 | PROTOCOL FOR REFRESH BETWEEN A MEMORY CONTROLLER AND A MEMORY DEVICE - The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller. | 02-02-2012 |
| 20120027138 | Interference cancellation in variable codelength systems for multi-access communication - A receiver employs low-rate processing to synthesize the effect of high-rate interference in a received multi-rate signal. Each high-rate subchannel is analyzed on its low-rate descendents to produce symbol estimates for each low-rate symbol interval. The symbol estimates are applied to low-rate descendent subchannels, which are then combined to synthesize the effects of the high-rate interference. An interference canceller processes the synthesized interference with the received signal for producing an interference-cancelled signal. Alternatively, analogous steps may be applied at high-rate to analyze, synthesize, and cancel the effects of low-rate interference in a multi-rate signal. | 02-02-2012 |
| 20120023363 | PROTOCOL INCLUDING A COMMAND-SPECIFIED TIMING REFERENCE SIGNAL - Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device. | 01-26-2012 |
| 20120020178 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 01-26-2012 |
| 20120020161 | Multiple Plane, Non-Volatile Memory With Synchronized Control - This disclosure provides a multiple-plane flash memory device where high voltage programming (setting) or erasing (resetting) pulses are timed to occur simultaneously. By regulating when each memory plane (e.g., each logical or physical partition of memory having its own dedicated array control and page buffer) applies high voltage pulses, the overhead circuitry needed to control multiple concurrent operations may be reduced, thereby conserving valuable die space. Both the “program phase” and the “verify phase” of each state change operation cycle may be orchestrated across all planes at once, with shared timing and high voltage distribution. | 01-26-2012 |
| 20120014427 | Methods and Apparatus for Determining a Phase Error in Signals - An integrated circuit includes samplers, a phase error determination circuit, and periodic signal generators. The samplers generate respective sampled signals by sampling respective input signals in response to respective periodic signals. The input signals have a common phase error. The phase error determination circuit receives the sampled signals from the samplers. The phase error determination circuit generates a representation of the common phase error of the input signals in response to sampled signals received in a set-up mode in which the samplers sample respective input signals having a common bit pattern. The periodic signal generators generate the periodic signals differing in phase from one another by defined phase differences in the set-up mode and subject the periodic signals to a common phase shift in a normal mode in response to the representation of the common phase error. The common phase shift matches the common phase error of the input signals. | 01-19-2012 |
| 20120013361 | Synthetic Pulse Generator for Reducing Supply Noise - A source-terminated transmitter conveys digital signals over a short channel as a voltage signal that transitions between levels for each symbol transition. The transmitter produces each transition by issuing a charge pulse onto the channel, and thus creates a series of charge pulses. The number of charge pulses per unit time is proportional to the transition density of the signal, as no charge pulse is required between like symbols. The supply current used to deliver the pulses is therefore dependent upon the data pattern. This data dependency can induce supply fluctuations, which can in turn cause errors and otherwise reduce performance. The transmitter issues a synthetic charge pulse for each adjacent pair of like symbols to reduce the data dependency of the supply current. The synthetic pulses can be scaled to match the charge required for symbol transitions on a given channel. | 01-19-2012 |
| 20120011331 | MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOL - The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which identifies a first row for the activate command. In response to the activate command, the system activates the first row in a first bank in the memory device. Similarly, in response to the precharge command, the system precharges a second bank in the memory device. | 01-12-2012 |
| 20110316590 | Driver Supporting Multiple Signaling Modes - A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination. | 12-29-2011 |
| 20110310949 | High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 12-22-2011 |
| 20110307672 | MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATION - A memory system communicates at least partially temporally overlapping write-data sequences associated with independent column write accesses on data links from a memory controller to a memory device via bidirectional links. Each of these write-data sequences may be associated with a different bank set in the memory IC. These bank sets may be micro-threaded so that each bank set is independently addressable and can concurrently perform operations associated with independent commands, including simultaneous column read/write. Furthermore, temporally interleaved data-mask information for the write-data sequences may be communicated from the memory controller to the memory IC via a data-mask link, so that alternate bits in the interleaved data-mask information may correspond to different write sequences. | 12-15-2011 |
| 20110305271 | High-Speed Signaling Systems With Adaptable Pre-Emphasis and Equalization - A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate. | 12-15-2011 |
| 20110299345 | Early Read After Write Operation Memory Device, System And Method - A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path. | 12-08-2011 |
| 20110292974 | Methods for estimation and interference suppression for signal processing - A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal. | 12-01-2011 |
| 20110291693 | TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES - Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generate a soft-blow signal based on the fuse configuration data, and a fuse circuit that includes a fuse and has first and second operational states corresponding to the fuse being intact and blown, respectively. The fuse circuit is configured to receive the soft-blow signal and to select its operational state to be the first or second operational state based on the received soft-blow signal. | 12-01-2011 |
| 20110289510 | ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS - A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor that does not have control over the address(es) associated with the data, the first processor sends a request, including the instruction to modify the data, to a second processor. Then, the second processor, which already has control of the address(es), modifies the data. Moreover, the first processor can immediately proceed to another instruction rather than waiting for the address(es) to become available. | 11-24-2011 |
| 20110289258 | MEMORY INTERFACE WITH REDUCED READ-WRITE TURNAROUND DELAY - Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links. | 11-24-2011 |
| 20110286280 | Pulse Control For NonVolatile Memory - This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust. | 11-24-2011 |
| 20110276733 | Memory System And Device With Serialized Data Transfer - A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage. | 11-10-2011 |
| 20110275356 | Methods and Circuits for Detecting and Reporting High-Energy Particles Using Mobile Phones and Other Portable Computing Devices - Described are mobile phones that incorporate radiation detectors formed using commonly available semiconductor memories. The radiation detectors require little or no additional hardware over what is available in a conventional phone, and can thus be integrated with little expense or packaging modifications. The low cost supports a broad distribution of detectors. Data collected from constellations of detector-equipped mobile phones can be used to locate mislaid or stolen nuclear materials or other potentially dangerous radiation sources. Phone users can be alerted to radiation dangers in their vicinity, and aggregated phone-specific error data can serve as user-specific dosimeters. | 11-10-2011 |
| 20110264849 | PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER - The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory-access request, the memory controller sends to the memory device a command that specifies performing a timing-calibration operation for a second link. The system subsequently transfers data associated with the memory-access request using the second link, wherein the timing-calibration operation occurs between sending the memory-access request and transferring the data associated with the memory-access request. | 10-27-2011 |
| 20110255615 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System - An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device. | 10-20-2011 |
| 20110255573 | Iterative Interference Suppression Using Mixed Feedback Weights and Stabilizing Step Sizes - A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimate. Receiver embodiments may be implemented explicitly in software of programmed hardware, or implicitly in standard Rake-based hardware either within the Rake (i.e., at the finger level) or outside the Rake (i.e., at the user of subchannel symbol level). | 10-20-2011 |
| 20110251819 | INTEGRATED CIRCUIT TESTING MODULE INCLUDING SIGNAL SHAPING INTERFACE - Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a higher slew rate than the slew rate at which signals are received from the automated testing equipment. In order to do so, the testing interface includes components configured for generating addresses, commands, and test data to be conveyed to the integrated circuit. A variety of test data patterns can be produced and the test data can be address dependent. The systems are optionally configured to include a test plan memory component configured to store one or more test plans. A test plan may include a sequence of test patterns and/or conditional branches whereby the tests to be performed next are dependent on the results of the preceding tests. The test plan memory is, optionally, be detachable from the test module. | 10-13-2011 |
| 20110249774 | Partial Response Equalizer and Related Method - A multi-phase partial response receiver supports various incoming data rates by sampling PrDFE output values at a selected one of at least two clock phases. The receiver includes a calibration circuit that performs a timing analysis of critical data paths in the circuit, and this analysis is then used to select the particular clock phase used to latch the output values. These techniques permit the multiplexer outputs from for each phase of the partial response receiver to directly drive selection of a multiplexer for the ensuing phase, i.e., by avoiding regions of instability or uncertainty in the respective multiplexer outputs. | 10-13-2011 |
| 20110249718 | METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMS - A system for dynamically correcting phase errors between data and a timing reference signal caused by a transient event during data communication between a transmitter and a receiver is described. During operation, the system stores one or more phase-offset values for the event in an offset table, wherein the constituent phase-offset values are associated with phase error caused by the event. Upon detecting a subsequent occurrence of the event, the system adjusts a phase relationship between the data and the timing reference signal based on the one or more phase-offset values. | 10-13-2011 |
| 20110239084 | CODE-ASSISTED ERROR-DETECTION TECHNIQUE - Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error-detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information. | 09-29-2011 |
| 20110239063 | ACTIVE CALIBRATION FOR HIGH-SPEED MEMORY DEVICES - A system for calibrating timing for write operations between a memory controller and a memory device is described. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data from the memory device to the memory controller. The system then transmits a test data pattern to the memory device within the time gap. The system subsequently uses the received test data pattern to calibrate a phase relationship between a received timing signal and data transmitted from the memory controller to the memory device during write operations. | 09-29-2011 |
| 20110238870 | Memory System With Command Filtering - A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode. | 09-29-2011 |
| 20110235764 | MESOCHRONOUS SIGNALING SYSTEM WITH MULTIPLE POWER MODES - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time. | 09-29-2011 |
| 20110235727 | COMMUNICATION CHANNEL CALIBRATION WITH NONVOLATILE PARAMETER STORE FOR RECOVERY - A communication channel is operated by storing a calibrated parameter value in nonvolatile memory during manufacturing, testing, or during a first operation of the device. Upon starting operation of the communication channel in the field, the calibrated parameter value is obtained from the nonvolatile memory, and used in applying an operating parameter of the communication channel. After applying the operating parameter, communication is initiated on a communication channel. The operating parameter can be adjusted to account for drift immediately after starting up, or periodically. The process of starting operation in the field includes power up events after a power management operation. In embodiments where one component includes memory, steps can be taken prior to a power management operation using the communication channel, such as transferring calibration patterns to be used in calibration procedures. | 09-29-2011 |
| 20110235459 | CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM - In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time. | 09-29-2011 |
| 20110228616 | Clock Generator Circuits with Non-Volatile Memory for Storing and/or Feedback-Controlling Phase and Frequency - A clock-signal generator (e.g. a PLL or a DLL) uses non-volatile memory to store an analog control voltage that determines an output phase and/or frequency of the clock-signal generator. Locked loops take time to lock on a given reference frequency. To keep this time to a minimum, NVM | 09-22-2011 |
| 20110228614 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 09-22-2011 |
| 20110222594 | Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. | 09-15-2011 |
| 20110222358 | Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data To Account for Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift. | 09-15-2011 |
| 20110219197 | Memory Controllers, Systems, and Methods Supporting Multiple Request Modes - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices. | 09-08-2011 |
| 20110219162 | Adaptive-Allocation Of I/O Bandwidth Using A Configurable Interconnect Topology - Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention. | 09-08-2011 |
| 20110216611 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. | 09-08-2011 |
| 20110211415 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 09-01-2011 |
| 20110211403 | BIMODAL MEMORY CONTROLLER - A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller. | 09-01-2011 |
| 20110208990 | Regulation of Memory IO Timing - This disclosure provides for adjustment of memory IO timing using a voltage controlled oscillator (VCO) and a register that generates a VCO control voltage directly used to vary memory IO timing. The register may be externally programmable by a controller and may be located on a memory device (IC, module or other device) or on an external voltage generator, which then provides an adjustable voltage to the memory device. This structure may be used to adjust memory timing so as to achieve a minimum target bitrate and thus minimize frequency of operation to minimize power. In one embodiment, each of several memory devices may be independently adjusted in this way to achieve a mesochronous memory system; in another embodiment, memory devices may be have their timing adjusted in parallel, with all memory devices equal to or greater than a target bitrate. Teachings presented herein provide a way to relax overdesign requirements and “tune” fast-fast and slow-slow devices to effectively operate as typical devices. | 08-25-2011 |
| 20110208905 | Non-Volatile Memory Device For Concurrent And Pipelined Memory Operations - This disclosure provides a non-volatile memory device that concurrently processes multiple page reads, erases or writes involving the same memory space. The device relies upon a crossbar and a set of page buffers that may each be dynamically assigned to each read or write request. The device also separates memory array control from IO control, such that multiple cycle state change operations can be performed while the buffers are used to transfer data into and out of the buffers along an external data bus; using this structure, the memory device can accept multiple transactions where pages can be immediately loaded into buffers and then “pipelined” either for transfer to a write data register or to an external bus as appropriate. By significantly mitigating the substantial “busy time” associated with program and erase of non-volatile memory devices, especially flash devices, this disclosure greatly expands potential application of such devices. | 08-25-2011 |
| 20110205406 | Method and Apparatus for Detecting Camera Sensor Intensity Saturation - An apparatus for detecting intensity saturation of a light sensor includes a saturation detector for detecting and measuring an intensity saturation condition of at least one pixel of a light sensor, the intensity saturation condition of the pixel being at saturation upon receiving light with an intensity above a predetermined level, the saturation detector emitting a digital signal with a reserved bit combination indicating the intensity saturation condition of the pixel, and a processor receiving and processing the digital signal from the saturation detector and transmitting a control signal in response to the digital signal to compensate for the intensity saturation condition of the pixel. | 08-25-2011 |
| 20110202789 | PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES - An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols. | 08-18-2011 |
| 20110202709 | OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORY - One embodiment of the present invention provides a method of operation within a flash memory system. During operation, the system receives write data and a corresponding logical address. The system then determines whether the write data matches a predetermined data pattern. If the write data does match the predetermined data pattern, instead of writing the data, the system records an indication that the predetermined data pattern corresponds to the logical address. | 08-18-2011 |
| 20110200151 | Iterative Interference Suppression Using Mixed Feedback Weights and Stabilizing Step Sizes - A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimate. Receiver embodiments may be implemented explicitly in software of programmed hardware, or implicitly in standard Rake-based hardware either within the Rake (i.e., at the finger level) or outside the Rake (i.e., at the user of subchannel symbol level). | 08-18-2011 |
| 20110193591 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 08-11-2011 |
| 20110182330 | Serial cancellation receiver design for a coded signal processing engine - An interference cancelling receiver combines data from multiple paths after aligning to transmitter timing, and uses either an equalizer or a Rake receiver to compute symbol estimates. Interference estimates are generated from the symbol estimates, and multiple interference estimates are combined after re-aligning the interference estimates to receiver timing. At least two segments of symbol estimates are computed for each segment of interference cancelled data. | 07-28-2011 |
| 20110179205 | METHOD AND APPARATUS FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING IN A BUS TOPOLOGY - A method and apparatus for providing bidirectional signaling in a bus topology is provided. The bus topology allows more than two electrical circuits or devices to be coupled together along one or more common electrical conductors. For each device on the bus, a transmit buffer is preferably provided for every other device on the bus with which it will communicate. One or more logic circuits, for example, a scheduler, is provided to coordinate exchange transactions between pairs of devices. Time delays are preferably provided between exchange transactions of different device pairs so as to prevent interference. Coherency checking is preferably implemented to avoid discrepancies introduced by information being held in a buffer pending an exchange transaction. | 07-21-2011 |
| 20110156776 | Locked Loop Circuit With Clock Hold Function - A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal. | 06-30-2011 |
| 20110153932 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 06-23-2011 |
| 20110128041 | Integrated Circuit With Configurable On-Die Termination - Described are integrated-circuit die with differential receivers, the inputs of which are coupled to external signal pads. Termination legs coupled to the signal pads support multiple termination topologies. These termination legs can support adjustable impedances, capacitances, or both, which may be controlled using an integrated memory. | 06-02-2011 |
| 20110128040 | SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION - Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver. | 06-02-2011 |
| 20110127990 | FREQUENCY RESPONSIVE BUS CODING - A data system | 06-02-2011 |
| 20110126081 | REQUEST-COMMAND ENCODING FOR REDUCED-DATA-RATE TESTING - Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via the CA link. A given CA packet includes an address field having address information corresponding to one or more storage locations in the memory device. Moreover, the memory device includes control logic having two operating modes, where, during a first operating mode, the control logic decodes address information in the CA packets using full-field sampling, and, during the second operating mode, the control logic decodes a portion of the address information in the CA packets using sub-field sampling. | 05-26-2011 |
| 20110119425 | DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM - The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module. | 05-19-2011 |
| 20110102043 | REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT - A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary. | 05-05-2011 |
| 20110096767 | Systems and Methods for Parallel Signal Cancellation - A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the interference canceller are configurable for processing multi-mode signals. | 04-28-2011 |
| 20110084737 | FREQUENCY RESPONSIVE BUS CODING - A data system permits bus encoding based on frequency of the bus and the frequency of switching on the bus so as to avoid undesirable frequency conditions such as a resonant condition or interference with other electrical devices. Transmission frequencies along one or more busses are monitored and used to control the encoding process, for example, an encoding process based on data bus inversion (DBI). The use of both a measure of an absolute number of logic levels (“DBI_DC”) and a measure of a number of logic level transitions relative to a prior signal (“DBI_AC”) provides a measure of control that may be used to compensate for both main and predriver switching noise. | 04-14-2011 |
| 20110080923 | Interference Suppression for CDMA Systems - Interference is cancelled from a baseband signal by synthesizing interference from estimated symbols in interfering subchannels. The estimated symbols are hard-coded, soft weighted, or zeroed, depending on the value of an estimated pre-processed signal-to-interference-and-noise ratio (SINR) in each subchannel in order to maximize a postprocessed SINR. The estimated pre-processed SINR is obtained from averages of estimated symbol energies and estimated noise variances, or from related statistical procedures. | 04-07-2011 |
| 20110069796 | Advanced Signal Processors for Interference Suppression in Baseband Receivers - A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the interference canceller are configurable for processing multi-mode signals. | 03-24-2011 |
| 20110069782 | Capacitive-coupled Crosstalk Cancellation - This disclosure presents a method of canceling inductance-dominated crosstalk using a capacitive coupling circuit; it also presents a method of calibrating, selecting and programming a capacitance value used for coupling, so as to add a derivative of each aggressor signal to each victim signal, and thereby negate crosstalk that would otherwise be seen by a given receiver. In the context of a multiple-line bus, cross-coupling circuits may be used between each pair of “nearest neighbors,” with values calibrated and used for each particular transmitter-receiver pair. Embodiments are also presented which address crosstalk induced between lines that are not nearest neighbors, such as, for example, for use in a differential signaling system. | 03-24-2011 |
| 20110069742 | Method and Apparatus for Interference Suppression with Efficient Matrix Inversion in a DS-CDMA System - A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal. | 03-24-2011 |
| 20110066792 | Segmentation Of Flash Memory For Partial Volatile Storage - This disclosure provides a method and system that segment flash memory to have differently managed regions. More particularly, flash memory is segmented into a “non-volatile” region, where program counts are restricted to preserve baseline retention assumptions, and a “volatile” region, where program counts are unrestricted. Contrary to conventional wisdom, wear leveling is not performed on all flash memory, as the volatile region is regarded as degraded, and as the non-volatile region has program counts restricted to promote long-term retention. More than two regions may also be created; each of these may be associated with intermediate program counts and volatility expectations, and wear leveling may be applied to each of these on an independent basis if desired. Refresh procedures may optionally be applied to the region of flash memory which is treated as volatile memory. | 03-17-2011 |
| 20110064172 | Systems and Methods for Serial Cancellation - A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal. | 03-17-2011 |
| 20110064066 | Methods for Estimation and Interference Cancellation for signal processing - A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal. | 03-17-2011 |
| 20110060868 | MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES - This disclosure has described embodiments of a nonvolatile memory that includes at least two concurrently accessible memory banks ( | 03-10-2011 |
| 20110051854 | ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION - Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols, and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition. | 03-03-2011 |
| 20110044378 | Iterative Interference Canceler for Wireless Multiple-Access Systems with Multiple Receive Antennas - This invention teaches to the details of an interference canceling receiver for canceling intra-cell and inter-cell interference in coded, multiple-access, spread spectrum transmissions that propagate through frequency selective communication channels to a multiplicity of receive antennas. The receiver is designed or adapted through the repeated use of symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimates. Receiver embodiments may be designed, adapted, and implemented explicitly in software or programmed hardware, or implicitly in standard RAKE-based hardware either within the RAKE (i.e., at the finger level) or outside the RAKE (i.e., at the user or subchannel symbol level). Embodiments may be employed in user equipment on the forward link or in a base station on the reverse link. It may be adapted to general signal processing applications where a signal is to be extracted from interference. | 02-24-2011 |
| 20110043220 | METHOD AND APPARATUS FOR POWER SEQUENCE TIMING TO MITIGATE SUPPLY RESONANCE IN POWER DISTRIBUTION NETWORK - The transient load current of a circuit powered by a power distribution network is increased in a plurality of steps, with the step transition times being adjusted based on the transient noise of the power distribution network. This reduces the resonance noise that would otherwise occur in the supply current of the power distribution network. | 02-24-2011 |
| 20110037772 | Scalable Unified Memory Architecture - A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller. | 02-17-2011 |
| 20110029801 | Method and System for Balancing Receive-Side Supply Load - Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensation current to reduce supply ripple. The compensation current is calculated based upon prior data samples rather than the current symbols, and consequently increases the maximum instantaneous current fluctuations between adjacent symbol sets as compared with circuits that do not include the compensation. The frequency response of the power-distribution network filters out the increased data dependence of the local supply current, however, and consequently reduces the fluctuations of total supply current. Some embodiments provide compensation currents for both transmitted and received symbols. | 02-03-2011 |
| 20110025533 | ENCODING DATA WITH MINIMUM HAMMING WEIGHT VARIATION - M-bit data are encoded into n-bit data such that the encoded n-bit data has a sufficient number of encoded data patterns enough to encode the number (2 | 02-03-2011 |
| 20110019760 | Methods and Systems for Reducing Supply and Termination Noise - A transmitter expresses continuous-time signals on alternate, parallel channels with reference to different supply voltages such that the signals on alternate channels have different common-mode voltages. At the transmitter, expressing the symbols using alternate supply voltages limits the maximum supply current used to express the signals and to transition between adjacent symbol sets. Limiting supply current ameliorates problems associated with simultaneous switching noise (SSN). At the receiver, the different common-mode voltages tend to balance the current to and from termination nodes, and consequently place reduced stress on a reference voltage. Providing different common-mode voltages on alternate channels may additionally reduce cross-talk between channels. | 01-27-2011 |
| 20110019656 | Advanced signal processors for Interference Cancellation in baseband receivers - An interference canceller comprises a composite interference vector (CIV) generator configured to produce a CIV by combining soft and/or hard estimates of interference, an interference-cancelling operator configured for generating a soft projection operator, and a soft-projection canceller configured for performing a soft projection of the received baseband signal to output an interference-cancelled signal. Weights used in the soft-projection operator are selected to maximize a post-processing SINR. | 01-27-2011 |
| 20110018599 | Partial Response Receiver And Related Method - A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. | 01-27-2011 |
| 20110016352 | PROGRAMMABLE MEMORY REPAIR SCHEME - The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elements and one or more redundant data storage elements, the primary data storage elements having respective addresses for memory access operations. The repair circuit is programmable by another semiconductor device separate from the memory device to recognize a malfunctioning address of the primary data storage elements and the programmed repair circuit is configured to reroute memory access from a primary data storage element having the recognized malfunctioning address to a corresponding redundant data storage element. | 01-20-2011 |
| 20110007377 | APPARATUS AND METHOD FOR REDUCING PIXEL OPERATIONAL VOLTAGE IN MEMS-BASED OPTICAL DISPLAYS - Embodiments of a display comprising pixels formed from suitably tethered deformable membrane-based MEMS subsystems are provided that include the means to dynamically alter the in-plane tension, and thus the effective spring constant, of the deformable membrane being ponderomotively propelled between active and inactive optical states, said dynamic alteration being effected by exploiting transverse piezoelectric properties of the deformable membranes. Manipulating the spring constant can reduce the actuation force required to turn pixels on, thus significantly reducing the operational voltages for the display composed of an array of such subsystems. Since display power rises with the square of the pixel drive voltage, such architectures give rise to more power efficient display systems. | 01-13-2011 |
| 20110004726 | PIECEWISE ERASURE OF FLASH MEMORY - Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multiple piecewise-erase commands within the memory device may be insufficient to erase the information stored in the storage cell. Moreover, the first circuit includes an interface that receives the multiple piecewise-erase commands from the control logic and that transmits the multiple piecewise-erase commands to the memory device. | 01-06-2011 |
| 20100329402 | Advanced Signal Processors for Interference Cancellation in Baseband Receivers - A multi-mode receiver includes a channel decomposition module (e.g., a Rake receiver) for separating a received signal into multipath components, an interference selector for selecting interfering paths and subchannels, a synthesizer for synthesizing interference signals from selected sub channel symbol estimates, and an interference canceller for cancelling selected interference in the received signal. At least one of the channel decomposition module, the synthesizer, and the interference canceller are configurable for processing multi-mode signals. | 12-30-2010 |
| 20100323624 | METHOD AND APPARATUS FOR SELECTIVELY APPLYING INTERFERENCE CANCELLATION IN SPREAD SPECTRUM SYSTEMS - The present invention is directed to the selective provision of interference canceled signal streams to demodulating fingers in a communication receiver. According to the present invention, potential interferer signal paths are identified. Signal streams having one or more potential interferer signals removed or canceled are created, and a correlation is performed to determine whether the strength of a desired signal path increased as a result. If the correlation indicates that the strength of a desired signal path was increased by the signal cancellation, the interference canceled signal stream is provided to the demodulation finger assigned to track the desired signal path. If the correlation determines that the strength of the desired signal path did not increase as a result of performing interference cancellation, the raw or a different interference canceled signal stream is provided to the demodulation finger. | 12-23-2010 |
| 20100318311 | Driver Calibration Methods and Circuits - Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals. | 12-16-2010 |
| 20100315142 | HIGH-SPEED SOURCE-SYNCHRONOUS SIGNALING - A system for communicating data between a first integrated circuit device and a second integrated circuit device. The first iterated circuit device transmits a timing signal to the second integrated circuit device, wherein the timing signal includes a first transition and a second transition. The first integrated circuit device then delays the data, so that the data is delayed relative to the timing signal by a first predetermined delay time. Next, the first integrated circuit device transmits the delayed data to the second integrated circuit device, which receives the tinting signal and the delayed data. Next, the second integrated circuit device delays the first transition of the timing signal by a second predetermined delay time to generate a delayed version of the first transition. The second integrated circuit device then senses the data during a time interval between the delayed version of the first transition and the second transition. | 12-16-2010 |
| 20100309964 | ASYMMETRIC COMMUNICATION ON SHARED LINKS - Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data. | 12-09-2010 |
| 20100309791 | EDGE-BASED LOSS-OF-SIGNAL DETECTION - Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data. | 12-09-2010 |
| 20100302229 | SIMPLE MATRIX ADDRESSING IN A DISPLAY - An addressing mechanism for charging and discharging quasi-capacitive elements in an X-Y matrix. The addressing mechanism may be configured to toggle a resistor-capacitor (RC) time constant between large and small values such as by opening or closing a circuit path to a low impedance resistor disposed in parallel with a higher impedance in-line resistor. When this occurs, elements in the X-Y matrix can be addressed and controlled. The X-Y matrix may be comprised of multiple “rows” and “columns” of conductors where crosstalk may occur along the columns and rows. Crosstalk may be curtailed by using either hysteresis management or global control of the row's impedance along its entire length. The resulting control obviates the need for active devices at each matrix element to perform the switching functions. | 12-02-2010 |
| 20100296566 | METHOD AND APPARATUS FOR DETERMINING A CALIBRATION SIGNAL - Embodiments of a system for determining and optimizing the performance a signaling system are described. During operation, the system captures or measures a single-bit response (SBR) for the signaling system. Next, the system constructs an idealized inter-symbol-interference-free (ISI-free) SBR for the signaling system which is substantially free of inter-symbol-interference (ISI). The system then calculates an ISI-residual from the captured SBR and the idealized ISI-free SBR. Next, the system constructs a calibration bit pattern for the signaling system that is based substantially on the ISI-residual. Finally, the system uses the calibration bit pattern to calibrate, optimize and determine an aspect of the performance of the signaling system. | 11-25-2010 |
| 20100290481 | ENCODING AND DECODING TECHNIQUES WITH IMPROVED TIMING MARGIN - Embodiments of an encoder and a decoder are described. The encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on two corresponding sets of output nodes, a first set and a second set. The encoder selects a current codeword such that it differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. A decoder receives and decodes the codewords by comparing symbols on node pairs for which the symbols expressed in the prior code word were alike and decoding the results of those comparisons. | 11-18-2010 |
| 20100289544 | Receiver With Enhanced Clock And Data Recovery - A receiver device implements enhanced data reception with edge-based clock and data recovery such as with a flash analog-to-digital converter architecture. In an example embodiment, the device implements a first phase adjustment control loop, with for example, a bang-bang phase detector, that detects data transitions for adjusting sampling at an optimal edge time with an edge sampler by adjusting a phase of an edge clock of the sampler. This loop may further adjust sampling in received data intervals for optimal data reception by adjusting the phase of a data clock of a data sampler such a flash ADC. The device may also implement a second phase adjustment control loop with, for example, a baud-rate phase detector, that detects data intervals for further adjusting sampling at an optimal data time with the data sampler. | 11-18-2010 |
| 20100265109 | ENCODING AND DECODING TECHNIQUES FOR BANDWIDTH-EFFICIENT COMMUNICATION - An encoder encodes data into parallel codewords. Each codeword is expressed as a set of logic 0s and a set of logic 1s on two sets of output nodes. The encoder selects a current codeword which differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. The current codeword is selected such that the first and second sets of nodes are different than additional nodes that contain transitions between the immediately preceding codeword and a bi-preceding codeword, and that logic values on additional nodes are unchanged between immediately preceding codeword and current codeword. A decoder decodes the codewords by comparing symbols on node pairs other than those for which transitions were expressed in the preceding code word, and decoding the results of those comparisons. | 10-21-2010 |
| 20100262790 | Memory Controllers, Methods, and Systems Supporting Multiple Memory Modes - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices. | 10-14-2010 |
| 20100259449 | TECHNIQUE FOR DETERMINING AN ANGLE OF ARRIVAL IN A COMMUNICATION SYSTEM - Embodiments of a circuit are described. In this circuit, a transmit circuit provides signals to antenna elements during an acquisition mode, where a given signal to a given antenna element includes at least two frequency components having associated phases, and where the phase of a given frequency component in the given signal is different from phases of the given frequency component for the other antenna elements. Moreover, an output node couples the transmit circuit to the antenna elements that transmit the signals. Note that these signals establish an angle of a communication path between the circuit and another circuit. | 10-14-2010 |
| 20100259295 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 10-14-2010 |
| 20100251040 | METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM - A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously. | 09-30-2010 |
| 20100240327 | ANTENNA ARRAY WITH FLEXIBLE INTERCONNECT FOR A MOBILE WIRELESS DEVICE - An antenna array can be mounted on a flexible substrate and connected by a flexible interconnect to an integrated circuit such as a radio frequency front end. The antenna array can be mounted in a device housing that includes radio frequency interference (RFI) shielding. The antenna array is aligned with and next to an area of the housing that is not shielded against RFI. | 09-23-2010 |
| 20100237903 | Configurable On-Die Termination - Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted. | 09-23-2010 |
| 20100235673 | SIMPLIFIED RECEIVER FOR USE IN MULTI-WIRE COMMUNICATION - An encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on output nodes. The encoder selects a current codeword from a group of codewords in a codespace which does not overlap the other group of codewords, i.e., codewords in a given group of codewords are not included in any other group of codewords in the codespace. This property allows a receiver of the codewords to be simplified. In particular, a mathematical operation performed on symbols in the current codeword uniquely specifies the corresponding group of codewords. This allows a decoder to decode the current codeword using comparisons of symbols received on a subset of all possible combinations of node pairs. | 09-16-2010 |
| 20100235554 | RECONFIGURABLE POINT-TO-POINT MEMORY INTERFACE - Embodiments of an apparatus are described. An interface circuit in this apparatus receives or transmits digital signals on a bus and is configured to alternatively operate as either a data-bus interface circuit or a control-bus interface circuit in dependence upon a mode setting stored in a register. For example, the interface circuit may be pre-configured to interpret a line of an external bus as either a data line or a control line in accordance with the stored mode setting. Moreover, the stored mode setting may be dynamically configured (e.g., reprogrammed) during operation of the interface circuit so that subsequent digital signals are subsequently handled in accordance with a new mode setting. | 09-16-2010 |
| 20100228514 | DELAY LOCK LOOP DELAY ADJUSTING METHOD AND APPARATUS - Systems and methods for synchronizing communication between devices include using a test circuit to measure a propagation time through a delay circuit. The propagation time is used to determine an initial delay value within a delay lock loop. This delay value is then changed until a preferred delay value, resulting in synchronization, is found. In various embodiments, used of the initial delay value increases the speed, reliability or other beneficial features of the synchronization. | 09-09-2010 |
| 20100223426 | Variable-width memory - Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance. | 09-02-2010 |
| 20100220828 | EDGE-BASED SAMPLER OFFSET CORRECTION - Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler ( | 09-02-2010 |
| 20100215118 | TECHNIQUES FOR MULTI-WIRE ENCODING WITH AN EMBEDDED CLOCK - Techniques for multi-wire encoding with an embedded clock are disclosed. In one particular exemplary embodiment, the techniques may be realized as a transmitter component. The transmitter component may comprise at least one encoder module to generate a set of symbols, each symbol being represented by a combination of signal levels on a set of wires. The transmitter component may also comprise at least one signaling module to transmit one or more of the symbols over the set of wires according to a transmit clock. The transmitter component may additionally comprise control logic to restrict transmission of first and second subsets of the set of symbols to respective first and second portions of a clock cycle of the transmit clock, such that a signal differential among at least two of the set of wires exhibits a switching behavior that has a same frequency as the transmit clock. | 08-26-2010 |
| 20100215091 | Adaptive Equalization Using Correlation of Edge Samples With Data Patterns - An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal. | 08-26-2010 |
| 20100214822 | VOLTAGE-STEPPED LOW-POWER MEMORY DEVICE - This disclosure has described a system for charging a capacitive energy storage device of at least one memory cell within an integrated circuit device from an initial voltage to a final voltage, wherein the integrated circuit device includes a plurality of memory cells which are formed at least in part by capacitive energy storage devices. During operation, the system charges the capacitive energy storage device from the initial voltage to the final voltage stepwise through one or more progressively higher intermediate voltage levels using one or more voltage sources. Specifically, each intermediate voltage level is between the initial voltage and the final voltage, and each voltage source generates a respective intermediate voltage level. Note that charging the capacitive energy storage device through one or more intermediate voltage levels reduces energy dissipation during the charging process. | 08-26-2010 |
| 20100211748 | Memory System With Point-to-Point Request Interconnect - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices. | 08-19-2010 |
| 20100208774 | Iterative Interference Cancellation Using Mixed Feedback Weights and Stabilizing Step Sizes - A receiver is configured for canceling intra-cell and inter-cell interference in coded, multiple-access, spread-spectrum transmissions that propagate through frequency-selective communication channels. The receiver employs iterative symbol-estimate weighting, subtractive cancellation with a stabilizing step-size, and mixed-decision symbol estimates. Receiver embodiments may be implemented explicitly in software or programmed hardware, or implicitly in standard Rake-based hardware either within the Rake (i.e., at the finger level) or outside the Rake (i.e., at the user or sub channel symbol level). | 08-19-2010 |
| 20100207189 | NON-VOLATILE MEMORY DEVICE WITH REDUCED WRITE-ERASE CYCLE TIME - A transistor includes a substrate having a surface, where a first region and a second region of the substrate are doped with a first type of dopant, and where a third region of the substrate between the first region and the second region is doped with a second type of dopant. An insulator layer is deposited above a portion of the surface, which includes the third region, and a gate layer is deposited above the insulator layer. An encapsulation layer encloses ends of the gate layer, thereby defining gaps between ends of the insulator layer and the encapsulation layer. These gaps have a depth relative to the ends of the gate layer, with one end of the insulator layer proximate to a boundary between the first region and the third region and another end of the insulator layer proximate to a boundary between the second region and the third region. | 08-19-2010 |
| 20100205343 | Generating interface adjustment signals in a device-to-device interconnection system - Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits. | 08-12-2010 |
| 20100202565 | COMMUNICATION USING CONTINUOUS-PHASE MODULATED SIGNALS - Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first modulated electrical signal and the second modulated electrical signal based on a phase value of the first phase-adjustment element. Additionally, an output interface, which is coupled to the first phase-adjustment element, is coupled to one or more antenna elements which output signals. These signals include a quadrature phase-shift-keying (QPSK) signal corresponding to the first modulated electrical signal and the second modulated electrical signal. | 08-12-2010 |
| 20100202227 | REFERENCE VOLTAGE AND IMPEDANCE CALIBRATION IN A MULTI-MODE INTERFACE - A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the output node and the receive circuit is configured to receive second data from the memory device through the input node. The memory controller includes a calibration circuit and control logic coupled to the calibration circuit, where the calibration circuit and the control logic are configured to select a first reference voltage and a driver impedance for the transmit circuit and are configured to select a second reference voltage and a termination impedance for the receive circuit. The first reference voltage, the second reference voltage, the driver impedance and the termination impedance are selected from a set of pre-determined values, which are associated with different signaling modes for communication of the first data and the second data. | 08-12-2010 |
| 20100199237 | TRANSFORMING VARIABLE DOMAINS FOR LINEAR CIRCUIT ANALYSIS - Embodiments in the present disclosure pertain to domain translators. A domain translator converts a variable from one domain to a different domain. Domains include, but are not limited to, voltage, current, frequency, phase, delay, and duty-cycle. In particular, domain translators enable conversion between standard voltage and current domains commonly used by circuit simulators to other domains such as frequency, phase, delay, duty-cycle, etc., so that linear analysis can be performed on a wide range of circuits that exhibit linear behavior in domains other than voltage and current. | 08-05-2010 |
| 20100188910 | CLOCK SYNCHRONIZATION IN A MEMORY SYSTEM - A system and method for synchronizing a strobed memory system | 07-29-2010 |
| 20100185810 | IN-DRAM CYCLE-BASED LEVELIZATION - Systems and methods are provided for in-DRAM cycle-based levelization. In a multi-rank, multi-lane memory system, an in-DRAM cycle-based levelization mechanism couples to a memory device in a rank and individually controls additive write latency and/or additive read latency for the memory device. The in-DRAM levelization mechanism ensures that a distribution of relative total write or read latencies across the lanes in the rank is substantially similar to that in another rank. | 07-22-2010 |
| 20100183090 | MULTI-ANTENNA TRANSMITTER FOR MULTI-TONE SIGNALING - Embodiments of a communication circuit are described. This communication circuit includes an input node ( | 07-22-2010 |
| 20100180143 | TECHNIQUES FOR IMPROVED TIMING CONTROL OF MEMORY DEVICES - Techniques for improved timing control of memory devices are disclosed. In one embodiment, the techniques may be realized as a memory controller to communicate with a memory device via a communications link. The memory controller may comprise a memory interface to exchange data with the memory device via a set of N conductors according to at least one clock, the data being encoded such that each M bits of data are represented by at least one symbol and each symbol is associated with a combination of signal levels on a group of n conductors, wherein M| 07-15-2010 | |
| 20100150290 | Clock-Data Recovery ("CDR") Circuit, Apparatus And Method For Variable Frequency Data - A circuit, such as a CDR circuit, includes a sampler to receive a data signal having a variable data bit-rate responsive to a clock signal in an embodiment of the present invention. A clock circuit is coupled to the sampler and generates the clock signal responsive to a selectable update rate and a selectable phase adjust step-size. In a second embodiment of the present invention, the clock circuit includes a Stall logic that is coupled to first, second and third stages and is capable to hold the phase adjust signal responsive to the first and second stage output signals. In a third embodiment of the present invention, an indicator detects the variable data bit-rate and a counter provides the selectable phase adjust step-size for the adjust signal. In a fourth embodiment of the present invention, the clock circuit includes the Stall logic, the indicator and the counter. In a fifth embodiment of the present invention, the clock circuit includes an Averaging circuit to output a phase adjust signal responsive to the averaging of a first and second adjust signals for a predetermined period of time. | 06-17-2010 |
| 20100149039 | MULTI-ANTENNA BEAM-FORMING SYSTEM FOR TRANSMITTING CONSTANT ENVELOPE SIGNALS DECOMPOSED FROM A VARIABLE ENVELOPE SIGNAL - Embodiments in the present disclosure pertain to a multi-antenna beam-forming system for transmitting constant envelope signals decomposed from a variable envelope signal. The variable envelope signal is decomposed into two constant envelope signals. Each of the constant envelope signals are separately amplified by power amplifiers and transmitted over separate antennas. Beam steering delays can be added to the transmit paths of the constant envelope signals to direct the beam to the location of a receiver. The transmitted constant envelope signals combine through spatial out-phasing such that a receiving antenna receives a variable envelope signal. | 06-17-2010 |
| 20100146321 | SINGLE-CLOCK, STROBELESS SIGNALING SYSTEM - A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset relative to a clock signal supplied by the clock generator, the phase offset being determined at least in part by a signal propagation time on the signal path. | 06-10-2010 |
| 20100146199 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 06-10-2010 |
| 20100142607 | Methods and Systems for Transmitting Data by Modulating Transmitter Filter Coefficients - A signaling system supports main and auxiliary communication channels between integrated circuits in the same direction over a single link. An equalizing transmitter applies appropriate filter coefficients to minimize the impact of intersymbol interference when transmitting the main data over a communication channel. The transmitter modulates at least one of the filter coefficients with the auxiliary data to induce apparent ISI in the transmitted signal. A main receiver ignores the apparent ISI to recover the main data, while an auxiliary receiver detects and demodulates the apparent ISI to recover the auxiliary data. The auxiliary data may be encoded using spread-spectrum techniques to reduce the impact of the auxiliary data on the main data. | 06-10-2010 |
| 20100135378 | Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing - A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery. | 06-03-2010 |
| 20100135370 | BI-DIRECTIONAL INTERFACE CIRCUIT HAVING A SWITCHABLE CURRENT-SOURCE BIAS - A bi-directional interface circuit includes a transmitter portion, a receiver portion, a current source bias circuit, and a switch. When the interface circuit is transmitting data, the switch steers the bias current generated by the current source bias circuit to the transmitter portion of the interface. When the interface is receiving data, the switch steers the bias current to the receiver portion of the interface. Thus, the current-source bias circuit is kept on regardless of whether the interface is transmitting or receiving data. Because the current-source bias circuit is not turned on and off, the switching noise generated when the interface transitions between transmitting and receiving operations is eliminated or reduced. Consequently, any dead time inserted for such a transition can be minimized, and the effective bandwidth of the interface is increased. | 06-03-2010 |
| 20100135100 | Adjusting Clock Error Across A Circuit Interface - A system is provided with clock skew measurement and correction technology. A first circuit or memory controller | 06-03-2010 |
| 20100131725 | Memory System And Device With Serialized Data Transfer - A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial streams of bits. Each of the memory devices receives at least one of the serial streams of bits from the memory controller and converts the serial stream of bits to a set of parallel bits for storage. | 05-27-2010 |
| 20100128542 | Reference Clock and Command Word Alignment - A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment. | 05-27-2010 |
| 20100115191 | System Including Hierarchical Memory Modules Having Different Types Of Integrated Circuit Memory Devices - A memory system is disclosed comprising a memory controller and a first set of volatile memory devices defining a first memory hierarchy. The first set of volatile memory devices are disposed on at least one first memory module, which is coupled to the memory controller in a daisy-chained configuration. A first integrated circuit buffer device is included on the module. The system has a second set of nonvolatile memory devices defining a second memory hierarchy. The second set of nonvolatile memory devices are disposed on at least one second memory module, which is coupled to the at least one first memory module in a daisy-chained configuration. The second module includes a second integrated circuit buffer device. The system is configured such that signals transmitted between the memory controller and the second memory hierarchy pass through the first memory hierarchy. | 05-06-2010 |
| 20100103999 | PARTIAL RESPONSE DECISION-FEEDBACK EQUALIZATION WITH ADAPTATION BASED ON EDGE SAMPLES | 04-29-2010 |
| 20100103713 | ADJUSTABLE WIDTH STROBE INTERFACE - A memory system comprises a circuit board | 04-29-2010 |
| 20100100661 | PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES - An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols. | 04-22-2010 |
| 20100097071 | Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement - An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance. | 04-22-2010 |
| 20100090732 | CLOCK AND DATA RECOVERY EMPLOYING PIECE-WISE ESTIMATION ON THE DERIVATIVE OF THE FREQUENCY - A system and method for performing clock data recovery. The system sets the phase of a recovered clock signal | 04-15-2010 |
| 20100085123 | INJECTION-LOCKED CLOCK MULTIPLIER - Embodiments of a clock circuit are described. This clock circuit includes an oscillator, which includes a resonance circuit having a resonance frequency, that outputs a first clock signal having a first frequency. Furthermore, a digital controller is coupled to the oscillator. This digital controller modifies the resonance frequency of the oscillator during a first mode of operation of the clock circuit, and the modifying is ceased during a second mode of operation of the clock circuit. In addition, on injection circuit is coupled to the oscillator. This injection circuit provides a second clock signal having a second frequency to the oscillator. Note that the second clock signal injection locks a phase and/or the first frequency of the first clock signal. Also note that a ratio of the first frequency to the second frequency is greater than or equal to one. | 04-08-2010 |
| 20100085100 | Low-Power Clock Generation and Distribution Circuitry - A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal. | 04-08-2010 |
| 20100077267 | Memory System with Point-to-Point Request Interconnect - A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices. | 03-25-2010 |
| 20100077136 | Memory System Supporting Nonvolatile Physical Memory - A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory. | 03-25-2010 |
| 20100074314 | Margin Test Methods And Circuits - Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing. | 03-25-2010 |
| 20100073047 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System - An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device. | 03-25-2010 |
| 20100073023 | SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION - Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver. | 03-25-2010 |
| 20100067314 | Memory Systems And Methods For Dynamically Phase Adjusting A Write Strobe And Data To Account For Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write strobe to compensate for timing drift at the memory device. The memory controller uses the read strobe as a measure of the drift. | 03-18-2010 |
| 20100066450 | High-Speed Low-Power Differential Receiver - A low-voltage differential communication system includes a low- and programmable-swing voltage-mode transmitter that delivers a low-voltage differential signal to a receiver via differential channel. The receiver employs two input transistors, each in a common-gate configuration, to recover the low-voltage differential signal. A current source in the receiver biases the input transistors such that their source voltages are nominally biased at the common-mode voltage of the differential signal, and their gate-source voltages remain essentially constant with common-mode-voltage fluctuations. | 03-18-2010 |
| 20100058100 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 03-04-2010 |
| 20100054323 | Adaptive Receive-Side Equalization - An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data eyes of the highest amplitude. A data filter may be included to enable the amplitude detector only in response to particular incoming data patterns. | 03-04-2010 |
| 20100050010 | Data-Width Translation Between Variable-Width and Fixed-Width Data Ports - Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency. | 02-25-2010 |
| 20100046600 | Methods and Circuits for Asymmetric Distribution of Channel Equalization Between Devices - A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC. | 02-25-2010 |
| 20100046597 | Adaptive Receive-Side Equalization - An adaptive receiver equalizes incoming data expressed as a series of symbols, the degree of equalization being adjusted by some adaptive control logic. An amplitude detector samples the amplitude of the eye openings of incoming symbols and conveys the resulting measures of eye amplitude to the adaptive control logic. The control logic experiments with different equalization settings while monitoring the resulting eye amplitude to find the equalization setting that provides incoming data eyes of the highest amplitude. A data filter may be included to enable the amplitude detector only in response to particular incoming data patterns. | 02-25-2010 |
| 20100040169 | CODING METHODS AND SYSTEMS FOR IMPROVED ERROR MARGINS - Each symbol in a sequence of codewords is expressed as a voltage level representative of a one or zero, and each codeword includes both levels. Sense amplifiers at the receiver compare all pairs of symbols in each codeword. Comparisons based upon like symbol values provide mid-range sensed voltages, and comparisons based upon disparate symbols values provide relatively higher or lower sensed voltages. Sampling the high and low voltages produces determinate sample values, whereas sampling the midrange voltage produces indeterminate sample values. Sampling the sensed voltages thus produces a mix of indeterminate and determinate values for each codeword. Codewords are selected such that the number and placement of the determinate sample values identify each codeword, and subsequent codewords are selected so the nodes supporting the high and low sensed voltages sampled to obtain the determinate sample values transitioned to their current voltage from either the intermediate voltage or did not transition. | 02-18-2010 |
| 20100030955 | MASK KEY SELECTION BASED ON DEFINED SELECTION CRITERIA - An improved data system permits power efficient mask key write operations. A mask key selector implements criteria-based selection of mask keys for mask key write operations on blocks data. In one embodiment, a first set of mask keys is compared to data bytes of a data block that will be written to memory. The comparison culls keys from the list of candidates that match unmasked data bytes, that is, values that will be written to memory as “changed” data. A mask key is selected from the resulting set of candidates so a memory write operation consumes less power (relative to selection of other keys), or so that the operation minimizes switching noise. The selected mask key is then substituted by a controller into masked data values, and a modified data block is transmitted to memory, with the memory detecting masked data by identifying mask keys in the modified data block. | 02-04-2010 |
| 20100027712 | EQUALIZING TRANSMITTER AND METHOD OF OPERATION - A transmitter for providing channel equalization that includes a first driver and second driver having a high pass filter. The first driver generates a first output signal representing a digital input signal. The second driver generates a second output signal representing a high pass filtered version of the digital input signal. The first and second output signals are summed to provide a third output signal that is channel equalized for transmission over a channel. | 02-04-2010 |
| 20100020861 | DFE Margin Test Methods and Circuits that Decouple Sample and Feedback Timing - Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter. | 01-28-2010 |
| 20100008414 | High-Speed Signaling Systems And Methods With Adaptable, Continuous-Time Equalization - A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI. | 01-14-2010 |
| 20090327565 | BIMODAL MEMORY CONTROLLER - A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller. | 12-31-2009 |
| 20090322370 | Method And Apparatus For Test And Characterization Of Semiconductor Components - A method and apparatus for testing and characterizing circuits is provided. In one embodiment, a high-speed interface of a semiconductor component includes high-speed test circuitry. The high-speed test circuitry obviates the need for an external high-speed testing system for testing and characterization. In one embodiment, the high-speed test circuitry includes a test pattern generation circuit, and various differential comparators to compare low bandwidth reference signals with interface signals during testing and characterization. In one embodiment, an interface that includes the test circuitry can test itself or another interface. In one embodiment, a timing reference signal decouples the individual parameters of two interfaces testing each other to avoid any errors introduced by the combination of individual interface circuit parameters, such as receiver parameters and transmitter parameters. The testing can be performed at the wafer stage, at the component stage, and in a system. | 12-31-2009 |
| 20090319719 | System Having A Controller Device, A Buffer Device And A Plurality Of Memory Devices - A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device. | 12-24-2009 |
| 20090300260 | SELECTIVE SWITCHING OF A MEMORY BUS - In a system, a memory bus has a first bus segment coupled to a memory controller that includes control logic and a first memory device, a second bus segment coupled to a second memory device, and a switch to selectively couple and decouple the first bus segment and the second bus segment in response to control information from the control logic. Note that the control logic may output control information to the switch to selectively decouple the first bus segment and the second bus segment to effect a change in an electrical length of the memory bus to enable data transfer with respect to the first memory device at a first data rate. Additionally, the control logic may output control information to the switch to selectively couple the first bus segment and the second bus segment to effect another change in the electrical length of the memory bus to enable data transfer with respect to the second memory device at a second data rate that is slower than the first data rate. | 12-03-2009 |
| 20090278565 | Calibration Methods and Circuits to Calibrate Drive Current and Termination Impedance - Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching. | 11-12-2009 |
| 20090257542 | Dual loop clock recovery circuit - A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator. | 10-15-2009 |
| 20090252213 | Selectable-Tap Equalizer - A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval. | 10-08-2009 |
| 20090243681 | Embedded Source-Synchronous Clock Signals - A synchronous communication system includes two transmitters that transmit respective first and second data signals that are phase offset from one another by about 90 degrees. On the receive side, a pair of extraction circuits extract a first clock signal from the first data signal and a second clock signal from the second data signal. The clock signals are offset from one another by about 90 degrees due to the phase offset of the corresponding data signals. Edges of the first clock signal are thus centered within the symbols of the second data signal, and edges of the second clock signal are centered within the symbols of the first data signal. A pair of receivers employs the first clock signal to sample the second data symbol and the second clock signal to sample the first data signal. | 10-01-2009 |
| 20090240448 | TECHNIQUE FOR DETERMINING PERFORMANCE CHARACTERISTICS OF ELECTRONIC DEVICES AND SYSTEMS - A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line. | 09-24-2009 |
| 20090235113 | MEMORY ERROR DETECTION - Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation | 09-17-2009 |
| 20090219067 | Locked Loop Circuit With Clock Hold Function - A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal. | 09-03-2009 |
| 20090198924 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 08-06-2009 |
| 20090195541 | RENDERING DYNAMIC OBJECTS USING GEOMETRY LEVEL-OF-DETAIL IN A GRAPHICS PROCESSING UNIT - The present embodiments provide a system for graphically rendering an object. This system operates first by pre-processing a geometry mesh for the object offline, wherein the geometry mesh is partitioned into a set of patches, and wherein each patch is bounded by a bounding box. The system then builds a multi-resolution representation for each of the set of patches. Next, during real time rendering, the system deforms the bounding boxes associated with the set of patches through superposition of object motions in each frame weighted by a set of predetermined mesh-skinning parameters. For each deformed bounding box, the system computes a geometry level-of-detail (LOD) value based on a projected area of the deformed bounding box in screen space. The system next deforms the object through a set of mesh skinning operations. The system then renders the deformed object based on the computed geometry LOD values for the set of patches and the multi-resolution representation for the geometry mesh. | 08-06-2009 |
| 20090186584 | TECHNIQUE FOR LOW-POWER OPERATION OF A WIRELESS DEVICE - Embodiments of a circuit are described. In this circuit, a receiver includes at least one input node that receives one or more signals from one or more antenna elements. Note that a given signal from a given antenna element may have an associated fixed bandwidth and/or may include directional information corresponding to a region in a space. Moreover, the receiver includes a measurement circuit, coupled to at least the one input node, that determines whether a metric of the given signal exceeds a corresponding threshold. Additionally, control logic in the circuit, which is coupled to the measurement circuit, instructs a communication circuit in the circuit to exit a first power-consumption mode if the metric of at least one of the signals exceeds the corresponding threshold. | 07-23-2009 |
| 20090164677 | TIMING ADJUSTMENT IN A RECONFIGURABLE SYSTEM - This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing parameters such as access latency and maximum clock speed typically reflect a worst-case configuration scenario. By in-situ detecting actual configuration (e.g., whether expansion boards have been inserted), and correspondingly configuring the system to operate in a mode geared to the specific configuration, worst-case or near worst-case scenarios may be ruled out and system timing parameters may be redefined for faster-than-conventionally-rated performance; this is especially the case in a DPP system where signal pathways typically become more direct as additional modules are added. Contrary to convention wisdom therefore, which might dictate that component expansion should slow down timing, clock speed can actually be increased in such a system, if supported by the configuration, for better performance. | 06-25-2009 |
| 20090161453 | METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM - A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship. | 06-25-2009 |
| 20090132741 | COMMUNICATION CHANNEL CALIBRATION USING FEEDBACK - A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component. | 05-21-2009 |
| 20090129505 | PARTIAL-RATE TRANSFER MODE FOR FIXED-CLOCK-RATE INTERFACE - Systems and methods are provided for a partial-rate transfer mode using fixed-clock-rate interfaces. In the partial-rate mode, each data bit is transmitted consecutively two or more times. The receiver uses a global clock without phase adjustment to detect the replicated incoming bits. As a result, the receiver system can receive data at a partial data rate when the system is locking into the phase of data received from the transmitter. | 05-21-2009 |
| 20090126027 | FILE ACCESSING AND RETRIEVAL USING SOFT DIGITAL RIGHTS MANAGEMENT TECHNOLOGY - The subject matter disclosed herein relates to a method and/or system for enabling access to computer file content using an open routine having a proprietary argument. | 05-14-2009 |
| 20090110115 | METHOD AND APPARATUS FOR DATA RECOVERY - A method for recovering data includes oversampling an input data signal to provide sample sets, and storing a plurality of sample sets in addressable memory. The sample sets are processed, using sequential logic to make determinations of respective samples suitable for use in data recovery from corresponding sample sets. One function applied for the determination, includes taking a first mean transition position in a first group of sample sets, taking a second mean transition position in a second group of sample sets, computing a slope value for change in transition position, and making the determination based on the order of the plurality of samples, the first and second means, and the slope. The determined samples are obtained and data recovery is achieved. Sample sets can be modified according to equalization functions. Other modifications include encoding the sample sets for data compression. | 04-30-2009 |
| 20090103572 | Crosstalk Minimization in Serial Link Systems - Described are methods and circuits for reducing the error-inducing effects of crosstalk. Communication circuits in accordance with some embodiments adjust the phase of transmitted “aggressor” data to misalign transmitted signals from the perspective of “victim” channels. This misalignment moves the noise artifacts cross coupled to the victim channel away from sensitive sample times in the victim data, and consequently reduces the net effects of aggressor crosstalk on neighboring victim channels. Some embodiments reduce the effects of crosstalk by introducing static timing offsets to one or a plurality of aggressor transmitters, one or a plurality of victim transmitters, or some combination of aggressor and victim transmitters. Other embodiments dynamically alter the relative timing of aggressor and victim transmitters. | 04-23-2009 |
| 20090089557 | UTILIZING MASKED DATA BITS DURING ACCESSES TO A MEMORY - Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted. | 04-02-2009 |
| 20090067484 | Selectable-Tap Equalizer - A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval. | 03-12-2009 |
| 20090067482 | Selectable-Tap Equalizer - A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval. | 03-12-2009 |
| 20090066376 | Equalizing Transceiver With Reduced Parasitic Capacitance - A signaling circuit having reduced parasitic capacitance. The signaling circuit includes a plurality of driver circuits each having an output coupled to a first output node, and a plurality of select circuits each having an output coupled to a control input of a corresponding one of the driver circuits. Each of the select circuits includes a control input to receive a respective select signal and a plurality of data inputs to receive a plurality of data signals. Each of the select circuits is adapted to select, according to the respective select signal, one of the plurality of data signals to be output to the control input of the corresponding one of the driver circuits. | 03-12-2009 |
| 20090060017 | Selectable-Tap Equalizer - A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval. | 03-05-2009 |
| 20090059642 | Memory Controller With Multi-Modal Reference Pad - A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller. | 03-05-2009 |
| 20090049324 | Methods and systems for operating memory in two modes - A memory system permits synchronized transmission of data with multiple memory modules in a dynamically expandable bus system such as with a point-to-point memory bus using strobed data transmission. Memory modules of the system are selectively configured to switch transmission modes to either transmit data to a memory controller or a timing reference signal to another memory module from a common terminal coupled to a common path of the bus which may depend on the number of memory modules configured in the system. The system permits all memory modules to operate with a strobed based memory controller even when some memory modules of the system do not share a strobe signal path with the memory controller of the system. | 02-19-2009 |
| 20090037626 | Multi-drop bus system - A multi-drop bus system and a method for operating such a system. The system includes a multi-drop bus having at least one bus line, each bus line being made up of a multiple of line segments. Each of the line segments terminates at a drop point and each drop point is coupled to a load impedance. The characteristic impedance of a line segment is matched to the equivalent impedance presented by the load impedance in combination with the characteristic impedance of a following segment, or is matched to the load impedance if there is no following segment. | 02-05-2009 |
| 20090034669 | PERIODIC CALIBRATION FOR COMMUNICATION CHANNELS BY DRIFT TRACKING - A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2 | 02-05-2009 |
| 20090034344 | Methods and apparatus for strobe signaling and edge detection thereof - A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations. | 02-05-2009 |
| 20090031091 | CONTINUOUS TIMING CALIBRATED MEMORY INTERFACE - A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting the timing of write operations at the memory controller based on the observed timing drift for the read data. | 01-29-2009 |
| 20090015340 | Phase Controlled Oscillator Circuit with Input Signal Coupler - An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal. | 01-15-2009 |
| 20080279032 | Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control - An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal. | 11-13-2008 |
