| QUALITAU, INC. Patent applications |
| Patent application number | Title | Published |
| 20100201389 | INTEGRATED UNIT FOR ELECTRICAL/RELIABILITY TESTING WITH IMPROVED THERMAL CONTROL - In accordance with an aspect, a thermally-controllable integrated unit is configured to hold devices under test. The integrated unit includes at least one heater board, comprised of a thermally-conductive material and provided with at least one global heater configured to globally heat the DUT board. A DUT board of the integrated unit includes a DUT board in thermal contact with the at least one heater board, the DUT board including a plurality of sockets, each socket configured to hold at least one DUT. The DUT has conductor paths to conduct electrical signals between test equipment and the terminals of DUTs in the sockets. Each socket includes an associated temperature sensor and a separately controllable local heater configured to, based on a temperature indication from the temperature sensor, heat a DUT in that socket. | 08-12-2010 |
| 20100052633 | MODIFIED CURRENT SOURCE (MCS) WITH SEAMLESS RANGE SWITCHING - A current source is provided with two resistor banks, and digital potentiometers are used to control how much each resistor bank affects the resulting output current. Furthermore, when the digital potentiometers are at a particular setting such that a particular resistor bank does not affect the resulting output current (i.e., the resistor bank is “inactive”), the resistance of that resistor bank can be switched without affecting the output current, thus minimizing or eliminating discontinuities in the output current during a current sweep operation. Thus, for example, when a resistor bank meets its threshold and becomes inactive, the resistance of the inactive resistor bank may be switched, and then the digital potentiometer setting may be changed to facilitate smoothly reactivating that resistor bank, with the new resistance. | 03-04-2010 |
| 20090206869 | ELECTROMIGRATION TESTER FOR HIGH CAPACITY AND HIGH CURRENT - An electronic device under test (DUT) may be incorporated into a circuit having a voltage limiter connected in parallel with the DUT. The circuit includes a controlled current source having an output current connected in series with the DUT. The voltage limiter is characterized in that, when the output current is such that the voltage across the DUT (Vdut) would exceed a particular maximum voltage Vmax, without the voltage limiter in place, at least a portion of the output current flows through the voltage limiter, so as to limit Vdut to be less than or equal to Vmax. When the output current is such that Vdut would be less than or equal to Vmax, current does not flow through the voltage limiter. The circuit may include a plurality of DUTs, each DUT connected in series with the output current of a controlled current source, with a voltage limiter connected in parallel with each DUT. | 08-20-2009 |
| 20080315900 | HIGH TEMPERATURE CERAMIC SOCKET CONFIGURED TO TEST PACKAGED SEMICONDUCTOR DEVICES - A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic. | 12-25-2008 |
| 20080315862 | SMART PARALLEL CONTROLLER FOR SEMICONDUCTOR EXPERIMENTS - An instrument is configured to coordinate execution of a plurality of experiments employing a plurality of source measurement units (SMU's) to characterize a plurality of devices under test (DUT's). Each experiment controller, of a plurality of experiment controllers, is configured to manage one of the plurality of experiments by, at least in part, controlling the SMU's allocated to that experiment. A main controller is configured to interoperate with a host to manage the experiment controllers. For example, the instrument may be configured to provide experiment parameters to the SMU's prior to execution of the experiments. In one aspect, the main controller is configured to receive experiment parameters from a host controller external to the instrument. At least in part based on the received experiment parameters, the main controller configure which experiment controllers are to manage which experiment. The main controller is also configured to cause each experiment controller to provide appropriate ones of the received experiment parameters to the SMU's allocated to the experiment which that experiment controller is configured to manage. | 12-25-2008 |
| 20080238451 | AUTOMATIC MULTIPLEXING SYSTEM FOR AUTOMATED WAFER TESTING - A parametric test system is for testing devices in dice in a semiconductor wafer, each die having a plurality of pads for electrically connecting to the device in the die. A tester of the system has a plurality of input/output lines for providing and receiving electrical signals during a device test. Multiplexer circuitry of the test system includes a plurality of networks of automated switches. The multiplexer circuitry is configured to receive electrical signals on the input lines from the tester and to provide the electrical signals to a wafer prober, wherein the multiplexer circuitry is configured to restrict how the electrical signals can be provided to the networks of automated switches. As a result of the multiplexer being configured to restrict how the electrical signals can be provided to the networks of automated switches, the configuration of the networks of automated switches can be simplified. | 10-02-2008 |