QUALCOMM TECHNOLOGIES, INC. Patent applications |
Patent application number | Title | Published |
20160126934 | SWITCHABLE CAPACITOR ARRAY AND METHOD FOR DRIVING A SWITCHABLE CAPACITOR ARRAY - An improved switchable capacitor array comprises a plurality of n≧2 capacitor units, each comprising a capacitor with a capacitance and a switch unit. The capacitor units are electrically connected in series. Equidistantly spaced impedance values can be obtained if the values of the capacitances are chosen properly. | 05-05-2016 |
20150301638 | SYSTEM AND METHOD FOR INTERFACING APPLICATIONS PROCESSOR TO TOUCHSCREEN DISPLAY FOR REDUCED DATA TRANSFER - System and method for substantially reducing an involvement of an applications processor in receiving data from a touchscreen display. In one aspect, the system includes a controller may be configured in an autonomous mode where it automatically measures the touchscreen display based configuration information received from the applications processor, determines notable events based on the measurement data, stores data and event identifiers related to the notable events in a memory, and sends a notification to the applications processor when event data is available In another aspect, the system includes a controller that filters user interactions events and transmits data related to only notable events to the applications processor. Because of the autonomous and event filtering operations of the touchscreen controller, there are substantially less communications between the controller and the applications processor. This improves the speed and efficiency of the applications processor. | 10-22-2015 |
20150019776 | SELECTIVE CHANGE OF PENDING TRANSACTION URGENCY - The present invention provides a transaction interface to be used between semiconductor intellectual property cores. The urgency attribute of pending transactions can be changed by a special type of transaction at the interface. The urgency can be incremented, raised to at least an indicated value, or changed to a value as specified. For an interface with multiple pending transactions, a mask can be used to indicate one or more IDs, the transactions of which should be changed. | 01-15-2015 |
20150019193 | VERIFICATION USING GENERIC PROTOCOL ADAPTERS - Verification IPs for the verification of semiconductor chip designs are designed to support specific interface protocols. Verification IP is expensive or unavailable to test devices with interfaces of uncommon protocols. Verification IP that uses a generic interface protocol, used in conjunction with simple adapters between interfaces of the VIP that use the generic protocol and interfaces of the device under test that use specific protocols, are reused to test interfaces with different specific protocols if the generic protocol supports a superset of the features of the specific protocols. | 01-15-2015 |
20140149687 | METHOD AND APPARATUS FOR SUPPORTING TARGET-SIDE SECURITY IN A CACHE COHERENT SYSTEM - A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects. | 05-29-2014 |
20140143531 | AUTOMATIC PIPELINE STAGE INSERTION - The optimal configuration of a number of optional pipeline stages within the data paths of systems-on-chip is determined by application of a solver. The solver includes variables such as: the placement of modules physically within the floorplan of the chip; the signal propagation time; the logic gate switching time; the arrival time, after a clock edge, of a signal at each module port; the arrival time at each pipeline stage; and the Boolean value of the state of activation of each optional pipeline stage. The optimal configuration ensures that a timing constraint is met, if possible, with the lowest possible cost of pipeline stages. | 05-22-2014 |
20140095809 | COHERENCY CONTROLLER WITH REDUCED DATA BUFFER - A coherency controller with a data buffer store that is smaller than the volume of pending read data requests. Data buffers are allocated only for requests that match the ID of another pending request. Buffers are deallocated if all snoops receive responses, none of which contain data. Buffers containing clean data have their data discarded and are reallocated to later requests. The discarded data is later read from the target. When all buffers are full of dirty data requests with a pending order ID are shunted into request queues for later service. Dirty data may be foisted onto coherent agents to make buffers available for reallocation. Accordingly, the coherency controller can issue snoops and target requests for a volume of data that exceeds the number of buffers in the data store. | 04-03-2014 |
20140095807 | ADAPTIVE TUNING OF SNOOPS - A coherency controller, such as one used within a system-on-chip, is capable of issuing different types of snoops to coherent caches. The coherency controller chooses the type of snoop based on the type of request that caused the snoops or the state of the system or both. By so doing, coherent caches provide data when they have sufficient throughput, and are not required to provide data when they do not have insufficient throughput. | 04-03-2014 |
20090040590 | MEMS DEVICE AND INTERCONNECTS FOR SAME - A microelectromechanical systems device having an electrical interconnect between circuitry outside the device and at least one of an electrode and a movable layer within the device. A layer of the electrical interconnect is formed directly under, over, or between a partially reflective layer and a transparent layer of the device. The layer of the electrical interconnect preferably comprises nickel. | 02-12-2009 |