QIMONDA NORTH AMERICA CORP. Patent applications |
Patent application number | Title | Published |
20120134204 | CONCENTRIC PHASE CHANGE MEMORY ELEMENT - The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device. | 05-31-2012 |
20100323493 | Method for Fabricating an Integrated Circuit Including Resistivity Changing Material Having a Planarized Surface - An integrated circuit is fabricated by providing a preprocessed wafer including a first electrode, depositing a dielectric material over the preprocessed wafer, etching an opening in the dielectric material to expose a portion of the first electrode and depositing a first resistivity changing material over exposed portions of the etched dielectric material and the first electrode. The first resistivity changing material is planarized to expose the etched dielectric material. A second resistivity changing material is deposited over the etched dielectric material and the first resistivity changing material, and an electrode material is deposited over the second resistivity changing material. | 12-23-2010 |
20100321990 | Memory Including Vertical Bipolar Select Device and Resistive Memory Element - A memory includes a first vertical bipolar select device including a first base and a first emitter, a first phase change element coupled to the first emitter, a second vertical bipolar select device including a second base and a second emitter, a second phase change element coupled to the second emitter, and a buried word line contacting the first base and the second base. | 12-23-2010 |
20100306605 | Apparatus and Method for Manufacturing a Multiple-Chip Memory Device - A method for manufacturing a multiple-chip memory device includes making a volatile memory element on a semiconductor substrate, examining the volatile memory element for one or more initial errors, correcting the one or more initial errors on the semiconductor substrate, incorporating the volatile memory element into the multiple-chip memory device, and incorporating a non-volatile memory element into the multiple-chip memory device. The volatile memory element is examined for one or more secondary errors, after incorporating the volatile memory element and the non-volatile memory element into the multiple-chip memory device. Repair information is stored in a non-volatile memory element, the repair information identifying the one or more secondary errors. | 12-02-2010 |
20100091595 | INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST - An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test. | 04-15-2010 |
20100080075 | Memory Device Refresh Method and Apparatus - In one embodiment, a memory device comprises a plurality of banks and a refresh controller. Each bank is logically divisible into at least two different sections of memory cells during a refresh operation. The refresh controller successively identifies each of the sections using a first portion of a row address and addresses a row of memory cells included in each of the sections using a second portion of the row address. The refresh controller also successively selects two or more different groups of the banks during different time intervals each time a different one of the sections is identified. The refresh controller refreshes the addressed row of memory cells included in the most recently identified section of each bank for the most recently selected group of banks. | 04-01-2010 |
20100054029 | CONCENTRIC PHASE CHANGE MEMORY ELEMENT - The present invention in one embodiment provides a memory device including a first electrode; a second electrode; and a memory cell positioned between the first electrode and the second electrode, the memory cell including a core of a first phase change material and a cladding of a second phase change material, wherein the first phase change material has a lower crystallization temperature than the second phase change material. The present invention also provides methods of forming the above described memory device. | 03-04-2010 |
20100034038 | INTEGRATED CIRCUIT INCLUDING SELECTABLE ADDRESS AND DATA MULTIPLEXING MODE - An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array. | 02-11-2010 |
20100019215 | MUSHROOM TYPE MEMORY CELL HAVING SELF-ALIGNED BOTTOM ELECTRODE AND DIODE ACCESS DEVICE - Memory devices are described along with methods for manufacturing. A memory device as described herein includes a plurality of word lines extending in a first direction, and a plurality of bit lines overlying the plurality of word lines and extending in a second direction. A plurality of memory cells are at cross-point locations. Each memory cell comprises a diode having first and second sides aligned with sides of a corresponding word line. Each memory cell also includes a bottom electrode self-centered on the diode, the bottom electrode having a top surface with a surface area less than that of the top surface of the diode. Each of the memory cells includes a strip of memory material on the top surface of the bottom electrode, the strip of memory material underlying and in electrical communication with a corresponding bit line. | 01-28-2010 |
20090316511 | Method and Apparatus for Selectively Disabling Termination Circuitry - In one embodiment, an electronic device comprises control circuitry. The control circuitry disables termination circuitry coupled to one or more input/output (I/O) signals of the electronic device during at least a portion of a relatively low frequency operation which causes insubstantial signal reflections at the I/O signals. The control circuitry re-enables the termination circuitry prior to the electronic device performing a relatively high frequency operation after completion of the low frequency operation, the high frequency operation causing substantial signal reflections at the I/O signals. The electronic device is a memory device in one embodiment. This way, the termination circuitry may be disabled during at least a portion of a refresh operation performed by the memory device and re-enabled prior to the memory device resuming normal operation (i.e., reads and writes) after completion of the refresh operation. | 12-24-2009 |
20090215206 | System and method for controlling a semiconductor manufacturing process - A semiconductor manufacture and testing device is provided, comprising: a process device configured to perform a semiconductor processing operation on a semiconductor wafer; a testing device configured to perform a testing operation on the semiconductor wafer and generate real-time testing metrics relating to the testing operation; a data storage element configured to store the real-time testing metrics as stored testing metrics; a control and dispatch element configured to receive the stored testing metrics and generate dispatch control signals based on the stored testing metrics and a set of evaluation rules; and a test routing element located between the process element and the testing element, and configured to route the semiconductor wafer either from the process element to the testing element or from the process element around the testing element, based the dispatch control signals. | 08-27-2009 |
20090168569 | Method and device for redundancy replacement in semiconductor devices using a multiplexer - A redundancy replacement scheme for a semiconductor device repairing a faulty memory cell in a column select line group with a spare memory cell in the column select line group based on a physical or logical address of the selected row. | 07-02-2009 |
20090154226 | INTEGRATED CIRCUIT INCLUDING QUENCH DEVICES - An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell. | 06-18-2009 |
20090006887 | System and method for addressing errors in a multiple-chip memory device - A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information. | 01-01-2009 |
20080313494 | MEMORY REFRESH SYSTEM AND METHOD - A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors. | 12-18-2008 |
20080285912 | INTEGRATED CIRCUIT WITH OPTICAL SWITCH - An integrated circuit having an optical switch includes an optical body configured to transmit light, the optical body having a boundary, and a thin film disposed at the boundary that is configured to selectively change a pseudo-Brewster angle of light reflected at the boundary. | 11-20-2008 |
20080285358 | Method and circuit for stressing upper level interconnects in semiconductor devices - A device or method for effectively stressing an interconnect in a current path of a semiconductor device. A bidirectional current is established across the current path, which stresses the interconnect therein. | 11-20-2008 |
20080282001 | PEAK POWER REDUCTION USING FIXED BIT INVERSION - A semiconductor device includes a first circuit block, a second circuit block, and a data bus. The data bus is coupled between the first and second circuit blocks. A first data inverter on the data bus inverts a selected segment of data that is transferred onto the data bus. A second data inverter at an end of the data bus re-inverts the selected segment of data before the data is transferred off the data bus. The data that is transferred onto the data is not analyzed in order to determine the selected segment of data that is inverted. | 11-13-2008 |
20080267258 | System and method for monitoring temperature in a multiple die package - A temperature control circuit, comprising: a plurality of temperature sensors each configured to measure a temperature of a corresponding memory chip chosen from a plurality of memory chips, and to generate a sensor output signal that is set to a first voltage if the measured temperature of the corresponding memory chip meets a temperature requirement, and is set to a floating voltage if the measured temperature of the corresponding memory chip does not meet the temperature requirement, the sensor output signal being connected to an intermediate node; a current source connected to the intermediate node; and a control circuit configured to provide chip control signals to the plurality of memory chips. | 10-30-2008 |
20080238468 | Integrated circuit chip and method for testing an integrated circuit chip - In a method or apparatus such as an integrated circuit (IC) chip including a plurality of circuits for executing a plurality of testmodes, a testmode entry code specifying one of the plurality of testmodes and one of an unrestricted private testmode category and a restricted public testmode category is received. Execution of only a public testmode of the plurality of testmodes is enabled when the testmode entry code specifies the restricted public testmode category. Execution of all of the plurality of testmodes is enabled when the testmode entry code specifies the unrestricted private testmode category. | 10-02-2008 |
20080237587 | Method and circuit for stressing upper level interconnects in semiconductor devices - A device or method for effectively stressing an interconnect in a test current path of a semiconductor device, which test current path is other than a current path used during normal operation of the semiconductor device. An operational voltage is adjusted to a test voltage, the test current path is opened and the test voltage is supplied to the test current path. | 10-02-2008 |
20080228950 | MEMORY POWER DOWN MODE EXIT METHOD AND SYSTEM - A memory includes a circuit having a set terminal for receiving an input signal indicating a request to exit a power-down mode. The circuit is configured to provide an output signal to enable exiting the power-down mode in response to the input signal before the input signal is latched. | 09-18-2008 |
20080222460 | Memory test circuit - A memory test circuit is provided, comprising: an output data selector configured to receive the plurality of read data bits and output a fraction of the plurality of read data bits as a plurality of fractional data bits; and a control circuit configured to select a set of bit positions in the plurality of read data bits whose corresponding values will form the plurality of fractional data bits, wherein the selected set of bit positions is selectable from a plurality of possible sets of bit positions, each actual bit position in the plurality of read data bits being contained in at least one of the possible sets of bit positions, and wherein a fractional length of the plurality of fractional data bits is smaller than a full length of the plurality of read data bits. | 09-11-2008 |
20080201626 | POWER SAVINGS FOR MEMORY WITH ERROR CORRECTION MODE - The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled. | 08-21-2008 |