PTEK TECHNOLOGY CO., LTD. Patent applications |
Patent application number | Title | Published |
20140197475 | POWER MOSFET DEVICE WITH A GATE CONDUCTOR SURROUNDING SOURCE AND DRAIN PILLARS - A power MOSFET device includes at least one MOSFET unit disposed over a substrate, wherein the MOSFET unit includes a plurality of cells and a boundary surrounding the cells. In one embodiment of the present invention, the cell is configured to provide a unit current, and comprises at least one source pillar and at least one drain pillar, a gate conductor surrounding the source pillar and the drain pillar, and an insulating structure electrically separating the gate conductor from the source pillar and the drain pillar, wherein the gate conductor extends from the cell to the boundary. | 07-17-2014 |
20120100683 | TRENCH-TYPED POWER MOS TRANSISTOR AND METHOD FOR MAKING THE SAME - A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region. | 04-26-2012 |
20110163378 | LAYOUT STRUCTURE OF POWER MOS TRANSISTOR - The present invention discloses a layout structure of a transistor unit of a power MOS transistor, wherein the layout structure comprises a drain area, a plurality of body areas, a plurality of source areas and a gate area. The plurality of body areas surround the drain area. The plurality of source areas extend from the perimeters of the plurality of body areas in an anisotropic manner. The gate area is disposed between the drain area and the plurality of source areas. The contacts of the drain area, the plurality of body areas and the plurality of source areas are all disposed on the same side of the layout structure. | 07-07-2011 |
20110163374 | TRENCH-TYPED POWER MOS TRANSISTOR AND METHOD FOR MAKING THE SAME - A trench-typed power MOS transistor comprises a trench-typed gate area, which includes a gate conductor and an isolation layer. A thin sidewall region of the isolation layer is formed between the gate conductor and a well region. A thick sidewall region of the isolation layer is formed between the gate conductor and a double diffusion region. A thick bottom region of the isolation layer is formed between the gate conductor and a deep well region. | 07-07-2011 |
20100276751 | INTEGRATED CIRCUIT UTILIZING TRENCH-TYPE POWER MOS TRANSISTOR - An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region. | 11-04-2010 |
20090294846 | TRENCH-TYPE POWER MOS TRANSISTOR AND INTEGRATED CIRCUIT UTILIZING THE SAME - A power MOS transistor comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region. | 12-03-2009 |