PS4 LUXCO S.A.R.L. Patent applications |
Patent application number | Title | Published |
20160071843 | Semiconductor Device and Method of Fabricating the Same - A semiconductor device includes the following elements. An element isolation portion separates first and second diffusion regions in a semiconductor substrate each other. A first insulating film is formed over the element isolation portion and the first and second diffusion regions. First and second contact plugs are formed over the first and second diffusion regions, respectively. The first and second contact plugs penetrate the first insulating film. A first conductive layer is formed over the first insulating film over the element isolation portion. A second insulating film is formed over the first conductive layer. A third contact plug penetrates the second insulating film, the third contact plug connecting the first contact plug. A second conductive layer is formed over the second insulating film contacting the third contact plug. The first and second conductive layers partly overlap the element isolation portion. | 03-10-2016 |
20160064301 | SEMICONDUCTOR DEVICE - One semiconductor device includes a wiring board, a semiconductor chip, and an encapsulation body. The wiring board includes an insulating base, a conductive pattern that is formed on one surface of the insulating base, and a heat dissipation via that is connected to the conductive pattern. The heat dissipation via is provided so as to penetrate through the insulating base from one surface to the other surface, while being exposed from the lateral side of the insulating base. The semiconductor chip is mounted on the wiring board so as to overlap the conductive pattern. The encapsulation body is formed on the wiring board so as to cover the semiconductor chip. | 03-03-2016 |
20160027758 | SEMICONDUCTOR DEVICE - [Problem] To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. [Solution] In the present invention, the following are provided: a semiconductor chip (100) that has first and second pad electrodes (120 | 01-28-2016 |
20160027755 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE PROVIDED WITH SEMICONDUCTOR CHIP - One semiconductor chip includes a substrate having insulation properties, a plurality of bump electrodes provided on one surface of the substrate, a plurality of recesses provided in the other surface of the substrate, and a solder layer disposed within the recesses. The recesses are formed such that the area of the opening decreases from the other surface side toward the one surface side of the substrate. | 01-28-2016 |
20160027754 | SEMICONDUCTOR DEVICE - To provide a semiconductor device with a wafer level package structure that allows for probing while reducing the area occupied by the pad electrodes. | 01-28-2016 |
20150364181 | OUTPUT SIGNAL GENERATING DEVICE, SEMICONDUCTOR DEVICE AND OUTPUT SIGNAL GENERATION METHOD - An output signal generation device in accordance with disclosed embodiments includes: a phase adjustment unit that generates an output signal on the basis of an input signal and is capable of executing an adjustment operation of setting the phase difference between the input signal and the output signal to a predetermined value; a holding unit that holds a reference voltage; a comparison voltage generation unit that generates a comparison voltage that is dependent on a power supply voltage; and a control unit that intermittently compares the comparison voltage with the reference voltage held in the holding unit, causes the phase adjustment circuit to execute the adjustment operation when the comparison result satisfies a predetermined condition representing a variation in the power supply voltage, and changes the reference voltage held in the holding unit in accordance with the power supply voltage. | 12-17-2015 |
20150303877 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first input terminal; a second input terminal; an inverting amplifier circuit that comprises an input node connected to a first input terminal, an inverting input node connected to a second input terminal, and an output node connected to an output terminal, amplifies a difference between a first input signal supplied to the input node and a second input signal supplied to the second input terminal, and that outputs an output signal whose polarity is inverted from that of the first input signal to the output node; and a non-inverting amplifier circuit that comprises an input node connected to a second input terminal, an inverting input node connected to a first input terminal, and an output node connected to an output terminal, amplifies a difference between the first input signal and the second input signal, and that outputs an output signal whose polarity is the same as that of the first input signal to the output node. | 10-22-2015 |
20150269995 | SEMICONDUCTOR DEVICE - A semiconductor device comprises memory cell array including first memory cell connected between first terminal and second terminal, written to first resistive state by applying voltage in first direction to first memory cell, and written to second resistive state by applying voltage in second direction different from first direction to first memory cell, first line and second line connected to first terminal and second terminal, respectively, third terminal receiving control signal, and first writing circuit comprising first input terminal connected to third terminal, second input terminal connected to one end of second line, and first output terminal connected to one end of first line, and first writing circuit being configured to control first line based on control signal of first input terminal and signal of second input terminal transmitted via second line. | 09-24-2015 |
20150269988 | Semiconductor Device Having Plural Selection Lines - The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group. | 09-24-2015 |
20150263727 | Output Circuit for Semiconductor Device, Semiconductor Device Having Output Circuit, and Method of Adjusting Characteristics of Output Circuit - To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased. | 09-17-2015 |
20150262991 | Device - A semiconductor device has a first and second transistors formed on an active region defined by an insulating region. The active region is divided into a first and second portions arranged in a first direction, and into a third and fourth portions interposed between the first portion and the second portion, and provided adjacent to each other in a second direction orthogonal to the first direction. The first transistor is provided in the first and third portions, and the second transistor is provided in the second and fourth portions. | 09-17-2015 |
20150262647 | Semiconductor Device Latching Data Signal In Response To Strobe Signal And Information Processing System Including The Same - Disclosed herein is a device including a timing control circuit that receives a strobe signal supplied from outside to generate an internal strobe signal that is used as a timing signal to latch a data signal. An operation state of the timing control circuit is changed according to temperature change so as to keep an output timing of the internal strobe signal with respect to an input timing of the strobe signal. | 09-17-2015 |
20150262645 | Semiconductor Device Including Stacked Semiconductor Chips - A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups. | 09-17-2015 |
20150243346 | SEMICONDUCTOR DEVICE HAVING HIERARCHICALLY STRUCTURED WORD LINES - Disclosed herein is a semiconductor device that includes: a memory cell array including sub-word lines, bit lines and memory cells arranged at intersections of the sub-word lines and the bit lines; a plurality of sub-word drivers each drives an associated one of the sub-word lines; and a plurality of main word drivers each supplies a main word signal having one of a selected-level potential and an unselected-level potential to an associated one of the sub-word drivers. Each of the sub-word drivers drives the associated one of the sub-word lines to an active level when an associated one of the main word signals has the selected-level potential, and drives the associated one of the sub-word lines to an inactive level when the associated one of the main word signals has the unselected-level potential. The unselected-level potential of the main word signals is variable depending on an operation mode. | 08-27-2015 |
20150236022 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed herein is a semiconductor device that includes: a semiconductor substrate; a well of a first conductive type that is formed in the semiconductor substrate; an element isolation region embedded in the semiconductor substrate so as to define an active region of the well; first and second gate electrodes each including a side surface and a bottom surface that are covered with the well such that the first and second gate electrodes are formed to traverse the active region, and a peak depth of the well corresponding to the active region is equal to or shallower than a peak depth of the well corresponding to the element isolation region. | 08-20-2015 |
20150235679 | SEMICONDUCTOR DEVICE - A semiconductor device includes data terminal, unit buffers which drive the data terminal and the impedance of which can be adjusted, and control circuits which successively switch the operation of at least two unit buffers selected from unit buffers. Because the operation of the plurality of unit buffers is switched successively, the peak current which flows during an output operation is dispersed, power-supply noise can be controlled, and the output potential can be switched very rapidly and continuously, while a fixed output impedance is maintained. | 08-20-2015 |
20150228658 | Semiconductor Device - Provided is a semiconductor device wherein chip size is reduced, while potential on the dummy word lines is fixed. The semiconductor device is provided with: a memory cell array including a plurality of memory cells, a plurality of word lines for controlling memory operations of the plurality of memory cells, and a plurality of dummy word lines that do not participate in memory operations of the plurality of memory cells; and a guard ring surrounding the memory cell array. The plurality of dummy word lines are electrically fixed to the guard ring. | 08-13-2015 |
20150214224 | MOS TRANSISTOR, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING THE SAME - In a MOS transistor having a structure in which a source and a drain are raised on a substrate by using a selective epitaxial growth technique, a bulk resistance can be reduced while an impurity concentration of a silicon layer is reduced in the selective epitaxial growth. A metal oxide semiconductor transistor includes a gate having a sidewall formed on a silicon substrate, a silicon layer formed on the silicon substrate by selective epitaxial growth, and an inclination portion inclined downward in a direction opposite to the gate on at least a portion of a cross-section including the silicon layer and the gate. | 07-30-2015 |
20150214207 | CHIP STACK, SEMICONDUCTOR DEVICES HAVING THE SAME, AND MANUFACTURING METHODS FOR CHIP STACK - A chip stack ( | 07-30-2015 |
20150206973 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - [Problem] To suppress damage to a semiconductor beam or a semiconductor substrate resulting from dry etching of gate electrode material during manufacture. | 07-23-2015 |
20150187411 | Semiconductor Device Having Data Terminal Supplied with Plural Write Data in Serial - Disclosed herein is a semiconductor device that includes: a frequency dividing circuit dividing a frequency of a first clock signal to generate second clock signals that are different in phase from one another; a multiplier circuit multiplying the second clock signals to generate a third clock signal; a data input/output terminal; data buses; and a data input/output circuit coupled between the data input/output terminal and the data buses. The data input/output circuit includes a data output circuit and a data input circuit. The data output circuit outputs read data supplied in parallel from the data buses to the data input/output terminal in serial in synchronism with the third clock signal. The data input circuit outputs write data supplied in serial from the data input/output terminal to the data buses in parallel in synchronism with a predetermined one of the second clock signals. | 07-02-2015 |
20150145011 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to: a semiconductor substrate; a memory capacitor; and a first compensation capacitor. The semiconductor substrate has at least first and second regions. The memory capacitor is positioned over the first region. The memory capacitor may include, but is not limited to: a first lower electrode; and a first dielectric film covering inner and outer surfaces of the first lower electrode. The first compensation capacitor is positioned over the second region. The first compensation capacitor includes, but is not limited to: a second lower electrode; a second dielectric film covering an inner surface of the second lower electrode; and a first insulating film covering an outer surface of the second lower electrode. | 05-28-2015 |
20150137386 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction. | 05-21-2015 |
20150131395 | Method for triggering a delay-locked loop (DLL) update operation or an impedance calibration operation in a dynamic random access memory device - A method for triggering an adjustment operation in a dynamic random access memory device, the method including receiving a refresh command, generating an execute signal, counting the execute signal to provide a count value, refreshing a memory array based on the count value and triggering the adjustment operation when the count value reaches a predetermined value. | 05-14-2015 |
20150131389 | SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM - The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. | 05-14-2015 |
20150084166 | Semiconductor Device Having Plural Memory Chip - A semiconductor device includes a stacked plurality of memory chips. The memory chips each include a plurality of memory banks, a plurality of read/write buses that are assigned to the respective memory banks, and a plurality of penetration electrodes that are assigned to the respective read/write buses and arranged through the memory chip. Penetration electrodes arranged in the same positions as seen in a stacking direction are connected in common between the chips. In response to an access request, the memory chips activate the memory banks that are arranged in respective different positions as seen in the stacking direction, whereby data is simultaneously input/output via the penetration electrodes that lie in different planar positions. | 03-26-2015 |
20150071013 | Semiconductor Device Having Level Shift Circuit - A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits. | 03-12-2015 |
20140375369 | SUPPLY VOLTAGE GENERATING CIRCUIT - A supply voltage generating circuit that enables a reduction in chip area includes: a booster for outputting a boosted voltage upon generating the boosted voltage by charge pumping of a capacitor element; a power-supply step-down unit for stepping down voltage of an external power supply to a voltage within a breakdown-voltage range of the capacitor element, and applying the stepped-down voltage to the power supply of the booster; and a switch element for switching between application of the external power supply to the power supply of the booster directly or via the power-supply step-down unit. The booster comprises multiple stages of booster circuits. The thicknesses of gate oxide films of capacitor elements constituted by MOS transistors included in respective ones of the booster circuits are the same and are made smaller than the thickness of a gate oxide film of a MOS transistor included in a load circuit having the output of the booster at its power supply. | 12-25-2014 |
20140339619 | SEMICONDUCTOR DEVICE - Problem: To prevent an excess charge from accumulating in a channel region of a transistor. | 11-20-2014 |
20140322830 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory cell array is correct or incorrect; and an analysis circuit that supplies, in a first operation mode, the electrical fuse circuit with an address signal supplied when the determination signal is activated, and supplies, in a second operation mode, the electrical fuse circuit with an address signal supplied when a data mask signal supplied from outside is activated irrespective of the determination signal. | 10-30-2014 |
20140293721 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 10-02-2014 |
20140286074 | SYSTEM AND MEMORY MODULE - A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip. | 09-25-2014 |
20140269108 | SEMICONDUCTOR DEVICE - A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer. | 09-18-2014 |
20140241088 | SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY BIT LINE PAIR - Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively. | 08-28-2014 |
20140239389 | SEMI CONDUCTOR DEVICE HAVING ELEVATED SOURCE AND DRAIN - Semiconductor layers on active areas for transistors in a memory cell region (region A) and a peripheral circuit region (region B) are simultaneously epitaxially grown in the same thickness in which the adjacent semiconductor layers in region A do not come into contact with each other. Only semiconductor layer ( | 08-28-2014 |
20140239384 | SEMICONDUCTOR DEVICE HAVING VERTICAL SURROUNDING GATE TRANSISTOR STRUCTURE, METHOD FOR MANUFACTURING THE SAME, AND DATA PROCESSING SYSTEM - A semiconductor device is provided which includes: semiconductor pillars which include impurity diffused layers, each semiconductor pillar having a width which allows full depletion of a semiconductor forming each semiconductor pillar, the impurity diffused layers being electrically connected to each other; and a common gate section which covers side faces of the pillars. | 08-28-2014 |