| Proton World International N.V. Patent applications |
| Patent application number | Title | Published |
|---|
| 20110271042 | METHOD FOR WRITING INTO AND READING FROM AN ATOMICITY MEMORY - A method for writing data into a reprogrammable non-volatile memory, wherein a marking pattern including several bits is added at the beginning of the data and the set formed of the marking pattern and of the data is written from an address in the memory varying from one write operation to another, the marking pattern being identical for each write operation. | 11-03-2011 |
| 20110252222 | EVENT COUNTER IN A SYSTEM ADAPTED TO THE JAVACARD LANGUAGE - The implementation of a counter in a microcontroller adapted to the JavaCard language while respecting the atomicity of a modification of the value of this counter, wherein the counter is reset by the sending to the microcontroller of an instruction to verify a user code by submitting a correct code, and the value of the counter is decremented by the sending to the microcontroller of the instruction to verify the user code with an erroneous code value. | 10-13-2011 |
| 20110122694 | LIMITATION OF THE ACCESS TO A RESOURCE OF AN ELECTRONIC CIRCUIT - A method and a circuit for controlling the access to at least one resource of an electronic circuit, in which a test of the value of a counter over at least one bit conditions the access to the resource, the counter being automatically reset after a time period independent from whether the circuit is powered or not. | 05-26-2011 |
| 20110061105 | PROTECTION OF A PRIME NUMBER GENERATION AGAINST SIDE-CHANNEL ATTACKS - A method for protecting the generation, by an electronic circuit, of at least one prime number by testing the primality of successive candidate numbers, including for each candidate number tests of primality with respect to prime numbers of at least one set of consecutive prime numbers, wherein the order of application of the tests is modified at least from one prime number generation to another. | 03-10-2011 |
| 20110022753 | SINGLE-WIRE BUS COMMUNICATION PROTOCOL - A method of communication over a single-wire bus between a transmitter device and at least one receiver device, wherein each data bit is transmitted in a frame successively including: a synchronization slot different from a reference voltage of the devices; a first idle slot in a state corresponding to the reference voltage of the circuit; a slot representing the data bit to be transmitted; a second idle slot identical to the first one; a slot intended to contain the state of an optional response bit; and an end slot identical to the idle slot. | 01-27-2011 |
| 20110010775 | PROTECTION OF INFORMATION CONTAINED IN AN ELECTRONIC CIRCUIT - A method and a circuit for protecting data contained in an electronic circuit against a disturbance of its operation, in which a detection of a disturbance conditions the incrementing or the decrementing of a counter over at least one bit, the counter being automatically reset at the end of a time period independent from the fact that the circuit is or not powered. | 01-13-2011 |
| 20100325320 | VERIFICATION OF DATA READ IN MEMORY - A method and a circuit for checking data transferred between a circuit and a processing unit, in which: the data originating from the circuit transit through a first buffer element having a size which is a multiple of the size of data to be subsequently delivered over a bus of the processing unit; an address provided by the processing unit for the circuit is temporarily stored in a second element; and the content of the first element is compared with current data originating from the circuit, at least when they correspond to an address of data already present in this first element. | 12-23-2010 |
| 20100306295 | PROTECTION OF A PRIME NUMBER GENERATION FOR AN RSA ALGORITHM - A method for protecting a generation, by an electronic circuit, of at least one prime number by testing the prime character of successive candidate numbers, including: for each candidate number: the calculation of a reference number involving at least one first random number, and at least one primality test based on modular exponentiation calculations; and for a candidate number having successfully passed the primality test: a test of consistency between the candidate number and its reference number. | 12-02-2010 |
| 20100017553 | INTERFACE BETWEEN A TWIN-WIRE BUS AND A SINGLE-WIRE BUS - A method and a device for converting a first bus including at least a data wire and a clock wire into a single-wire bus, wherein a data bit of the first bus is converted on half a period of the clock signal for transmission over the second bus, a waiting pattern being placed on the second bus during the other half-period. | 01-21-2010 |
| 20090067630 | RECORDING OF A KEY IN AN INTEGRATED CIRCUIT - The invention concerns a method and a system for customizing electronic components ( | 03-12-2009 |
| 20080263533 | IMPLEMENTATION OF PATCHES BY A PROCESSING UNIT - A method and a circuit of execution, by a processing unit, of at least one patch of at least one first program stored in a first non-reprogrammable non-volatile memory, the patch being stored in a second memory, and wherein: each current address of an instruction of the first program provided by the processing unit is compared with values preloaded in at least one volatile storage element; in case of an identity between the current address and a preloaded value, an interrupt is triggered, this interrupt triggering a search, from a correspondence table, for an address of a patch in the second memory; and the patch is executed. | 10-23-2008 |
| 20080232581 | Data parallelized encryption and integrity checking method and device - A method and device for encrypting and/or decrypting binary data blocks protecting both confidentiality and integrity of data sent to or received from a memory. The encryption method comprises steps of: applying to the input data block a reversible scrambling process, the scrambling process providing a scrambled data block in which the bits of the input data block are mixed so that a modification of one bit in the scrambled data block impacts on every bit of the input data block, and applying to the scrambled data block a stream cipher encryption algorithm providing an encrypted data block. Application can be made to secured integrated circuits requiring to securely store data in an external memory. | 09-25-2008 |
| 20080219400 | Event Counter - A counting method and a counter using an integrated circuit memory area, including at least one step of storage of partial values in several words of identical memory sizes, the result of the counting being obtained by arithmetically adding the values contained in the different words. | 09-11-2008 |
