POWERTECH TECHNOLOGY INC Patent applications |
Patent application number | Title | Published |
20150091154 | SUBSTRATELESS PACKAGES WITH SCRIBE DISPOSED ON HEAT SPREADER - Disclosed is a substrateless semiconductor package having a plurality of scribe lines formed on a heat spreader, primarily comprising the heat spreader, a chip disposed on the heat spreader and an encapsulant. Formed on a thermally dissipating surface of the heat spreader are a plurality of scribe line grooves with a plurality of openings formed inside to penetrate through the die-attaching surface of the heat spreader. The chip is disposed on the die-attaching surface and the encapsulant is formed on the die-attaching surface to encapsulate a first surface of the chip on which a plurality of external pads are formed Without being covered by the encapsulant. Therein, the encapsulant is filled in the scribe line grooves via the openings so that a scribe line pattern exposed from the thermally dissipating surface is formed. | 04-02-2015 |
20150061718 | WAFER-LEVEL TESTING METHOD FOR SINGULATED 3D-STACKED CHIP CUBES - Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions. Accordingly, the real-production wafer-level testing step can be run smoothly without unnecessary shut down of adjustment or repair leading to the maximum productivity without overkill issues. | 03-05-2015 |
20150048499 | FINE-PITCH PILLAR BUMP LAYOUT STRUCTURE ON CHIP - Disclosed is a fine-pitch pillar bump layout structure on chip, comprising a chip, a passivation layer and at least two pillar bumps. Bonding pads of the chip are disposed along an X-axis. Openings of the passivation layer have a first aspect ratio. Pillar bumps are disposed on the bonding pads and each has a pillar body and a solder cap. Each pillar body has a plurality of symmetrical raised blocks disposed on the passivation layer and extended in both directions of Y-axis. The pillar bodies have shrunk bump widths along the X-axis so that a second aspect ratio is at least 1.5 times greater than the first aspect ratio and to partially expose the bonding pads and to make the central points of the pillar bodies be vertically aligned with the central points of the openings of the passivation layer. | 02-19-2015 |
20150048496 | FABRICATION PROCESS AND STRUCTURE TO FORM BUMPS ALIGNED ON TSV ON CHIP BACKSIDE - Disclosed is a fabrication process of fabricating bumps aligned on TSVs on chip backside. A plurality of TSV pillars are embedded inside the semiconductor layer of an IC substrate where the sidewalls the bottom of the TSV pillars toward the chip backside are covered by a dielectric liner. Then, the thickness of the semiconductor layer is reduced from the chip backside to make the bottom portion of the dielectric liner to be exposed from the chip backside by including a first selectively etching. Then, a backside passivation is disposed on the chip backside without disposing on the bottoms of the TSV pillars. Then, the bottom portion of the dielectric liner is removed by a second selectively etching. An UBM layer is disposed on the backside passivation. A plurality of bumps are disposed on the UBM layer where the interface between each bump and each TSV pillar is a central protrusion lumped toward the corresponding bump. Accordingly, the interfaces between the bumps and the TSV pillars offer an increased bonding area to increase adhesion anchoring effects for the bumps bonded on the UBM layer through the central protrusions. | 02-19-2015 |
20140167231 | LEADFRAME-TYPE SEMICONDUCTOR PACKAGE HAVING EMI SHIELDING LAYER CONNECTED TO GROUND - Disclosed is a leadframe-type semiconductor package having an EMI shielding layer connected to ground, comprising a leadframe, a chip, an encapsulant, and an EMI shielding layer. The encapsulant has two lead-extending sides and two leadless sides. The EMI shielding layer covers at least one surface of the encapsulant and the leadless sides. A metal tie bar coupling to the die attach pad of the leadframe has a cut end aligned with and exposed on one of the leadless sides. A ground lead also has a cut end aligned with and exposed on one of the leadless sides Since the EMI shielding layer covers and electrically connects the cut ends of the metal tie bar and the ground lead, the die pad with its metal tie bar of the leadframe is connected to the ground lead through external electrical connection outside the encapsulant to allow the die pad having ground potential. | 06-19-2014 |
20130076384 | METHOD FOR TESTING MULTI-CHIP STACKED PACKAGES - Disclosed is a method for testing multi-chip stacked packages. Initially, one or more substrate-less chip cubes are provided, each consisting of a plurality of chips such as chips stacked together having vertically connected with TSV's where there is a stacked gap between two adjacent chips. Next, the substrate-less chip cubes are adhered onto an adhesive tape where the adhesive tape is attached inside an opening of a tape carrier. Then, a filling encapsulant is formed on the adhesive tape to completely fill the chip stacked gaps. Next, the tape carrier is fixed on a wafer testing carrier in a manner to allow the substrate-less chip cubes to be loaded into a wafer tester without releasing from the adhesive tape. Accordingly, the probers of the wafer tester can be utilized to probe testing electrodes of the substrate-less chip cubes so that it is easy to integrate this testing method in TSV fabrication processes. | 03-28-2013 |
20120327729 | MEMORY TESTING DEVICE HAVING CROSS INTERCONNECTIONS OF MULTIPLE DRIVERS AND ITS IMPLEMENTING METHOD - Disclosed is a memory testing device having cross interconnections of multiple drivers, comprising a first wiring bus and a second wiring bus connected to a first device area and a third wiring bus and a fourth wiring bus connected to a second device area. A first I/O driver module bus is connected to the first wiring bus through a first driving bus. A second I/O driver module bus is connected to the third wiring bus through the second driving bus. The fourth wiring bus is Y-shaped connected to the node between the first wiring bus and first driving bus. And, the second wiring bus is Y-shaped connected to the node between the third wiring bus and the second driving bus. | 12-27-2012 |
20120139110 | TAPE - A tape for carrying at least a semiconductor package structure comprising a body, a carrying plate and a side wall is provided. The body has at least an opening. The carrying plate is capable of carrying the semiconductor package structure and has a plurality of containing portions. The side wall surrounds the carrying plate and connects between the body and the carrying plate. A side surface of the semiconductor package structure leans against the side wall and a plurality of solder balls disposed on a bottom surface of the semiconductor package structure are contained in the containing portion. Accordingly, the solder balls may be protected from being damaged by the carrying plate. | 06-07-2012 |
20100162789 | APPARATUS FOR DROP TESTING AND METHOD UTILIZING THE SAME - An apparatus for drop testing is disclosed. The apparatus has a drop angle setting jig that horizontally moves on a support frame and positions a test object at a predetermined angle by clamping with a fixture. The jig provides a second datum plane and is connected to a moveable holding frame, with the holding frame providing a first datum plane. After the fixture clamps the testing object, the jig can be pulled back without touching the testing object, and the testing object stays still. Therefore, the testing object can be precisely positioned. Furthermore, with the sliding track and the stopping block, the jig is able to quickly return back to the reference position. | 07-01-2010 |
20100127362 | SEMICONDUCTOR PACKAGE HAVING ISOLATED INNER LEAD - A semiconductor package with isolated inner lead(s) is revealed. A chip is disposed on a leadframe segment and encapsulated by an encapsulant. The leadframe segment includes a plurality of leads, an isolated lead, and an external lead where each lead has an internal portion and an external portion. The isolated inner lead is completely formed inside the encapsulant and the external lead is partially formed inside and extended outside the encapsulant. At least one of the internal portions of the leads is located between the isolated inner lead and the external lead. Two fingers are formed at two opposing ends of the isolated inner lead without covering by the chip. One of the fingers imitates a plurality of fingers of the leads to arrange along a first side of the chip. The other finger of the isolated inner lead and a finger of the external lead are arranged along a second side of the chip. A jumping wire electrically connecting the isolated inner lead and the external lead is adjacent to the second side to achieve the redistribution of pin assignments without affecting wire-bonding. Especially, this package can be applied for multi-chip stacking. | 05-27-2010 |
20100000384 | Method for cutting large-size wafer and apparatus for the same - The present invention discloses a method for cutting a large-size wafer and an apparatus for the same. The method of the present invention decreases the frequency of wafer transmission to reduce wafer damages, wherein a wafer is always carried by an identical working susceptor, and the working susceptor is moved to the related devices performing corresponding works, or wherein a wafer is always carried by an identical working susceptor, and the related devices are moved to the working susceptor to perform corresponding works. | 01-07-2010 |
20090298233 | Method for Fabricating Semiconductor Elements - The present invention discloses a method for fabricating semiconductor elements, which comprises steps: providing a substrate having a wiring pattern on the upper surface thereon electrically connecting a wafer to the substrate for signal input and output; filling a resin into between the wafer and tire substrate to fix the wafer to the substrate; and singulating the combination of the wafer and the substrate into a plurality of semiconductor elements. Therefore, the present can simplify the fabrication process or semiconductor elements. | 12-03-2009 |
20090294933 | Lead Frame and Chip Package Structure and Method for Fabricating the Same - The present invention discloses a lead frame and chip package structure, which comprises a plurality of leads including a plurality of inner leads and a plurality of outer leads; a plurality of chips arranged on a portion of the inner leads; a plurality of connecting wires electrically connecting the chips to the other inner leads; a support member arranged on the lower surface of the inner leads and having a fillister with an opening, wherein the backside of the opening faces the inner leads; and a resin encapsulant covering the leads, the chips, the connecting wires and the support member, and filling up the fillister with a portion of the outer leads and a portion of the surface of the support member being revealed. Further, the present invention also discloses a method for fabricating a lead frame and chip package structure, whereby the quality of a chip package is promoted. | 12-03-2009 |
20090283878 | LEAD-ON-CHIP SEMICONDUCTOR PACKAGE AND LEADFRAME FOR THE PACKAGE - A LOC semiconductor package with the leadframe for the package is revealed. The LOC semiconductor package primarily comprises a plurality of leadframe's leads, at least a tie bar, a chip, and an encapsulant encapsulating the components mentioned above. Each lead has a bonding finger. The tie bar has a dummy finger where the dummy finger is linearly disposed at one side of the disposition area of the bonding fingers. The chip has an active surface with the bonding fingers. When the dummy finger and the bonding fingers are disposed above the active surface by a die-attaching layer, the dummy finger is adjacent to one edge of the active surface. The bonding fingers are electrically connected with the bonding pads. The dummy finger will bear the concentrated stresses to avoid the bonding fingers on the active surface to delamination or break due to external stresses and to avoid the interference to the layout of the leads. | 11-19-2009 |
20090236739 | SEMICONDUCTOR PACKAGE HAVING SUBSTRATE ID CODE AND ITS FABRICATING METHOD - A semiconductor package with a substrate ID code and its manufacturing method are revealed. A circuit and a solder mask are formed on the bottom surface of a substrate where the solder mask covers most of the circuit and a circuit-free zone of the substrate. A chip is disposed on the top surface of the substrate. A substrate ID code consisting of a plurality of laser marks is inscribed in the solder mask or in a portion of an encapsulant on the bottom surface away from the circuit to show the substrate lot number on the bottom surface. Therefore, quality control and failure tracking and management can easily be implemented by tracking the substrate ID code from the semiconductor package without changing the appearance of the semiconductor package. Furthermore, the substrate ID code can be implemented by the existing laser imprinting machines for semiconductor packaging processes and be formed at the same time of formation of a product code. The complexity of the semiconductor packaging processes is not increased and the circuits of the substrates are not easily damaged. | 09-24-2009 |
20090200685 | Electronic packaging method and apparatus - The present invention utilizes a panel substrate as the packaging substrate carried by a working susceptor. Packaging devices are hung in the nearby of the working susceptor and moved by robot arms to the working susceptor, whereby the problems of substrate warpage and substrate transportation are overcome. Further, identical or different packaging steps can be simultaneously performed in different areas of a panel substrate, whereby the cost is reduced and the product yield is promoted. | 08-13-2009 |
20090173528 | CIRCUIT BOARD READY TO SLOT - A circuit substrate ready to slot is revealed, primarily comprising a board base with slot-reserved area. A plurality of bonding fingers, a plating bus loop, and a plurality of plating lines disposed on the bottom surface of the board base. The bonding fingers are located adjacent to but outside the slot-reserved area and the plating bus loop is located inside the slot-reserved area. The plating lines connect the bonding fingers to the plating bus lines. The plating bus loop includes two side bars closer to the long sides of the slot-reserved area than the bonding fingers to the long sides. Accordingly, the lengths of the plating lines within the slot-reserved area are shortened. It is possible to solve the issues of metal burs and shifting of the remaining plating lines when routing a slot along the peripheries of the slot-reserved area. Moreover, the plating current can evenly distribute to improve the plating qualities on the surfaces of the bonding fingers. | 07-09-2009 |
20090160038 | Semiconductor package with leads on a chip having multi-row of bonding pads - A LOC leadframe-based semiconductor package includes a chip with multiple rows of bonding pads. At least a bus bar is attached to the chip and is disposed between a first row of bonding pads and the fingers of the leads. A plurality of bonding wires electrically connect the first row of bonding pads to the fingers of the leads. The portion of the bus bar attached to the active surface of the chip includes a bent section bent away from the fingers. A long bonding wire electrically connects one of a second row of bonding pads to one of the fingers of the leads by overpassing the bent section. Therefore, the distance between the long bonding wire and the bus bar is increased to avoid electrical short between the long bonding wire and the bus bar and to enhance the quality of electrical connections of the LOC semiconductor package. | 06-25-2009 |
20090096070 | Semiconductor package and substrate for the same - A semiconductor package is revealed with a special designed substrate. The substrate has a plurality of fingers, a dummy metal pattern, and at least a peripheral slot penetrating through the substrate. The dummy metal pattern is aligned to two opposing sides of the peripheral slot and is electrically isolated from the fingers. A chip is disposed on the substrate and is electrically connected to the fingers. An encapsulant is completely filled the peripheral slot. The peripheral slot can enhance the mold flow and eliminate the mold flash. The shape of the dummy metal pattern aligned to the peripheral slot is used to offer stiffening edges to prevent the substrate from warpage and from breakage at peripheries, to enhance the thermal stress resistance due to thermal cycles, and to avoid damages to the chip. | 04-16-2009 |