| POWERCHIP TECHNOLOGY CORPORATION Patent applications |
| Patent application number | Title | Published |
|---|
| 20120104088 | TANK-LOCKING DEVICE, SYSTEM FOR MANAGING LIQUID SUPPLY AND METHOD USING THE SAME - A system for managing liquid supply suitable for a process equipment with a liquid tank is disclosed. The system includes a host, a data-reading tool, a system controller and a tank-locking device. The host stores a built-in liquid database. The data-reading tool used for reading data related to the liquid tank is electrically connected to the host. The host receives the data related to the liquid tank from the data-reading tool, and the received data mapped with the liquid database. The system controller drives the tank-locking device according to the signal from the host to whether or not allow replacement of the liquid tank. | 05-03-2012 |
| 20120103434 | TANK-LOCKING DEVICE, SYSTEM FOR MANAGING LIQUID SUPPLY AND METHOD USING THE SAME - A system for managing liquid supply suitable for a process equipment with a liquid tank is disclosed. The system includes a host, a data-reading tool, a system controller and a tank-locking device. The host stores a built-in liquid database. The data-reading tool used for reading data related to the liquid tank is electrically connected to the host. The host receives the data related to the liquid tank from the data-reading tool, and the received data mapped with the liquid database. The system controller drives the tank-locking device according to the signal from the host to whether or not allow replacement of the liquid tank. | 05-03-2012 |
| 20120092925 | VERTICAL CAPACITOR-LESS DRAM CELL, DRAM ARRAY AND OPERATION OF THE SAME - A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer. | 04-19-2012 |
| 20120018801 | VERTICAL CHANNEL TRANSISTOR ARRAY AND MANUFACTURING METHOD THEREOF - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 01-26-2012 |
| 20120015494 | METHOD FOR FABRICATING BOTTOM ELECTRODE OF CAPACITORS OF DRAM - A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased. | 01-19-2012 |
