POWERCHIP TECHNOLOGY CORPORATION Patent applications |
Patent application number | Title | Published |
20150355665 | NEGATIVE REFERENCE VOLTAGE GENERATING CIRCUIT AND NEGATIVE REFERENCE VOLTAGE GENERATING SYSTEM USING THE SAME - A negative reference voltage generating circuit includes a clamp-type reference voltage circuit and a differential amplifier. The clamp-type reference voltage circuit is connected between a node of a first negative voltage which is equal to or lower than the ground voltage and a node of a second negative voltage which is lower than the first negative voltage, and is formed by connecting a first circuit and a second circuit in parallel. The differential amplifier amplifies the difference between a node voltage in the first circuit and a node voltage in the second circuit, and outputs a negative reference voltage. | 12-10-2015 |
20150325299 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF - A non-volatile semiconductor memory device utilized to implement the writing of data by adding a predetermined voltage for assigning a word line to a non-volatile memory cell includes a control process or generating and outputting control data implementing a program code for writing data including a word line assignment command and voltage source assignment data, a writing controller decoding the control data and generating a control signal of the word line assignment command and a control signal of the voltage source assignment data, a voltage generation circuit generating several voltages for writing data, and a switch circuit selecting a voltage, corresponding to voltage source assignment data, among several voltages, according to the control signal of the word line assignment command and the control signal of voltage source assignment data and outputting the selected voltage to the word line corresponding to the word line assignment command. | 11-12-2015 |
20150255614 | SPLIT GATE FLASH MEMORY AND MANUFACTURING METHOD THEREOF - A split gate flash memory is provided. A device isolation structure is disposed in a substrate to define an active area. A first doping region and a second doping region are respectively disposed in an active area of the substrate. A select gate is disposed in a trench in the substrate, and a side of the select gate is adjacent to the first doping region. A gate dielectric layer is disposed between the select gate and the substrate. A floating gate is disposed on the substrate, a side of the floating gate overlaps to the second doping region, and a portion of the floating gate is disposed on the select gate. An inter-gate dielectric layer is disposed between the floating gate and the select gate and between the floating gate and the substrate. | 09-10-2015 |
20150228895 | RESISTIVE RANDOM ACCESS MEMORY - A resistive random access memory including a first electrode, a dielectric layer, at least a first nanostructure and a second electrode is provided. The dielectric layer is disposed on the first electrode. The first nanostructure is disposed between the first electrode and the dielectric layer and includes a plurality of first cluster-type-type metal nanoparticles and a plurality of first covering-type metal nanoparticles. The first cluster-type-type metal nanoparticles are disposed on the first electrode. The first covering-type metal nanoparticles covers the first cluster-type-type metal nanoparticles, wherein a diffusion coefficient of the first cluster-type-type metal nanoparticles is larger than a diffusion coefficient of the first covering-type metal nanoparticles. The second electrode is disposed on the dielectric layer. | 08-13-2015 |
20150137204 | MEMORY CIRCUIT STRUCTURE AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME - A semiconductor process for manufacturing particular patterns includes the steps of forming a target layer and evenly-spaced core bodies on a substrate, conformally forming a hard mask layer, forming a first photoresist covering a predetermined region on the hard mask layer wherein the predetermined region encompasses at least two core bodies, performing a first etch process to remove a portion of the hard mask layer outside the predetermined region and expose a number of core bodies, removing the exposed core bodies, forming a second photoresist at least encompassing all the recesses in the predetermined region, and performing a second etch process to pattern the target layer. | 05-21-2015 |
20150078100 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD THEREOF - A nonvolatile memory cell array is divided into first and second cell arrays, the page buffer circuit is arranged between the first and second cell arrays, a second latch circuit is arranged by the outside edge section of the first cell array, and the page buffer circuit is connected to the second latch circuit via a global bit line of the first cell array. The data writing to the first or second cell array is controlled by transmitting the writing data to the page buffer circuit via the global bit line from the second latch circuit, after the writing data is latched in the second latch circuit. The data reading of outputting the data read from the first or second cell array to the external circuit is controlled by transmitting data to the second latch circuit from the page buffer circuit via the global bit line. | 03-19-2015 |
20140256104 | MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY - A manufacturing method of a vertical channel transistor array is provided. The method includes following steps. A plurality of embedded word lines are formed at bottoms of trenches, and each of the embedded word lines is located at a first side wall of one of the trenches and connected to first sides of the semiconductor pillars in the same row. Each of the embedded word lines is not connected to second sides of the semiconductor pillars in the same row, and the first sides are opposite to the second sides. Only one embedded word line is correspondingly connected to the semiconductor pillars arranged in one row. An isolation structure is formed between a second side wall of each of the trenches and each of the embedded word lines. The first side wall is opposite to the second side wall. | 09-11-2014 |
20140255829 | MASK FOR DUAL TONE DEVELOPMENT - A mask for dual tone development including a opening pattern region and a partial transparent pattern is provided. The opening pattern region includes a plurality of transparent patterns and a plurality of opaque patterns, and a plurality of opening patterns is defined in a photoresist for dual tone development by the transparent patterns and the opaque patterns. The partial transparent pattern surrounds the opening pattern region. | 09-11-2014 |
20140140129 | PROGRAMMING METHOD FOR NAND FLASH MEMORY DEVICE TO REDUCE ELECTRONS IN CHANNELS - In a programming method for a NAND flash memory device, a self-boosting scheme is used to eliminate excess electrons in the channel of an inhibit cell string that would otherwise cause programming disturb. The elimination is enabled by applying a negative voltage to word lines connected to the inhibit cell string before boosting the channel, and this leads to bringing high program immunity. A row decoder circuitry to achieve the programming operation and a file system architecture based on the programming scheme to improve the efficiency of file management are also described. | 05-22-2014 |
20140091273 | RESISTIVE RANDOM ACCESS MEMORY AND FABRICATION METHOD THEREOF - A resistive random access memory (RRAM) unit includes at least one bit line extending along a first direction, at least one word line disposed on a substrate and extending along a second direction so as to intersect the bit line, a hard mask layer on the word line to isolate the word line from the bit line, a first memory cell on a sidewall of the word line, and a second memory cell on the other sidewall of the word line. | 04-03-2014 |
20140036597 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND READING-OUT METHOD THEREFORE - In a non-volatile semiconductor memory device outputting a data value determined according to a majority rule by reading-out data from each memory cell for an odd number of times, an odd number of latch circuits, each of which comprises a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence, is provided. The capacitor of each latch circuit is connected in parallel after the capacitor of each latch circuit selectively holds the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and the data value is determined by the majority rule based on a composite voltage of the capacitor of each latch circuit connected in parallel. | 02-06-2014 |
20140022845 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND READOUT METHOD THEREOF - A non-volatile semiconductor device includes: memory strings formed by series connection of memory cells respectively connected to word lines, wherein each memory string is connected between a bit line and a source line via first and second select gate transistors; and a control circuit controlling the first and second select gate transistors, such that when voltage of the word line is raised to a predetermined value for data readout from the memory cell, a first status where the first select gate transistor is turned on and the second select gate transistor is turned off and second status where the first select gate transistor is turned off and the second select gate transistor is turned on are generated alternately. | 01-23-2014 |
20140004665 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
20140002179 | INTERNAL VOLTAGE TRIMMING CIRCUIT, METHOD THEREOF AND SEMICONDUCTOR CIRCUIT DEVICE COMPRISING THE SAME | 01-02-2014 |
20130249595 | LEVEL SHIFT CIRCUIT AND SEMICONDUCTOR DEVICE USING LEVEL SHIFT CIRCUIT - A level shift circuit, for outputting a data output signal with a second level via an output inverter after a data input signal with a first level is stored in a latch, includes a level set circuit, when the output data signal outputs with a low level, setting the output data signal to a low level in response to a change of the input data signal. The level set circuit is connected to an output terminal of the output inverter, and has an NMOS transistor having a drain electrode and a source electrode coupled to a ground, wherein the NMOS transistor turns on in response to the input data signal with a high level. | 09-26-2013 |
20130217218 | FABRICATING METHOD OF NON-VOLATILE MEMORY - A fabricating method of a non-volatile memory is provided. A tunneling dielectric layer and a first conductive layer are sequentially formed on a substrate. Isolation structures are formed in the first conductive layer, the tunneling dielectric layer and the substrate. The first conductive layer is patterned to form protruding portions. A portion of the isolation structures is removed, so that a top surface of each isolation structure is disposed between a top surface of the first conductive layer and a surface of the substrate. An inter-gate dielectric layer is formed on the substrate. A second conductive layer is formed on the inter-gate dielectric layer. The second conductive layer is patterned to form control gates, and the first conductive layer is patterned to form floating gates. The protruding portion of each floating gate is fully covered and surrounded by the control gate in any direction. | 08-22-2013 |
20130203228 | METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE - A method of fabricating a non-volatile memory is provided. A tunneling dielectric layer and a first patterned conductive layer are sequentially formed on a substrate. A patterned inter-gate dielectric layer and a second patterned conductive layer are stacked on a first surface of the first patterned conductive layer, and a second surface of the first patterned conductive layer is exposed. The second surface is adjacent to the first surface. The substrate is covered by a passivation layer, and a first sidewall of the first patterned conductive layer is exposed. A recess is formed on the first sidewall of the first patterned conductive layer, such that the first sidewall has a sharp corner. A portion of the passivation layer on the second surface is removed, such that the sharp corner of the first patterned conductive layer is exposed. | 08-08-2013 |
20130200328 | PHASE CHANGE MEMORY DEVICES - A phase change memory device is provided, including: a substrate; a first dielectric layer disposed over the substrate; a first electrode disposed in the first dielectric layer; a second dielectric layer formed over the first dielectric layer, covering the first electrode; a heating electrode disposed in the second dielectric layer, contacting the first electrode; a phase change material layer disposed over the second dielectric layer, contacting the heating electrode; and a second electrode disposed over the phase change material layer, wherein the heating electrode includes a first portion contacting the first electrode and a second portion contacting the phase change material layer, and the second portion of the heating electrode includes metal silicides, and the first portion of the heating electrode includes no metal silicides, and includes refractory metal materials or noble metal materials. | 08-08-2013 |
20130137270 | METHOD FOR FORMING CONTACT HOLE - A method for forming contact holes includes following steps. A substrate including a dense region and an isolation region is provided. A material layer is formed on the substrate. Sacrificed patterns are formed on the material layer in the dense region, wherein there is a first opening between the two adjacent sacrificed patterns. A spacer is formed on each of two sides of each of the sacrificed patterns, wherein the spacers are separated from each other. The sacrificed patterns are removed to form a second opening between two adjacent spacers. A planar layer is formed to fill up the second openings. A first slit is formed in the planar layer, wherein the first slit exposes a portion of the material layer under the second openings. The portion of the material layer exposed by the first slit is removed to form third openings in the material layer. | 05-30-2013 |
20130130471 | MANUFACTURING METHOD OF VERTICAL CHANNEL TRANSISTOR ARRAY - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 05-23-2013 |
20120261736 | NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A non-volatile memory device includes a substrate, a gate stack, a selecting gate, an erasing gate, a source region, and a drain region. The gate stack on the substrate includes from bottom to top a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a spacer that is located between sidewalls of the control gate and the inter-gate dielectric layer. A side of the floating gate adjacent to the erasing gate has a warp-around profile and a sharp corner protruding from a vertical surface of the spacer. The selecting and erasing gates are respectively located at first and second sides of the substrate of the gate stack. The source region is located in the substrate under the erasing gate. The drain region is located in the substrate at a side of the selecting gate. | 10-18-2012 |
20120244785 | POLISHING METHOD AND POLISHING SYSTEM - A polishing method and a polishing system are provided. By means of adjusting a rotational center of a polishing article corresponding to positions of a polishing pad or polishing pads, a polishing rate of the polishing article surface has a better uniformity, resulted from compensation of polishing rates at the rotational center of the polishing article. | 09-27-2012 |
20120181606 | VERTICAL CHANNEL TRANSISTOR ARRAY AND MANUFACTURING METHOD THEREOF - A vertical channel transistor array includes a plurality of embedded bit lines, a plurality of bit line contacts, a plurality of embedded word lines, and a current leakage isolation structure. An active area of a vertical channel transistor is defined by the semiconductor pillars. The embedded bit lines are disposed in parallel in a semiconductor substrate and extended in a column direction. Each of the bit line contacts is respectively disposed at a side of one of the embedded bit lines. The embedded word lines are disposed in parallel above the embedded bit lines and extended in a row direction. Besides, the embedded word lines and the semiconductor pillars in the same row are connected but spaced by a gate dielectric layer. The current leakage isolation structure is disposed at ends of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 07-19-2012 |
20120161221 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory having a tunneling dielectric layer, a floating gate, a control gate, an inter-gate dielectric layer and a first doping region and a second doping region is provided. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer, and has a protruding portion. The control gate is disposed over the floating gate to cover and surround the protruding portion. The protruding portion of the floating gate is fully covered and surrounded by the control gate in any direction, including extending directions of bit lines, word lines and an included angle formed between the word line and the bit line. The inter-gate dielectric layer is disposed between the floating gate and the control gate. The first doping region and the second doping region are respectively disposed in the substrate at two sides of the control gate. | 06-28-2012 |
20120153371 | DYNAMIC RANDOM ACCESS MEMORY CELL AND ARRAY HAVING VERTICAL CHANNEL TRANSISTOR - A dynamic random access memory cell having vertical channel transistor includes a semiconductor pillar, a drain layer, an assisted gate, a control gate, a source layer, and a capacitor. The vertical channel transistor has an active region formed by the semiconductor pillar. The drain layer is formed at the bottom of the semiconductor pillar. The assisted gate is formed beside the drain layer, and separated from the drain layer by a first gate dielectric layer. The control gate is formed beside the semiconductor pillar, and separated from the active region by a second gate dielectric layer. The source layer is formed at the top of the semiconductor pillar. The capacitor is formed to electrical connect to the source layer. | 06-21-2012 |
20120104088 | TANK-LOCKING DEVICE, SYSTEM FOR MANAGING LIQUID SUPPLY AND METHOD USING THE SAME - A system for managing liquid supply suitable for a process equipment with a liquid tank is disclosed. The system includes a host, a data-reading tool, a system controller and a tank-locking device. The host stores a built-in liquid database. The data-reading tool used for reading data related to the liquid tank is electrically connected to the host. The host receives the data related to the liquid tank from the data-reading tool, and the received data mapped with the liquid database. The system controller drives the tank-locking device according to the signal from the host to whether or not allow replacement of the liquid tank. | 05-03-2012 |
20120103434 | TANK-LOCKING DEVICE, SYSTEM FOR MANAGING LIQUID SUPPLY AND METHOD USING THE SAME - A system for managing liquid supply suitable for a process equipment with a liquid tank is disclosed. The system includes a host, a data-reading tool, a system controller and a tank-locking device. The host stores a built-in liquid database. The data-reading tool used for reading data related to the liquid tank is electrically connected to the host. The host receives the data related to the liquid tank from the data-reading tool, and the received data mapped with the liquid database. The system controller drives the tank-locking device according to the signal from the host to whether or not allow replacement of the liquid tank. | 05-03-2012 |
20120092925 | VERTICAL CAPACITOR-LESS DRAM CELL, DRAM ARRAY AND OPERATION OF THE SAME - A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer. | 04-19-2012 |
20120018801 | VERTICAL CHANNEL TRANSISTOR ARRAY AND MANUFACTURING METHOD THEREOF - A vertical channel transistor array has an active region formed by a plurality of semiconductor pillars. A plurality of embedded bit lines are arranged in parallel in a semiconductor substrate and extended along a column direction. A plurality of bit line contacts are respectively disposed on a side of one of the embedded bit lines. A plurality of embedded word lines are arranged in parallel above the embedded bit lines and extended along a row direction. Besides, the embedded word lines connect the semiconductor pillars in the same row with a gate dielectric layer sandwiched between the embedded word lines and the semiconductor pillars. The current leakage isolation structure is disposed at terminals of the embedded bit lines to prevent current leakage between the adjacent bit line contacts. | 01-26-2012 |
20120015494 | METHOD FOR FABRICATING BOTTOM ELECTRODE OF CAPACITORS OF DRAM - A method for manufacturing a capacitor bottom electrode of a dynamic random access memory is provided. The method comprises providing a substrate having a memory cell region and forming a polysilicon template layer on the memory cell region of the substrate. A supporting layer is formed on the polysilicon template layer and plural openings penetrating through the supporting layer and the polysilicon template layer are formed and a liner layer is formed on at least a portion of the polysilicon template layer exposed by the openings A conductive layer substantially conformal to the substrate is formed on the substrate. A portion of the conductive layer on the supporting layer is removed so as to form plural capacitor bottom electrodes. Using the polysilicon template layer, the openings with relatively better profiles are formed and the dimension of the device can be decreased. | 01-19-2012 |