| POLAR SEMICONDUCTOR, INC. Patent applications |
| Patent application number | Title | Published |
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| 20110147865 | INTEGRATED HYBRID HALL EFFECT TRANSDUCER - A Hall effect transducer in a semiconductor wafer comprises a first layer of semiconducting material, a second layer of semiconducting material, and a contact structure configured to provide a path for electrical current to pass through the second layer. The second layer has higher electron hole mobility than the first layer, and is epitaxially grown atop the first layer. | 06-23-2011 |
| 20110115407 | SIMPLIFIED CONTROL OF COLOR TEMPERATURE FOR GENERAL PURPOSE LIGHTING - A lighting system includes at least first and second light sources providing first and second colors of light. Control circuitry is operatively coupled to the first and second light sources, and is configured to control the first and second light sources relative to one another to provide a color point that is linearly controlled to approximate a non-linear target lighting behavior in the CIE 1931 color space. | 05-19-2011 |
| 20110110134 | Saving energy mode (SEM) for an interleaved power factor correction (PFC) converter - A method of controlling a power factor correction (PFC) converter having a first PFC sub-circuit and a second PFC sub-circuit determines when to transition the PFC converter between an interleaved mode and a saving energy mode (SEM). The method includes generating an amplified error signal based on a monitored output voltage of the PFC converter. The second PFC sub-circuit is disabled in response to the amplified error signal being less than a first threshold value and enabled in response to the amplified error signal exceeding a second threshold value. | 05-12-2011 |
| 20110110133 | FREQUENCY COMPRESSION FOR AN INTERLEAVED POWER FACTOR CORRECTION (PFC) CONVERTER - A controller provides frequency compression for an interleaved power factor correction (PFC) converter that determines the ON and OFF times of each switch associated with the PFC converter to prevent operating frequencies in the audible range. The controller includes a first circuit for generating an ON time current source having a magnitude related to an amplified error signal and the monitored input voltage, and a second circuit for generating an OFF time current source having a magnitude related to the ON time current source, the monitored input voltage, and the monitored output voltage. Gate drive circuitry provides gate drives signals to the switches of the interleaved PFC converter at a frequency determined by magnitudes of the ON time current source and the OFF time current source. | 05-12-2011 |
| 20110110132 | TIME-LIMITING MODE (TLM) FOR AN INTERLEAVED POWER FACTOR CORRECTION (PFC) CONVERTER - The present invention provides a method of controlling an interleaved power factor correction (PFC) circuit operating in a discontinuous conduction mode (DCM). The controller employs a normal mode of operation in which inductor currents in each PFC sub-circuit are estimated based on the monitored input voltage and monitored output voltage, and switching devices associated with each PFC sub-circuit are controlled to ensure DCM operation. As the input voltage increases, the OFF times of each PFC sub-circuit increase such that the inductor currents no longer overlap. In response, the controller activates a time-limiting mode (TLM) in which OFF time durations for each sub-circuit are based on the monitored sum of load currents as opposed to the monitored input voltage and monitored output voltage. | 05-12-2011 |
| 20110058285 | OVER-CURRENT PROTECTION DEVICE FOR A SWITCHED-MODE POWER SUPPLY - An over-current protection device is employed to control switching associated with a switched mode power supply to prevent the excessive buildup of current. The device includes a function for relating the switching of the SMPS with a monitored output of the SMPS. This function is selectively modified to ensure the current associated with the SMPS does not exceed a maximum value and does not fall below a minimum value. | 03-10-2011 |
| 20110037069 | METHOD AND APPARATUS FOR VISUALLY DETERMINING ETCH DEPTH - Etch depth of a material in a semiconductor wafer may be determined by forming a production region and a test region of the wafer, the test region having a test pattern for determining etch depth on a the wafer. The semiconductor wafer is comprised of a base layer, an intermediate layer above and visually distinguishable from the base layer, and a mask of photoresist material formed atop the intermediate layer. The mask of photoresist material has an areal photoresist coverage that varies across a horizontal axis. When the wafer is etched, a visible boundary can be seen between a region where the intermediate layer has been entirely etched away, and a region where at least some of the intermediate layer remains. The horizontal position of this visible boundary corresponds to the vertical etch depth in the production region., after etching of the semiconductor wafer. | 02-17-2011 |
| 20110024803 | SEMICONDUCTOR DEVICE WITH INTEGRATED CHANNEL STOP AND BODY CONTACT - A channel stop is provided for a semiconductor device that includes at least one active region. The channel stop is configured to surround the semiconductor device, to abut the at least one active region at a periphery of the semiconductor device, and to share an electrical connection with the at least one active region. | 02-03-2011 |
| 20100320935 | CURRENT-REGULATED POWER SUPPLY WITH SOFT-START PROTECTION - A current-regulated power supply provides soft-start protection to prevent the generation of large in-rush currents. The current-regulated power supply includes a current regulation module that operates in either a soft-start mode of operation or a normal mode of operation and a mode selection module that makes mode of operation determinations. In particular, mode-selection module monitors the load current supplied to the attached load and maintains the current-regulation module in the soft-start mode of operation until the monitored load current exceeds a threshold value, at which time the mode-selection module causes the current regulation module to operate in the normal mode of operation. | 12-23-2010 |
| 20100295472 | Power supply for floating loads - A power supply includes a current supply, a plurality of output channels, and a controller. Each of the output channels has a load and a channel switch with a reference voltage. All of the channel switches are referenced to the same reference voltage. | 11-25-2010 |
| 20100283322 | Multiple output power supply - A method is provided for supplying power to multiple output channels. Channel control signals are monitored to determine a state for each of the output channels. Each channel control signal is associated with one of the output channels. The energy in a storage element is directed to output channels according to the state of the channel control signals. | 11-11-2010 |
| 20100270625 | METHOD OF FABRICATING HIGH-VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR DEVICES - A process of fabricating a transistor employs a relatively thicker sacrificial nitride layer that reduces the time and cost associated with chemical-mechanical polish (CMP) processes by reducing the topography associated with the transistor. The process includes forming the gate oxide region and a field oxide region on a substrate. A polysilicon layer is formed on the gate oxide region and the field oxide region. A sacrificial nitride layer is formed on the polysilicon layer, wherein the sacrificial nitride layer has a thickness approximately equal to or greater than a thickness of the gate oxide region. A polysilicon gate is formed by selectively removing portions of the polysilicon layer and the sacrificial layer to expose a portion of the gate oxide region adjacent to the polysilicon gate. Source/drain regions are formed adjacent to the polysilicon gate using lightly-doped drain (LDD) implantation. A spacer layer is formed over the polysilicon gate and source/drain regions. Portions of the spacer layer are selectively removed, along with the sacrificial nitride layer and the gate oxide region to form sidewall spacers at each end of the polysilicon gate. A pre-metal dielectric layer is formed on the high-voltage MOS transistor, and the pre-metal dielectric layer is planarized. | 10-28-2010 |
| 20100252905 | LOCOS NITRIDE CAPPING OF DEEP TRENCH POLYSILICON FILL - A polysilicon-filled isolation trench in a substrate is effective to isolate adjacent semiconductor devices from one another. A silicon nitride cap is provided to protect the polysilicon in the isolation trench from subsequent field oxidation. The cap has lateral boundaries that extend between the side boundaries of the polysilicon and the sidewalls of the trench. Subsequent field oxide regions formed adjacent to the trench establish a gap dimension from the substrate to a top surface of the field oxide regions adjacent to the polysilicon side boundaries that is no less than half of the field oxide thickness. | 10-07-2010 |
| 20100202169 | Protection and clamp circuit for power factor correction controller - A controller generates a drive signal for a converter circuit that includes an active component (i.e., transistor) that is selectively controlled to convert a rectified input to direct current (DC) output. The controller employs an outer feedback loop (based on monitored output voltage of the converter circuit), an inner feedback loop (based on monitored AC input current drawn by the converter circuit), and a pulse width modulator (PWM) to generate the drive signals necessary to generate the desired DC output voltage and to provide power factor correction to the converter circuit. In particular, the inner feedback loop includes an amplifier and a fault protection and clamp circuit. The amplifier has a first input connected to receive a feedback signal representing the monitored AC input current, a second input, and an output that provides a current feedback signal to the PWM. The fault protection and clamp circuit is connected to monitor the voltage at the second input of the PWM and to detect fault conditions associated with the converter circuit, wherein in response to an over-voltage condition at the second input or a detected fault condition the fault protection and claim circuit clamps the current feedback signal provided to the second input of the PWM to a reference value and provides the reference value in feedback to either the first or second input of the amplifier. | 08-12-2010 |
| 20090231770 | Current-mode under voltage lockout circuit - A current-mode under voltage lockout (UVLO) circuit provides an output signal that indicates to connected devices whether a connected power supply is sufficient (i.e., of sufficient strength and stability) based on a comparison of a current that is proportional to the power supply and a reference current. The current-based UVLO circuit employs a reference current generator that is capable of providing a stable reference current and a voltage-to-current converter that provides a current proportional to the power supply voltage. A comparator compares the reference current to the current proportional to the power supply voltage and determines based on the magnitudes of the two currents whether the power supply voltage is sufficient or ‘good’ and generates an output signal indicating the status of the power supply voltage. | 09-17-2009 |
| 20080266738 | Over-current protection device for a switched-mode power supply - An over-current protection device for use in a switched mode power supply prevents over-current conditions caused by short-circuits faults. The over-current protection device monitors a current in the switched mode power supply, and in particular, determines a peak current value associated with the monitored current. The monitored current is compared to a reference value to determine whether an over-current condition exists. If an over-current condition is detected, then the over-current protection device modifies the ‘off’ time of the switched mode power supply based on the determined peak current value. | 10-30-2008 |
