PMC-SIERRA US, INC. Patent applications |
Patent application number | Title | Published |
20140281828 | SYSTEM AND METHOD FOR ACCUMULATING SOFT INFORMATION IN LDPC DECODING - A system and method reading, accumulating and processing soft information for use in LDPC decoding. In accordance with the present invention, an LDPC decoder includes accumulation circuitry to receive soft reads of a cell of the nonvolatile memory storage module and to produce an accumulated soft read that can be used to identify an appropriate LLR for the cell. The accumulation circuitry of the present invention may include, an accumulation RAM, an arithmetic logic unit (ALU) and a soft accumulation control and sequencing module for accumulating and processing soft information for use in LDPC decoding. | 09-18-2014 |
20140281823 | SYSTEM AND METHOD WITH REFERENCE VOLTAGE PARTITIONING FOR LOW DENSITY PARITY CHECK DECODING - A nonvolatile memory storage controller for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes partitioning circuitry for identifying a set of soft-decision reference voltages having the smallest calculated introduced error value based upon the estimated BER of the nonvolatile memory. The controller further includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using the set of soft-decision reference voltages having the smallest calculated LLR introduced error value to provide a plurality of soft-decision bits representative of the codeword. The controller further includes an LLR look-up table accessible by the read circuitry to provide LLRs to the LDPC decoder for the subsequent decoding of the codeword. | 09-18-2014 |
20140281800 | SYSTEM AND METHOD FOR HIGHER QUALITY LOG LIKELIHOOD RATIOS IN LDPC DECODING - A nonvolatile memory storage controller is provided for delivering log likelihood ratios (LLRs) to a low-density parity check (LDPC) decoder for use in the decoding of an LDPC encoded codeword. The controller includes read circuitry for reading an LDPC encoded codeword stored in a nonvolatile memory storage module using a plurality of soft-decision reference voltages to provide a plurality of soft-decision bits representative of the codeword. The controller further includes a plurality of neighboring cell contribution LLR look-up tables representative of the contribution of the neighboring cells to threshold voltage distribution of the memory storage module. The controller provides the LLRs from the appropriate LLR look-up table to an LDPC decoder for the subsequent decoding of the codeword. | 09-18-2014 |
20140281762 | SYSTEM AND METHOD FOR RANDOM NOISE GENERATION - A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module. | 09-18-2014 |
20140133544 | COMPENSATION FACTOR REDUCTION IN AN UNROLLED DECISION FEEDBACK EQUALIZER - An unrolled decision feedback equalizer (DFE) as disclosed herein has a reduced number of compensation factors while keeping a suitable performance level for a given application. The K | 05-15-2014 |
20140095737 | METHOD AND APPARATUS FOR A MULTI-ENGINE DESCRIPTOR CONTROLLER - A method and apparatus, such as multi-engine controller that can be used to control multiple data processing engines in a command based IO processing system, such as a storage controller, to solve to the problem of scaling the data processing rate to match the advances in the IO interface data rates, including a method of identifying dependencies among various tasks queued up in the system and scheduling tasks out-of-order to avoid head of line blocking, a method to buffer and reorder the completed tasks such that the task output order is the same as that in the input to the system. | 04-03-2014 |
20140001601 | METHOD OF REDUCING CURRENT LEAKAGE IN A DEVICE AND A DEVICE THEREBY FORMED | 01-02-2014 |
20130104007 | CYCLICALLY INTERLEAVED DUAL BCH, WITH SIMULTANEOUS DECODE AND PER-CODEWORD MAXIMUM LIKELIHOOD RECONCILIATION - A method and system are provided for forward error correction. Embodiments of the present disclosure provide a strong FEC algorithm that performs similarly to RS(255, 239) when a simple decoder is used, and scales up linearly to a full-scale decoder that outperforms all 7% algorithms currently in G.975.1. The Forward Error Correction code is suitable for use in optical transport networks (OTN) and other applications requiring high decode performance and high code rate. Embodiments of the present disclosure provide an FEC code that is a cyclically interleaved dual BCH, with simultaneous decode and per-codeword maximum likelihood reconciliation. | 04-25-2013 |