| 20090033353 | SYSTEMS AND METHODS FOR ELECTRICAL CHARACTERIZATION OF INTER-LAYER ALIGNMENT - Systems and methods for electrical characterization of inter-layer alignment. In one embodiment, a wafer including a plurality of test structures are accessed. The plurality of test structures include chains of conductive segments on multiple layers, coupled by vias. The plurality of test structures are designed with varying amounts of intentional misalignment between the multiple layers. The reactance of each of the plurality of test structures is measured. The reactance is analyzed to determine the process-induced inter-layer misalignment of the integrated circuit wafer. | 02-05-2009 |
