Patrenella Capital Ltd., LLC Patent applications |
Patent application number | Title | Published |
20090231929 | MEMORY AND CONTROL UNIT - A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data. | 09-17-2009 |
20090231904 | FERROELECTRIC MEMORY WITH SUB BIT-LINES CONNECTED TO EACH OTHER AND TO FIXED POTENTIALS - A memory capable of suppressing increase of a chip area thereof while preventing nonselected subarrays from disturbance is obtained. This memory comprises a first transistor for connecting respective sub bit lines with each other, and connects the sub bit lines of the nonselected subarrays with each other through the first transistor and connects the same to fixed potentials arranged on both ends of a memory cell array at least in a read operation. | 09-17-2009 |