| OptimalTest Ltd. Patent applications |
| Patent application number | Title | Published |
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| 20120123734 | MISALIGNMENT INDICATION DECISION SYSTEM AND METHOD - Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers. | 05-17-2012 |
| 20120109874 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING A TESTING SCENARIO LANGUAGE - Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs. | 05-03-2012 |
| 20110251812 | SYSTEM AND METHODS FOR PARAMETRIC TESTING - Methods, systems, computer program products and program storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test range. One of the methods comprises: attaining results generated from a parametric test performed on semiconductor devices included in a control set comprising a subset of a population of semiconductor devices; selecting from among the semiconductor devices at least one extreme subset including at least one of a high-scoring subset including all devices whose results exceed a high cut-off point and a low-scoring subset including all devices whose results fall below a low cut-off point; plotting at least results of the at least one extreme subset as a normal probability plot located between a zero probability axis and a one probability axis; fitting a plurality of curves to a plurality of subsets of the results of the at least one extreme subset respectively; extending each of the plurality of curves to the zero probability axis for the low-scoring subset or to the one probability axis for the high scoring subset thereby to define a corresponding plurality of intersection points along the zero or one probability axis; defining an estimated maximum test range based on at least one of the intersection points; and determining whether or not to perform an action based at least partly on the estimated maximum test range. | 10-13-2011 |
| 20110224938 | SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner. | 09-15-2011 |
| 20110000829 | SYSTEM AND METHOD FOR BINNING AT FINAL TEST - Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program. | 01-06-2011 |
| 20100161276 | System and Methods for Parametric Test Time Reduction - A parametric test time reduction method for reducing time expended to conduct a test program flow on a population of semiconductor devices, the test program flow comprising at least one parametric test having a specification which defines a known pass value range characterized in that a result of the test is considered a passing result if the result falls within the known pass value range, the method comprising, for at least one parametric test, computing an estimated maximum test range, at a given confidence level, on a validation set comprising a subset of the population of semiconductor devices, the estimated maximum test range comprising the range of values into which all results from performing the test on the set will statistically fall at the given confidence level, the validation set defining a complementary set including all semiconductors included in the population and not included in the validation set; and at least partly disabling the at least one parametric test based at least partly on a comparison of the estimated maximum test range and the known pass value range. | 06-24-2010 |
| 20090265300 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING A TESTING SCENARIO LANGUAGE - Methods and systems for semiconductor testing. In one embodiment, a semiconductor testing method includes one or more of the following stages: defining a rule relating to semiconductor testing, validating the rule, bundling the rule with other rules, correlating the rule with other rules, publishing the rule, actualizing the rule, and follow up relating to the rule. In one embodiment, a semiconductor testing system includes one or more of the following modules: rule creation module(s), analysis module(s), simulation module(s), real time production module(s), and offline production module(s). In one embodiment, user friendly graphical user interface(s) can be used for defining the building blocks of a rule and/or for viewing an optional hierarchy of categories to which the rule belongs. | 10-22-2009 |
| 20090192754 | SYSTEMS AND METHODS FOR TEST TIME OUTLIER DETECTION AND CORRECTION IN INTEGRATED CIRCUIT TESTING - Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner. | 07-30-2009 |
| 20090119048 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted. | 05-07-2009 |
| 20090115445 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted. | 05-07-2009 |
| 20090112501 | METHODS AND SYSTEMS FOR SEMICONDUCTOR TESTING USING REFERENCE DICE - Methods and systems of semiconductor testing where reference dice and non-reference dice in a wafer and/or lot are tested differently. In one embodiment of the invention, geography, lithography exposure, other characteristics, performance and/or behavior are taken into account when selecting reference dice, thereby improving the likelihood that the response of reference dice to testing is well representative of the wafer and/or lot. In one embodiment, based on data from the testing of reference dice, the test flow for non-reference dice and/or other testing may or may not be adjusted. | 04-30-2009 |
