ON-CHIP TECHNOLOGIES, INC.
|ON-CHIP TECHNOLOGIES, INC. Patent applications|
|Patent application number||Title||Published|
|20090316506||Serially Decoded Digital Device Testing - Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices.||12-24-2009|
Patent applications by ON-CHIP TECHNOLOGIES, INC.