OKI SEMICONDUCTOR CO., LTD. Patent applications |
Patent application number | Title | Published |
20130185575 | SEMICONDUCTOR DEVICE FOR SUPPLYING POWER SUPPLY VOLTAGE TO SEMICONDUCTOR DEVICE - A semiconductor device includes first, second and third power supply terminals respectively supplied with first, second and third power supply voltages. The semiconductor device also includes a first terminal connectable to a host device and a second terminal connectable to a peripheral device. The semiconductor device also includes a first circuit block connected to the first terminal and the first power supply terminal and receiving data output from the host device based on the first power supply voltage, a second circuit block connected to the second terminal and the third power supply terminal and receiving data output from the peripheral device based on the third power supply voltage, and a third circuit block connected to the second power supply terminal and controlling operation of the first circuit block and the second circuit block based on the second power supply voltage. | 07-18-2013 |
20120286926 | WIRELESS KEY SYSTEM AND KEY LOCATION DETERMINATION METHOD - A wireless key system and location detection method determine whether a wireless key is located inside or outside a main body. A communication device in the main body transmits a wireless signal using an inner antenna and an outer antenna outside the main body having a different directivity. A wireless key measures direction of movement of the wireless key when the wireless signal is received by one of antennas having different directivities, detects one of the antennas receiving the highest signal level of the wireless signal as a first antenna, selects one of the antennas having the same directivity as the inner antenna as a second antenna according to the measured direction of movement and detected directivity of the antenna, and decides that the wireless key is inside the main body based on the signal levels of the wireless signals received by the first and second antennas. | 11-15-2012 |
20120175787 | SEMICONDUCTOR PACKAGE - A semiconductor package including a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads. | 07-12-2012 |
20120146233 | SEMICONDUCTOR DEVICE AND SUBSTRATE - A semiconductor device of the invention include a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element comprises, a plurality of first electrodes formed along a first edge of a surface thereof, a plurality of second electrodes formed along an edge opposite to the first edge of the surface, a plurality of third electrodes formed in the neighborhood of a functional block, and an internal wiring for connecting the first electrodes and the third electrodes. The substrate comprises, a first wiring pattern for connecting the external input terminal and the first electrodes, a second wiring pattern for connecting the external output terminal and the second electrodes, and a third wiring pattern for connecting the first electrodes and the third electrodes. | 06-14-2012 |
20120133040 | SEMICONDUCTOR CHIP AND SOLAR SYSTEM - There is provided a semiconductor chip having four sides and being substantially formed in a rectangle, the semiconductor chip including: a first terminal which is located along one side of the four sides of the semiconductor chip and which is to be electrically connected to a solar cell outside the semiconductor chip; a second terminal which is located along the one side of the semiconductor chip and which is to be electrically connected to a secondary cell outside the semiconductor chip; and an interconnection line that electrically interconnects the first terminal and the second terminal. | 05-31-2012 |
20120092938 | SEMICONDUCTOR MEMORY - Semiconductor memory including a reference amplifier and a high-speed start-up circuit having four FETs. The reference amplifier supplies the reference voltage to a sense amplifier via a reference voltage supply line. The high-speed startup circuit has four FETs. The first FET is turned on to apply a first voltage onto a first line when the enable signal indicates deactivation. The second FET is turned on to apply ground potential onto the first line when the voltage on the reference voltage supply line is higher than a gate threshold voltage value. The third FET is turned on to generate the first voltage when the enable signal indicates activation. The fourth FET is turned off when the first line is at ground potential and is turned on to supply the first voltage from the third FET onto the reference voltage supply line when the first voltage is applied onto the first line. | 04-19-2012 |
20120086697 | DRIVING DEVICE OF DISPLAY DEVICE - There is provided a driving device of a display device, including: a first switching portion; a second switching portion; and a control section that, when the potential of a drive signal line is lower than a target potential, operates the first switching portion by using, as a first reference potential, a potential that is less than or equal to the target potential and that is closest to the target potential, among predetermined n types (n≧1) of potentials, and, when the potential of the drive signal line is higher than the target potential, operates the second switching portion by using, as a second reference potential, a potential that is greater than or equal to the target potential and that is closest to the target potential, among the n types of potentials. | 04-12-2012 |
20120081349 | DISPLAY PANEL DRIVING DEVICE - A display panel driving device has a signal line driver. The signal line driver applies a pixel driving voltage based on an input image signal to each signal line of a display panel at a timing corresponding to a clock signal. The signal line driver is divided into a plurality of driver chips connected in cascade by the clock line. The display panel driving device supplies a clock signal through the driver chips. The duty ratio of the clock signal is stabilized when the clock signal passes through the driver chips, without leading to an increase in power consumption and in manufacturing costs. | 04-05-2012 |
20120081167 | SEMICONDUCTOR DEVICE, AND METHOD OF DIAGNOSING ABNORMALITY OF BOOSTING CIRCUIT OF SEMICONDUCTOR DEVICE - The battery monitoring IC is provided with the short circuiting switch that includes the switching element that shorts the input side and the output side of the boosting circuit that boosts the power supply voltage to the driving voltage, that can drive the MOS transistor within the buffer amplifier in the saturated region, and supplies the driving voltage as the driving voltage of the buffer amplifier. An abnormality of the boosting circuit can be diagnosed by comparing the output voltage, that is measured when the short circuiting switch is turned off and the driving voltage boosted by the boosting circuit is supplied to the buffer amplifier, and the output voltage, that is measured when the short circuiting switch is turned on and the power supply voltage is, without going through the boosting circuit, supplied as is to the buffer amplifier. | 04-05-2012 |
20120081151 | DELAY CIRCUIT AND INVERTER FOR SEMICONDUCTOR INTEGRATED DEVICE - An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential. | 04-05-2012 |
20120069483 | PROTECTION DEVICE, COMPLEMENTARY PROTECTION DEVICE, SIGNAL OUTPUT DEVICE, LATCH-UP PREVENTING METHOD, AND COMPUTER-READABLE MEDIUM - A protection device includes: a serial element unit that includes a first switching element and a resistive element, one end being connected to a control terminal of a protection-target switching element, the other end being connected to a first voltage line, the protection-target switching element including a first terminal connected to the first voltage line, a second terminal connected to a second voltage line and an inductor unit, and the control terminal, the protection-target switching element switching a conduction state at the normal time to a non-conduction state between the first terminal and the second terminal when an off-voltage is applied to the control terminal; a capacitance provided at the protection-target switching element and has a predetermined capacitance value; and a controller that performs control such that the first switching element is in a conduction state if the protection-target switching element is put into a non-conduction state. | 03-22-2012 |
20120069058 | OFFSET CANCEL OUTPUT CIRCUIT OF SOURCE DRIVER FOR DRIVING LIQUID CRYSTAL DISPLAY - An offset cancel output circuit of source drivers for driving liquid crystal displays which is capable of appropriately cancelling out an offset voltage from an output amplifier to thereby prevent degradation in display quality. The offset cancel output circuit includes an operational amplifier with a non-inverted input port to which a reference voltage is applied, and an input capacitor and an output capacitor with each one end thereof connected to an inverted input port of the operational amplifier. The offset cancel output circuit further includes a switching element circuit which has a first field effect transistor connected between the inverted input port and an output port of the operational amplifier and controlled to turn on during a reset operation. During the reset operation and the normal output operation, a first potential equal to the reference voltage is applied to the substrate of the first field effect transistor. | 03-22-2012 |
20120068764 | SIGNAL AMPLIFIER, BRIDGE CONNECTION SIGNAL AMPLIFIER SIGNAL OUTPUT DEVICE, LATCH-UP PREVENTION METHOD, AND PROGRAM STORAGE MEDIUM - A signal amplifier includes an inverting amplification circuit, a first switching element, a second switching element, and a control section. The inverting amplification circuit includes a first voltage terminal, a second voltage terminal, an inverting input terminal, an output terminal, a first protected switching element, and a second protected switching element. The control section controls such that when an overcurrent has flowed in the first voltage line, the first and second protected switching elements are switched to a non-conducting state after switching the first switching element in a conducting state and switching the second switching element in a non-conducting state, and when an overcurrent has flowed in the second voltage line, the first the second protected switching elements are switched to a non-conducting state after switching the first switching element in a non-conducting state and switching the second switching element in a conducting state. | 03-22-2012 |
20120056578 | CHARGING APPARATUS - A charging device can prevent overcharging by coping with a plurality of cell voltages without increasing a circuit area and current consumption. The charging device selects one of at least two judgment voltages in response to a select signal determined depending on a chargeable voltage of a secondary battery. The charging device compares a comparison voltage based on a voltage of a lower stream of a back flow prevention unit with the selected judgment voltage to detect a fully charged state of the secondary battery. The charging device interrupts supply of charging current to the back flow prevention unit upon detecting the fully charged state. | 03-08-2012 |
20120046761 | INFORMATION PROCESSING DEVICE, COMMUNICATION SYSTEM, AND INFORMATION PROCESSING METHOD - An information processing device includes: a receiving unit that receives information to be processed that includes valid data, that has processing content information and identification information, and start information; and a control unit that controls an apparatus such that an initial processing is executed on the basis of the processing content information, and, if the identification information is included in the information to be processed, controls the apparatus such that processing that follows the initial processing is executed, and, if the identification information is not included in the information to be processed, controls the apparatus such that the processing that follows the initial processing is not executed. | 02-23-2012 |
20120045025 | DIVERSITY RECEPTION DEVICE AND DIVERSITY RECEPTION METHOD - A diversity reception device includes branches, a controller and a combining section. Each branch includes a correlation section that generates a correlation signal that represents a correlation between a received signal and a delayed signal or between the received signal and a reference signal, where the correlation signal level disregarding the received signal level, a time position detector that detects time positions at which the level of the correlation signal is at a peak, a demodulation section that demodulates the received signal, and a multiplication section that multiplies the demodulated signal with a weighting factor. The controller controls the weighting factor on the basis of the respective levels of the correlation signals at the detected time positions. The combining section combines, by adding, the respective demodulated signals of the branches subsequent to the demodulated signal of each branch being multiplied with the weighting factor. | 02-23-2012 |
20120045004 | CORRELATOR AND DEMODULATION DEVICE INCLUDING THE CORRELATOR - The Present invention provides a correlator including, a read-out processing circuit that reads out an OFDM signal in RAM as 2n−1 number of delay OFDM signals that are increased and delayed sequentially with their adjusted read-out timings. Complex conjugate circuits that outputs complex conjugates of the inputted n | 02-23-2012 |
20120037963 | SEMICONDUCTOR DEVICE WITH PROTECTIVE FILMS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate having a drain region, a source region and an impurity diffusion region; an oxide film formed on the impurity diffusion region; a first protective film including a SiN film as a principle component and being formed on the oxide film; and a second protective film containing carbon and being formed on the first protective film. A method of manufacturing the semiconductor device, includes doping an impurity into a semiconductor substrate, thereby forming a drain region, a source region and an impurity diffusion region; forming an oxide film on the impurity diffusion region; forming a first protective film including a SiN film as a principle component on the oxide film; and forming a second protective film containing carbon on the first protective film. | 02-16-2012 |
20120032338 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed is a semiconductor device which includes a base substrate; a lower electrode formed on a main surface of the base substrate; and an insulating film formed over the lower electrode and the main surface of the base substrate. The insulating film has a contact hole defined by a wall extending upwardly from the top surface of the lower electrode. The insulating film has a film density distribution in which a film density decreases with increasing distance from the main surface of the base substrate in the thickness direction. A width of the contact hole increases as the film density decreases. | 02-09-2012 |
20120025912 | DIFFERENTIAL AMPLIFIER CIRCUIT - A differential amplifier circuit can reduce consumption current and the circuit size while improving a power supply rejection ratio. The differential amplifier circuit includes a power supply line and an input part that includes an input circuit and an active load. The input circuit includes two differential input elements, and the active load includes two transistors connected to the two differential input elements. The input part generates a differential signal in response to an input signal given to the two differential input elements. The differential amplifier circuit also includes an amplifying part for generating an output voltage generating signal by amplifying the differential signal. The differential amplifier circuit also includes an output part for generating an output voltage based on the output voltage generating signal and a power supply voltage. The differential amplifier circuit includes a noise permitting part located between control terminals of the two transistors and the power supply line. | 02-02-2012 |
20120020174 | ASYNCHRONOUS SEMICONDUCTOR MEMORY CAPABLE OF PREVENTING COUPLING NOISE - Disclosed herein is a semiconductor memory which is capable of performing data reading without a faulty operation irrespective of the span of an address skew period. In detecting whether an address transition has been made and precharging a bit line formed in a memory cell array when a certain delay period has elapsed after the address transition is detected, the delay period is adjusted based on a delay period extension signal. | 01-26-2012 |
20120014178 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF REUSING SAME - A nonvolatile semiconductor memory device and a method of reusing the same that allow a good use of the semiconductor device without degrading characteristics even when reused. The semiconductor memory device comprises information holding means for holding information that indicates an operation mode of said memory cell array, a decoder for generating, to said memory cell array, a selection signal to designate at least a read address of said memory cell array in accordance with an address signal that comprises plural bits; and mode setting means for fixing a logical value of at least one bit of said plural bits of said address signal in accordance with the information held by said information holding means, and supplying said address signal, on which fixing of the logical value is effected, to said decoder. | 01-19-2012 |
20120013375 | FREQUENCY SYNTHESIZER DEVICE AND MODULATION FREQUENCY DISPLACEMENT ADJUSTMENT METHOD - A frequency synthesizer device that includes two modulation paths and suitably adjusts the amplitude of a control voltage that is outputted from a digital-to-analog converter (DAC) to a voltage-controlled oscillator. The frequency synthesizer device is provided with a voltage-controlled oscillator, a programmable frequency divider, a frequency phase comparator, a DAC, a switch and a modulation frequency displacement correction circuit. The voltage-controlled oscillator oscillates at an oscillation frequency depending on an input voltage. The programmable frequency divider frequency-divides a signal from the voltage-controlled oscillator. The frequency phase comparator outputs a phase difference between the frequency-divided signal and a reference clock. The DAC outputs an adjustment voltage. The switch connects the voltage-controlled oscillator to a reference voltage power source at a time of correction of the adjustment voltage. The modulation frequency displacement correction circuit specifies adjustment data that corresponds to the adjustment voltage corresponding to the target frequency displacement. | 01-19-2012 |
20120002936 | IMAGE PROCESSING SYSTEM AND STORAGE MEDIUM IN WHICH IMAGE PROCESSING PROGRAM IS STORED - An image processing system is provided. A region specifying component specifies one or more playing regions for generating predetermined sounds in an image represented by the moving image data that have been acquired by the acquiring component. A detecting component detects a specific image showing a specific subject existing in the image represented by the moving image data that have been acquired by the acquiring component. An assigning component assigns, for each of the playing regions that have been specified by the region specifying component, sounds to be outputted in a case where the specific image that has been detected by the detecting component overlaps those playing regions. A signal outputting component outputs signals representing the sounds that have been assigned to those playing regions by the assigning component, in a case where the specific image overlaps the playing regions. | 01-05-2012 |
20120001952 | DRIVING CIRCUIT AND DISPLAY APPARATUS - A driving circuit includes a pair of operational amplifiers, one producing an analog voltage output of positive polarity, the other producing an analog voltage output of negative polarity. An output switching circuit interchanges these outputs between a pair of data lines. One or both of the operational amplifiers includes a parasitic diode having one terminal connected to the output terminal of the operational amplifier and another terminal normally connected to a power supply voltage of the operational amplifier. When the output of the operational amplifier is switched, a protective switching circuit temporarily disconnects the parasitic diode from the power supply of the operational amplifier and instead connects it to a power supply line carrying a voltage high enough, or low enough, to ensure that the parasitic diode is not forward biased by the existing voltage on the data line to which the output is switched. | 01-05-2012 |
20120001588 | BATTERY CHARGER, VOLTAGE MONITORING DEVICE AND SELF-DIAGNOSIS METHOD OF REFERENCE VOLTAGE CIRCUIT - Disclosed is a battery charger including a battery cell, a reference voltage generating section, an A/D converting section including an A/D converter and a control section. The reference voltage generating section includes a first reference voltage circuit generating a first reference voltage and a second reference voltage circuit generating a second reference voltage equal to the first reference voltage. To diagnose the A/D converter, the first reference voltage circuit is used. To diagnose the first reference voltage circuit, a second A/D conversion value obtained by A/D converting a second divided voltage of the second reference voltage via the A/D converter using the first reference voltage is compared with a first reference value obtained by A/D converting a first divided voltage of the first reference voltage via the A/D converter using the first reference voltage when the first reference voltage circuit is normal. | 01-05-2012 |
20110320988 | LAYOUT PATTERN GENERATING APPARATUS AND LAYOUT PATTERN GENERATING METHOD - An apparatus for generating a layout pattern of each element includes a storage, a basic figure generator, an additional figure generator, a display unit and an operation input unit; wherein the storage stores terminal figure relative position information, figure adjustment value information and additional figure relative position information; the basic figure generator generates an effective area figure and a terminal figure of a layout pattern generation target element on the basis of the terminal figure relative position information and the figure adjustment value information; the additional figure generator generates the additional figure of the layout pattern generation target element on the basis of the generated effective area figure and terminal figure and the additional figure relative position information; the display unit displays the generated effective area figure, terminal figure and additional figure; and the figure adjustment value information is changed depending on an input from the operation input unit. | 12-29-2011 |
20110320853 | COMMUNICATION INTERFACE DEVICE AND COMMUNICATION METHOD - A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal | 12-29-2011 |
20110317498 | NON-VOLATILE STORAGE DEVICE - There is provided a non-volatile storage device including: a memory array section arrayed with plural non-volatile memory cells for electronically writable data storage; plural bit lines that are connected to respective memory cells and have voltage levels that change according to the data stored in the memory cells; a supply section that supplies a voltage of a reference level to act as a comparator reference when determining data stored in the memory cells; a comparator section that compares the voltage level of the bit line connected to the memory cell subject to reading against the reference level supplied by the supply section; and a charging section that, in preparation for comparison by the comparator section, charges the bit line connected to the memory cell subject to reading to the voltage of the reference level supplied by the supply section. | 12-29-2011 |
20110317490 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory can reduce variations in an amount of current during data writing operation. This allows for the writing of data to memory cells with high precision. The nonvolatile semiconductor memory includes a plurality of memory cells, word lines connected to the memory cells, and bit lines connected to each of the memory cells. At least two of the bit lines are selected, and a current is simultaneously supplied from a power supply line to those memory cells which are connected to the selected bit lines in order to write data thereto. The nonvolatile semiconductor memory also includes charge amount measurement units for measuring respective amounts of charge stored in the memory cells. The nonvolatile semiconductor memory also includes current path switching circuits connected to the respective bit lines. Those current path switching circuits which are connected to the selected bit lines supply a current from the power supply line to the memory cells or a predetermined terminal depending on a measured value of the amount of charge measured by the charge amount measurement section. | 12-29-2011 |
20110316581 | SEMICONDUCTOR DEVICE WITH BUS CONNECTION CIRCUIT AND METHOD OF MAKING BUS CONNECTION - A semiconductor device capable of achieving desirable communication behavior through a bus regardless of whether or not a pull-up resistor is connected on a bus line. The semiconductor device includes external pull-up determination unit and internal pull-up setting unit. The external pull-up determination unit applies a pull-down voltage through an internal pull-down resistor to the bus line, and determines whether an external pull-up resistor external to the semiconductor device is connected on the bus line on the basis of the voltage level of the bus line when the pull-down voltage is applied to the bus line. The internal pull-up setting unit stops application of the pull-down voltage, and applies a pull-up voltage through an internal pull-up resistor to the bus line if it is determined that no external pull-up resistor is connected on the bus line. The internal pull-up setting unit stops application of the pull-down voltage if it is determined that the external pull-up resistor is connected on the bus line. | 12-29-2011 |
20110315555 | PLATING METHOD - Disclosed is a plating method including: performing plating on a plating surface of a plating substrate with a cathode electrode contacting an area in an outer circumferential section of the plating substrate where the cathode electrode is to be contacted, the plating substrate being provided with a dummy plating area between the area where the cathode electrode is to be contacted and a product area on the plating surface of the plating substrate, by supplying a plating solution to the plating surface of the plating substrate and applying electric current between the cathode electrode and an anode electrode via the plating solution. | 12-29-2011 |
20110314234 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE - An MCP type semiconductor memory device having a defective cell remedy function, which enables easy design and manufacture while minimizing chip area increase, is provided. The semiconductor memory device includes memory chips and a memory controller chip that designates an address of a memory chip according to an access request received from outside and controls access to the designated address. Each memory chip includes first and second storage regions and an information holder that holds address information representing associations between addresses in the first and second storage regions. The memory controller chip includes an address translating part that performs, upon receiving a request to access a specific address in the first storage region indicated by the address information, address designation by translating the specific address in the first storage region to an address in the second storage region corresponding to the specific address based on the associations represented by the address information. | 12-22-2011 |
20110311130 | IMAGE PROCESSING APPARATUS, METHOD, PROGRAM, AND RECORDING MEDIUM - Extracting information corresponding to a three-dimensional object from an image captured by plural imaging apparatuses is implemented with a simple configuration and a simple processing. | 12-22-2011 |
20110309525 | MULTI-CHIP PACKAGE SEMICONDUCTOR MEMORY DEVICE - An MCP type semiconductor memory device having a structure in which a stack memory chip including a plurality of stacked memory chips and a memory controller chip are juxtaposed on a substrate is provided, which achieves a reduction in package size. The semiconductor memory device includes a stack memory chip including a plurality of stacked memory chips, a substrate on which the stack memory chip is provided, and a memory controller chip provided adjacent to the stack memory chip on the substrate. The stack memory chip is constructed such that an upper memory chip is stacked so as to shift toward a mounting position of the memory controller chip relative to a memory chip immediately below the upper memory chip. At least a part of the memory controller chip is received within a space between the substrate and a part of the stack memory chip that protrudes toward the memory controller chip. | 12-22-2011 |
20110291869 | DETECTING DEVICE - A detecting device has: a detecting element to which a first constant voltage is applied; a resistance element connected to the detecting element; a switching element having a first terminal to the resistance element, a second terminal controlled to a second constant voltage lower than the first constant voltage, and a control terminal sets the first terminal and the second terminal in a conducting state; a control unit, according to a conducting/non-conducting state, controls voltage to the control terminal to maintain a potential difference between the detecting element and the resistance element; and an AD converter converting, into a digital value, a potential of a potential difference between the first constant voltage and the first terminal being voltage-divided at the detecting element and the resistance element to the detecting element, a first reference potential is the first constant voltage, and a second reference potential is voltage to the first terminal. | 12-01-2011 |
20110291760 | Folded cascode differential amplifier and semiconductor device - A folded cascode differential amplifier includes a high-voltage input stage and a low-voltage output stage. The input stage is formed from high-voltage MOS transistors, two of which constitute a differential pair. The output stage is formed from low-voltage MOS transistors, some of which constitute a current mirror circuit connected to the differential pair. The output stage also includes at least one transistor that amplifies a voltage produced in the current mirror circuit to generate an output voltage signal. The high-voltage MOS transistors have higher breakdown voltages than the low-voltage MOS transistors. Incorporation of both types of transistors into a single amplifier reduces the necessary number of transistors and the necessary number of bias voltages. | 12-01-2011 |
20110291665 | TIMER CIRCUIT - A timer circuit is provided with a comparator CMP | 12-01-2011 |
20110287585 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate—such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder. | 11-24-2011 |
20110285465 | OPERATIONAL AMPLIFIER HAVING A COMMON MODE FEEDBACK CIRCUIT PORTION - An operational amplifier that can suppress lowering of the current driving capability while performing a self adjustment of the common mode voltage is disclosed. A common mode voltage adjusting transistor and an auxiliary transistor are connected in parallel with a low-voltage side drive transistor of each of push-pull amplifying circuits that produce first and second amplified difference signals having different polarities in accordance with drive signals obtained by level-shifting a difference signal indicating a difference value of the levels of the first and second input signals by predetermined values. Current drive capabilities during a period of outputting said first and second amplified difference signals and a common mode voltage adjusting period respectively are increased by driving said auxiliary drive transistor by alternately using the drive signal obtained by level-shifting the difference signal and a common mode voltage adjusting signal. | 11-24-2011 |
20110267902 | Semiconductor device - A semiconductor device includes a drive circuit that outputs a drive signal to drive an external device; a voltage output circuit that outputs a first voltage and a second voltage that is larger than the first voltage; a selector that, when supplying a power supply voltage to the drive circuit, selects the first voltage and, when supplying a power supply voltage to an internal device, selects the second voltage; and a step-up circuit that, when the first voltage selected by the selector is input, boosts the first voltage to a third voltage and outputs the third voltage as the power supply voltage to the drive circuit and, when the second voltage selected by the selector is inputted, boosts the second voltage to a fourth voltage and outputs the fourth voltage as the power supply voltage to the internal device. | 11-03-2011 |
20110261627 | SEMICONDUCTOR NONVOLATILE MEMORY DEVICE - In a semiconductor nonvolatile memory device, nonvolatile memory cells are plurally arranged in a memory array portion. An output circuit outputs setting information selected from plural sets of setting information to generate reference currents with different current values. A reference current circuit generates a reference current with a current value according to the setting information outputted from the output circuit. An amplifier circuit compares a cell current outputted from a selected memory cell of the memory array portion with the reference current generated by the reference current circuit. | 10-27-2011 |
20110260770 | METHOD AND SEMICONDUCTOR DEVICE FOR MONITORING BATTERY VOLTAGES - A semiconductor device for monitoring batteries or cells connected in series has a selector switch that selects one of the batteries or cells and outputs voltages obtained from its positive and negative terminals. A pair of buffer amplifiers receives these voltages at high-impedance input terminals and output corresponding voltages to a level shifter. The level shifter generates an output voltage equal to the difference between the outputs of the buffer amplifiers. By preventing current flow between the selector switch and the level shifter, the buffer amplifiers reduce the output droop that occurs at the beginning of a voltage measurement, even if the semiconductor device is connected to the batteries or cells through a low-pass filter circuit with a comparatively large time constant. Measurement time is shortened accordingly. | 10-27-2011 |
20110255642 | RECEIVING APPARATUS, AND COMPUTER READABLE MEMORY MEDIUM THAT STORES A PROGRAM - Suitable gain control is achieved at low cost. | 10-20-2011 |
20110254616 | Boosting circuit of charge pump type and boosting method - A boosting circuit of charge pump type includes: charging portion for applying an input voltage to a first capacitor; double boosting portion for applying the input voltage to a second capacitor and applying a sum of the input voltage and a voltage across the first capacitor to an output capacitor in a first predetermined period after start of a boosting operation; and triple boosting portion for repeating in order, after end of the first predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor. | 10-20-2011 |
20110247211 | CIRCUIT BOARD WITH EMBEDDED COMPONENT AND METHOD OF MANUFACTURING SAME - A circuit board has an embedded electronic component such as an integrated circuit chip with a wafer level chip size package. A via hole extends through the electronic component. Another via hole extends through the substrate or prepreg on which the electronic component is mounted inside the circuit board. Conductors in the via holes enable a terminal on the surface of the electronic component to be electrically connected to a wiring pattern or another electronic component on the opposite side of the substrate or prepreg. Routing the connection through the electronic component itself saves space and reduces the length of the connection. | 10-13-2011 |
20110242714 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device of the invention can reduce a manufacturing cost and achieve size reduction without degrading performances. The semiconductor integrated circuit device includes an internal circuit and at least one input/output circuit. Each input/output circuit is adapted to feed an input signal from outside to the internal circuit and to output an output signal from the internal circuit to the outside. The semiconductor integrated circuit device also includes at least one first power source terminal. Each first power source terminal is associated with each input/output circuit for supplying a drive voltage to the internal circuit. The semiconductor integrated circuit device also includes at lease one second power source terminal. Each second power source terminal is associated with each input/output circuit for supplying a drive voltage to the associated input/output circuit. The semiconductor integrated circuit device also includes at least one common ground terminal. Each common ground terminal is associated with each input/output circuit for supplying a common ground voltage to the internal circuit and the associated input/output circuit. The first power source terminal, second power source terminal and common ground terminal for each input/output circuit are arranged next to each other to define a unit terminal group. | 10-06-2011 |
20110242084 | Source driver for liquid crystal display panel - A source driver for a liquid crystal display (LCD) panel in which during a first predetermined period immediately after polarity of a voltage according to image data is inverted, each column terminal of the LCD panel is shorted to a common line through an output terminal and a second switch element, a first output amplifying portion is set to a high impedance state, and an output signal of a second output amplifying portion is fed back to a differential amplifying portion through a third switch element. During a period after the first predetermined period and before inversion of polarity of a voltage according to the image data, an output signal of the first output amplifying portion is supplied to the output terminal without passing though a switch element, and is fed back to the differential amplifying portion through a fourth switch element. The output signal of the second output amplifying portion is fed back to the differential amplifying portion through the first and fourth switch elements. | 10-06-2011 |
20110241817 | CURRENT FUSE, SEMICONDUCTOR DEVICE, AND METHOD OF BLOWING A CURRENT FUSE - A current fuse includes: a fuse portion that is disposed on a substrate; and a conductive portion that is placed in an overlying layer above the fuse portion or an underlying layer between the substrate and the fuse portion, has the same potential as that of one portion of the fuse portion when a current is passed through the fuse portion, and extends apart from the fuse portion from the one portion side of the fuse portion as far as an overlying layer above or an underlying layer below another portion of the fuse portion whose potential differs from that of the one portion. | 10-06-2011 |
20110241129 | TRANSISTOR, SEMICONDUCTOR DEVICE AND TRANSISTOR FABRICATION PROCESS - The present invention provides a transistor, a semiconductor device and a transistor fabrication process that thoroughly ameliorate electric fields in a transistor element. Namely, the transistor includes a semiconductor substrate, incline portions, a gate electrode, side walls, and a source and a drain. The semiconductor substrate includes a protrusion portion at a surface thereof. The incline portions constitute side surface portions of the protrusion portion and are inclined from the bottom to the top of the protrusion portion. The gate electrode is formed on the top of the protrusion portion, with a gate insulation film interposed therebelow. The side walls are formed on the top of the protrusion portion at two side surfaces of the gate electrode and the gate insulation film. The source and the drain each include a low density region and a high-density region. | 10-06-2011 |
20110234320 | VOLTAGE OUTPUT DEVICE HAVING AN OPERATIONAL AMPLIFIER - A voltage output device which is capable of preventing an increase in circuit scale and includes an offset compensation function that is suitably applicable in particular to a drive circuit for display devices such as liquid crystal display panels. The voltage output device includes an operational amplifier which has an inverting input terminal and a non-inverting input terminal. Resistance values of a load resistor on the inverting input side and a load resistor on the non-inverting input side are maintained when the output voltage of the amplifier has changed while sequentially varying either one or both of the resistance values of the load resistor on the inverting input side and the load resistor on the non-inverting input side in a state that the inverting input terminal and the non-inverting input terminal are connected. The voltage output device is configured to output the output voltage of the amplifier with the inverting input terminal not connected to the non-inverting input terminal. | 09-29-2011 |
20110232075 | Wafer holding apparatus and method - A wafer holding apparatus for holding a wafer in a semiconductor fabrication apparatus includes a stage having a wafer receiving area with a large number of apertures. A gas, supply source supplies gas to the apertures to levitate the wafer by gas pressure. The levitated wafer is held in contact with a retainer disposed above a peripheral part of the wafer receiving area by the gas pressure, which the retainer resists. The wafer is thereby held securely even when the stage is moved, and the surface configuration of the wafer is not affected by the presence of foreign matter between the wafer and stage. | 09-29-2011 |
20110223724 | Semiconductor device having low parasitic resistance and small junction leakage characteristic and method of manufacturing the same - A semiconductor device includes diffusion layers formed in a SOI layer under a side-wall, a channel formed between the diffusion layers, silicide layers sandwiching the diffusion layers wherein interface junctions between the diffusion layers and the silicide layers are (111) silicon planes. | 09-15-2011 |
20110216490 | Display panel - The present invention provides a display panel including: a first input terminal group in which input terminals are disposed at intervals along first long side of a rectangular driver IC facing a panel end portion; a second input terminal group in which input terminals are disposed at intervals along the second long side of the driver IC facing a display section; a first wiring group connected to the first input terminal group, that extends under the first short side of the driver IC and extends out from between the driver IC and the panel body; and a second wiring group connected to the second input terminal group, that passes under the second long side of the driver IC and extends out from between the driver IC and the panel body. | 09-08-2011 |
20110215853 | DATA TRANSFER CIRCUIT - A data transfer circuit includes primary data holding circuits that hold input data according to a first clock pulse signal and output data being held; and secondary data holding circuits that hold the output data of the primary data holding circuits according to a second clock pulse asynchronous to the first clock pulse and output data being held. Pulse signal generator generates a pulse signal synchronous with the second clock pulse signal when a pulse edge of the first clock pulse signal and a pulse edge of the second clock pulse signal occur at different timings and generates a pulse signal having the pulse edge the second clock pulse signal removed therefrom when the pulse edge of the the first clock pulse signal and the pulse edge of the the second clock pulse signal occur at the same timing. The secondary data holding circuits hold the output data of the primary data holding circuits synchronously with the pulse signal generated by the pulse signal generator. | 09-08-2011 |
20110215067 | ACCELERATION SENSOR WITH PROTRUSIONS FACING STOPPERS - An integrally micromachined acceleration sensor has a mass with a surface facing a stopper. At least one protrusion projects from this surface toward the stopper. In the absence of acceleration, the protrusion is spaced apart from the stopper, but by limiting motion of the mass toward the stopper, the protrusion improves the shock resistance of the acceleration sensor. The protrusion also prevents the mass from sticking to the stopper during the fabrication process. The stopper may have a pattern of holes surrounding the protrusion, so that the protrusion is produced naturally during the wet etching process that separates the mass from the stopper. The holes also shorten the wet etching time. | 09-08-2011 |
20110208899 | MEMORY WRITING SYSTEM AND METHOD - Memory writing system and method determining an optimum data amount per one-time data transmission to one memory writer to enable optimization of communication efficiency and write speed, include: setting the amount of data to be transmitted per one-time transmission from a writer controller to different values for respective memory writers; transmitting data of each of the data amounts from the writer controller to a corresponding one of the memory writers; measuring, for each of the data amounts, a processing time required for the writer controller to transmit data to the corresponding memory writer and a data write time of the corresponding memory writer; obtaining, for each of the data amounts, a correlation between the processing time and the data write time based on respective measured values; setting an optimum data amount based on the correlation to satisfy a desired data write time condition; and, after the optimum data amount is set, sequentially transmitting data of the optimum data amount from the writer controller to the memory writers. | 08-25-2011 |
20110208472 | Movement detection device, electronic device, movement detection method and computer readable medium - Tri-axial acceleration component data detected by a tri-axial acceleration sensor of acceleration acting on a movement detection device is split into respective stationary components obtained by low-pass filtering processing and movement components of the acceleration component data from which the respective stationary component has been removed. Which axial direction has been moved in is detected based on the split movement component expressing the maximum value. A shake duration is detected as a period of time from the point in time when this maximum movement component exceeded a threshold value expressing an upper limit value of a specific range up to once again becoming a value in the specific range after becoming less than a threshold value expressing a lower limit value, or as a period of time from the point in time when the movement component became less than the lower threshold value up to once again becoming a value in the specific range after exceeding the upper threshold value. The magnitude of movement is determined by whether or not the shake duration is a determination period or longer, or by whether or not the vector integral value over the shake duration is a determination threshold value or greater. | 08-25-2011 |
20110207290 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device fabrication method deposits a dielectric stress-canceling film on oxide films formed on the surfaces of a semiconductor substrate and its isolation trenches, and partly etches the dielectric stress-canceling film to leave a dielectric base film inside each trench and a dielectric top film outside each trench. The trenches are then filled with a dielectric layer that covers the dielectric top and base films, the upper part of this dielectric layer is removed to expose the dielectric top films, and the dielectric top films are selectively etched, using the trench-filling dielectric layer as an etching mask. In the resulting trench isolation structure, the trenches are completely filled with dielectric material, and stress exerted by the oxide films in the trenches during heat treatment is canceled by opposing stress exerted by the dielectric base films. | 08-25-2011 |
20110207278 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a method of fabricating a semiconductor device that includes both an enhancement-mode FET and a depletion-mode FET. The method includes forming an opening in a gate electrode for the depletion-mode FET. The opening is located in or in the vicinity of one of the overlapping regions in which the gate electrode extends over active regions. The method further includes ion-implanting dopant impurities into the active regions at an oblique angle using the gate electrode as a mask, thereby to form the doped region that is located under the opening and continuously extending from one of the opposite sides of the gate electrode to the other. | 08-25-2011 |
20110205815 | Decoder circuit of semiconductor storage device - The present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed. Namely, the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application MOS transistors for each of plural word lines, the voltage application MOS transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation, and applying a high voltage in a predetermined high voltage operation; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation, and that outputs the normal voltage or the high voltage in the high voltage operation, to the voltage application MOS transistor. | 08-25-2011 |
20110205778 | CURRENT DETECTION CIRCUIT FOR DETECTING READ CURRENT FROM A MEMORY CELL - A current detection circuit that can normally perform a current detection operation to detect a current in a memory cell of a memory device even if an applied power supply voltage is a low voltage, includes a current detection means which comprises first and second MOS transistors of a same channel type and third to sixth MOS transistors of a channel type different from the channel type of the first and second MOS transistors, and a MOS gate control means which supplies, to a control electrode of each of the first and second MOS transistors, a voltage which is obtained by subtracting an absolute value of a threshold voltage of each of the first and second MOS transistors from the power supply voltage when the power supply voltage is equal to or lower than the absolute value of the threshold voltage. | 08-25-2011 |
20110205776 | SEMICONDUCTOR STORAGE CIRCUIT - The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier. | 08-25-2011 |
20110205679 | Protection circuit and semiconductor device - A protection circuit | 08-25-2011 |
20110204481 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION - The present invention provides a semiconductor device including: a first resistance element formed of a first polysilicon layer that contains impurities; a second resistance element provided on a same surface as the first polysilicon layer, and formed of a second polysilicon layer that contains an equal amount of impurities to the first polysilicon layer; a first interlayer insulation film provided so as to cover the first resistance element and the second resistance element; and a first metal layer provided on the first interlayer insulation film so as to cover the second resistance element with the first interlayer insulation film disposed therebetween. | 08-25-2011 |
20110204451 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction. | 08-25-2011 |
20110204444 | Semiconductor intergrated device and method of manufacturing same - A semiconductor integrated device of the invention can enhance a radiation resistance. In an exemplary embodiment, the semiconductor integrated device includes a semiconductor supporting substrate, an insulation layer provided on the semiconductor supporting substrate, and a silicon thin film provided on the insulation layer. A predetermined region in the silicon thin film that is adjacent to the boundary between the insulation layer and the silicon thin film (i.e., boundary neighboring region) has an impurity-concentration-increased region. In this region, the impurity concentration becomes higher as the position approaches the boundary. | 08-25-2011 |
20110204423 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Disclosed is a semiconductor device that comprises a first semiconductor layer of one conductivity type provided on a substrate; a second semiconductor layer of the one conductivity type provided on the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer; an isolation region extending from one principal face of the second semiconductor layer to reach the substrate; a first region in an element region of the second semiconductor layer isolated by the isolation region and having an opposite conductivity type; a second region of the one conductivity type provided in the element region extending from the one principal face to reach the first semiconductor layer and having an impurity concentration higher than the second semiconductor layer; and an insulation region extending from the one principal face to the first semiconductor layer, kept away from the substrate, and provided between the first and the second regions. | 08-25-2011 |
20110201178 | SEMICONDUCTOR DEVICE AND PROCESS FOR FABRICATING THE SAME - A thin stacked semiconductor device has a plurality of circuits that are laminated and formed sequentially in a specified pattern to form a multilayer wiring part. At the stage for forming the multilayer wiring part, a filling electrode is formed on the semiconductor substrate such that the surface is covered with an insulating film, a post electrode is formed on specified wiring at the multilayer wiring part, a first insulating layer is formed on one surface of the semiconductor substrate, the surface of the first insulating layer is removed by a specified thickness to expose the post electrode, and the other surface of the semiconductor substrate is ground to expose the filling electrode and to form a through-type electrode. A second insulating layer if formed on one surface of the semiconductor substrate while exposing the forward end of the through-type electrode, and bump electrodes are formed on both electrodes. | 08-18-2011 |
20110199224 | SUBSTRATE INTER-TERMINAL VOLTAGE SENSING CIRCUIT - A substrate inter-terminal voltage sensing circuit which can promptly sense a plasma charge-up occurring on a semiconductor wafer across a wide range without connection of a voltage measuring instrument. The substrate inter-terminal voltage sensing circuit is adapted to sense a voltage occurring between a pair of electrodes arranged on a semiconductor substrate. The voltage sensing circuit includes a resistance path that is connected between the electrodes. The voltage sensing circuit also includes a circuit power supply that is connected at one end to a midpoint of the resistance path. The voltage sensing circuit also includes at least two fuse circuits that are connected between one end of the resistance path and the other end of the circuit power supply so as to be in parallel with each other. The fuse circuits have different rated fusing currents from each other. Each of the fuse circuits includes a switch that turns ON or OFF depending on a potential difference between the one end and midpoint of the resistance path. Each fuse circuit also has a current path that is connected across the circuit power supply. The current path possesses a resistive element and a fuse element serially connected to the switch. | 08-18-2011 |
20110198748 | Semiconductor device and method of fabricating same - A method of fabricating a semiconductor device includes: forming a semiconductor chip portion having an electrode on a main surface of a wafer; forming a first resist pattern having a first opening on the electrode; filling the first opening with a first electrically conductive material, thereby forming an electrically conductive post; removing the first resist pattern after said forming of the electrically conductive post; forming an interlayer dielectric film having a second opening positioned on the electrically conductive post; and forming an electrically conductive redistribution layer extending from an upper surface of the electrically conductive post over an upper surface of the interlayer dielectric film. | 08-18-2011 |
20110189798 | CHIP ID APPLYING METHOD SUITABLE FOR USE IN SEMICONDUCTOR INTEGRATED CIRCUIT - A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer. | 08-04-2011 |
20110187446 | SEMICONDUCTOR DEVICE - A semiconductor device includes a bonding option pad, an internal power supply, and a MOS transistor. The bonding option pad is selectively wire-bonded to two voltage supply portions through which external power supply voltages with different power supply potentials are supplied from an external power supply. The internal power supply is caused to generate a pre-specified internal power supply voltage. The MOS transistor stabilizes an output level of the internal power supply voltage. The source and drain of the MOS transistor are shorted together and connected to the bonding option pad, and the gate there. | 08-04-2011 |
20110185239 | SEMICONDUCTOR TESTING APPARATUS AND METHOD - The present invention provides a semiconductor testing apparatus and method capable of reliably determining whether a semiconductor memory is good or bad. A “1” reading test of each cell corresponding to one bit at a first step is first performed on a memory cell array. “0” writing of each cell corresponding to one bit at a second step and a “0” reading test of each cell corresponding to one bit at a third step are executed on the memory cell array. Thus, the time taken from the supply of power to the start of the “0” reading test of the reference cell at the third step can be significantly shortened. As a result, a defect of a reference bit line due to a breaking or high resistance of a gate of a reference column switch transistor corresponding to a normally ON transistor can be screened. | 07-28-2011 |
20110183496 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SUBSTRATE CARRIER STRUCTURE - A substrate carrier structure includes a tray and a secondary electron absorbing material. The tray holds a semiconductor substrate having a first surface on which semiconductor device elements are formed. The secondary electron absorbing material is interposed between the tray and this first surface of the semiconductor substrate. When the semiconductor substrate is irradiated with charged particles to form lattice defects, the secondary electron absorbing material prevents unwanted trapping of secondary electrons emitted from the tray, and thereby reduces the variability of electrical characteristics of semiconductor device elements formed on the semiconductor substrate. | 07-28-2011 |
20110181329 | SEMICONDUCTOR DEVICE AND PULSE WIDTH DETECTION METHOD - An internal pulse waveform shaping circuit provided to an IC chip generates an internal pulse monitor signal that changes in a predetermined direction at a rise timing of an internal pulse signal during a period in which a first enable signal is asserted and a second enable signal is de-asserted and then continues in the changed state for a predetermined period of time or longer, and generates the internal pulse monitor signal that changes in the predetermined direction at a fall timing of the pulse signal during a period in which the first enable signal is de-asserted and the second enable signal is asserted and then continues in the changed state for the predetermined period of time or longer. The generated internal pulse monitor signal is output to a tester for detecting the pulse width of the internal pulse signal. | 07-28-2011 |
20110171786 | Mold resin sealing device and molding method - A mold resin sealing device for sealing a surface of a semiconductor wafer with a mold resin, includes: a first mold die; and a second mold die disposed opposite to the first mold die, the second mold die having a second surface; wherein the first mold die includes a first part having a first surface facing the second surface of the second mold die and having an opening in a central region of the first surface; and a first step-like movable part capable of moving in the opening in both directions so that the first step-like movable part moves toward and away from the second mold die. | 07-14-2011 |
20110171779 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A BGA substrate which has a back surface to which a heat radiating plate is attached and an opening for accommodating a relay wiring substrate therein, which is provided in the center of its surface, is used. The relay wiring substrate to which an ASIC chip and a memory chip are flip-chip connected, is bonded to the heat radiating plate in the opening with a thermal conductive bonding material. Further, each of the back surfaces of the ASIC chip and the memory chip is connected to a metal cap for sealing the opening through a thermal conductive material interposed therebetween. | 07-14-2011 |
20110163422 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF PRINTING ON SEMICONDUCTOR WAFER - A method of printing on a semiconductor wafer, a manufacturing method of a semiconductor device, and a semiconductor device which enable to easily perform positioning in the direction perpendicular to the top of the wafer and to easily identify the type of the wafer. The manufacturing method includes preparing a semiconductor wafer having a structure in which an element forming film is stacked on the top of an insulative transparent substrate, forming a light reflection film to reflect light for positioning on the bottom of the transparent substrate, irradiating a laser from the side at which the element forming film is disposed so as to form printed letters at the light reflection film, forming a semiconductor element at the element forming film, forming an interlayer dielectric film to cover the element forming film and the semiconductor element, forming a contact wire, and forming a metal wire on the interlayer dielectric film. | 07-07-2011 |
20110156193 | SEMICONDUCTOR COMPONENT AND METHOD OF FABRICATING SEMICONDUCTOR COMPONENT - There is provided a semiconductor component including: a semiconductor substrate of a first conduction type; a semiconductor layer of a second conduction type that is formed on the semiconductor substrate and is PN-joined with the semiconductor substrate; an insulator layer laminated on the semiconductor layer; a metal layer laminated on the insulator layer at a pre-specified region; a semiconductor of the second conduction type at a side of the semiconductor layer at which the insulating layer is laminated, the semiconductor being formed directly under the metal layer such that incident light that is incident from the metal layer side is not illuminated onto the semiconductor layer, and the semiconductor containing more impurities than the semiconductor layer; and a conduction portion that conducts between the metal layer and the semiconductor. | 06-30-2011 |
20110153046 | Signal processing device and signal processing method - A signal processing device includes a first amplifier, a converter, a signal processor, a controller, and a second amplifier. The first amplifier amplifies a level of an externally input analog audio signal with a first gain whose value is variable. The converter converts the analog audio signal amplified by the first amplifier into a digital audio signal. The signal processor that performs tone control signal processing on the digital audio signal. The controller detects a level of the digital audio signal before the signal processing and controls the value of the first gain in accordance with the detected level. The second amplifier detects a level of the digital audio signal after the signal processing and amplifies the digital audio signal after the signal processing with a second gain determined in accordance with the detected level and the first gain whose value has been controlled by the controller. | 06-23-2011 |
20110151638 | Method of fabricating semiconductor device - There is provided a method of fabricating a semiconductor including: forming a first and a second bipolar transistors on a semiconductor substrate; forming a dummy layer on, or on the periphery of, at least one region of the emitter region, the base region, or the collector region of the second bipolar transistor and on an area surrounding a contact region for establishing an electrical connection to the outside in the at least one of the emitter region, the base region, or the collector region; forming an insulation layer so as to cover the first bipolar transistor, the second bipolar transistor, and the dummy layer; forming, together with the insulation layer and in a contact region of each region of the first bipolar transistor and the second bipolar transistor, a contact hole for establishing contact with each of those regions; and embedding a conductive member in the contact holes. | 06-23-2011 |
20110150237 | Signal processing device and signal processing method - A signal processing device includes a non-inverting amplifier, an inverting amplifier, a converter, and a controller. The non-inverting amplifier amplifies a level of an analog sound signal input from outside with a first gain whose value is variable. The inverting amplifier amplifies a level of the analog sound signal amplified by the non-inverting amplifier with a second gain whose value is variable. The converter converts the analog sound signal amplified by the inverting amplifier to a digital sound signal. The controller detects a level of the digital sound signal converted by the converter and, in accordance with the detected level of the digital sound signal converted by the converter, controls the first gain and the second gain such that a level of the analog sound signal input to the converter is at a pre-specified level. | 06-23-2011 |
20110148850 | SYNCHRONOUS PROCESSING SYSTEM AND SEMICONDUCTOR INTEGRATED CIRCUIT - A synchronous processing system having semiconductor integrated circuits. One of the semiconductor integrated circuits as a master chip comprises a first synchronization controller and a first counter controller that allows a counter in the master chip to perform counting synchronously with a clock pulse in response to a synchronization control signal from the first synchronization controller. Another semiconductor integrated circuit as a slave chip comprises a second synchronization controller that receives the synchronization control signal from the master chip, and a second counter controller that allows a counter in the slave chip to perform counting synchronously with the clock pulse in response to the synchronization control signal received. Each of the first and second counter controllers allows the counter to stop counting if the synchronization control signal is not supplied at the time point that a count value of the counter has reached a predetermined value. | 06-23-2011 |
20110148842 | SOURCE DRIVER FOR LIQUID CRYSTAL DISPLAY PANEL - A source driver for a liquid crystal display panel which comprises a first amplifier which outputs a drive voltage to one of two mutually adjacent column terminals of the liquid crystal display panel, a second amplifier which outputs a drive voltage to the other of the two mutually adjacent column terminals of the liquid crystal display panel, a switching portion which alternately outputs a first reference voltage and a second reference voltage corresponding to image data to the first and second amplifiers through two output terminals by switching operations performed for each predetermined period, and a connecting portion which electrically connects lines from the two output terminals to the amplifiers, while the switching portion is performing a switching operation. | 06-23-2011 |
20110148516 | MINUTE CAPACITANCE ELEMENT AND SEMICONDUCTOR DEVICE USING THE SAME - A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance. | 06-23-2011 |
20110148472 | VOLTAGE CHANGE DETECTION DEVICE - A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential according to a comparison between a voltage at the first node and a voltage at the second node. | 06-23-2011 |
20110142231 | Prime number generating device, prime number generating method, and computer readable storage medium - A prime number generating device is provided that includes a computation unit capable of performing at least addition and division on data of a predetermined number of bits or less; a prime number candidate data generating unit that generates prime number candidate data with a larger number of bits than the predetermined number of bits; a partitioned prime number candidate data generating unit that generates a plurality of partitioned prime number candidate data elements by partitioning the prime number candidate data; and a determination data generating unit that generates determination data for determining whether or not the prime number candidate expressed by the prime number candidate data is a composite number by using the computation unit to add together the respective plurality of partitioned prime number candidate data elements. | 06-16-2011 |
20110140223 | LIGHT DETECTING APPARATUS AND METHOD OF MANUFACTURING SAME - A light detecting apparatus includes an SOI substrate. In the SOI substrate, a semiconductor layer and a silicon substrate are laminated via an insulating layer. The semiconductor layer has a light receiving unit and a circuit unit formed therein. The light detecting apparatus also includes an interlayer insulating film formed on a first main surface of the SOI substrate. The light detecting apparatus also includes a front surface circuit wiring embedded in the interlayer insulating film. The light detecting apparatus also includes a front surface pseudo-wiring having a grid unit. The grid unit has at least one opening allowing passage of a light of a predetermined wavelength range to the light receiving unit. The light detecting apparatus also includes a rear surface circuit wiring and a rear surface pseudo-wiring formed on a second main surface of the SOI substrate. The light detecting apparatus also includes a penetration circuit wiring that connects the front surface circuit wiring to the rear surface circuit wiring. The light detecting apparatus also includes a penetration pseudo-wiring that electrically connects the front surface pseudo-wiring to the rear surface pseudo-wiring. The light receiving unit is surrounded by the front surface pseudo-wiring, the rear surface pseudo-wiring, and the penetration pseudo-wiring. | 06-16-2011 |
20110133845 | OSCILLATOR CIRCUIT - The present invention provides an oscillator circuit that can decrease consumed current. Namely, a second PMOS transistor is provided between a first PMOS transistor in which a constant current flows and an NMOS transistor for amplifying an oscillating signal, in order to interrupt the constant current flowing in the first PMOS transistor MP | 06-09-2011 |
20110133291 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME - Disclosed is a fabrication method which includes: forming a first gate electrode and a second gate electrode which cross over an active region, the overall width of the second gate electrode being less than that of the first gate electrode; ion-implanting dopants into the active region at an oblique angle using the first and second gate electrodes as a mask for ion-implantation, thereby to form separated doped regions on opposite sides of the first gate electrode and to form a continuous doped region extending from one of opposite sides of the second gate electrode to the other. | 06-09-2011 |
20110129034 | FSK SIGNAL MODULATOR FOR PRODUCING A BINARY FSK SIGNAL - An FSK signal modulator is provided in a transmitter which receives desired information to be transmitted on its input and which modulates the information to be transmitted to transmit a binary FSK signal. A counter counts a value of addition with the value of addition modified in accordance with a predetermined rule, depending on the value specified by the information to be transmitted, and for holding the counted value . The count value is determined by a threshold value decision circuit with respect to a threshold value. The result from the decision is output in the form of binary FSK signal. An FSK signal modulator will be provided which is simplified in circuit constitution. | 06-02-2011 |
20110128019 | Method and circuitry for identifying plug type - This method is applied to a dual-use jack of an electronic device. Either a headphone plug or a line output plug is inserted into the dual-use jack. The method determines the type of a plug connected to the dual-use jack when the plug is inserted into the dual-use jack. The determination is made based on a load resistance of the plug connected to the jack. The method includes feeding an electric current through the load resistance in a first direction. The method compares a voltage across the load resistance to a reference voltage and determines the type of the plug in use. The method also includes feeding an electric current through the load resistance in a second direction. This electric current can reduce or eliminate a pop-noise when the plug type is determined. The second direction is different from the first direction. | 06-02-2011 |
20110117741 | Method of fabricating SOI wafer - There is provided a method of fabricating an SOI wafer, the method including: a) preparing a bonded SOI substrate that has a buried oxide layer and an SOI layer formed in this sequence on a circular plate shaped support, and at a peripheral edge portion of the support substrate, has a silicon island region in which the SOI layer is not well formed with scattered defective silicon layer; b) etching a silicon island region defective silicon layer to remove the defective silicon layer scattered in the silicon island region by dry etching; and c) etching a silicon island region buried oxide layer to remove the buried oxide layer in the silicon island region by wet etching. | 05-19-2011 |
20110115775 | VACUUM FLUORESCENT DISPLAY DRIVING APPARATUS - The present invention provides a vacuum fluorescent display driving apparatus and a vacuum fluorescent display driving method that may prevent generation of excessive load on power lines employed in driving, without causing an increase in size of the apparatus. The vacuum fluorescent display driving apparatus of the present invention includes, a grid driver that applies a driving voltage to plural grid electrodes respectively provided in the vacuum fluorescent display, and a grid driver limiting section that performs limitation on the number of grid electrodes to which voltage is applied simultaneously by the grid driver, to less than a predetermined first threshold value. | 05-19-2011 |
20110113881 | ACCELERATION SENSOR AND METHOD OF FABRICATING ACCELERATION SENSOR - There is provided an acceleration sensor including: a weight portion; plural fixed portions formed above a bottom plate around a periphery of the weight portion; a beam portion coupling the fixed portions and the weight portion, and holding the weight portion at a position separated from the bottom plate; a detection portion provided at the beam portion and detecting deformation of the beam portion; a frame portion provided so as to project out from the bottom plate and surround the fixed portions at a position separated from the fixed portions; and a lid portion of plate shape that seals an opening of the frame portion. | 05-19-2011 |
20110103511 | TRANSMISSION APPARATUS, SIGNAL SENDING APPARATUS, AND SIGNAL RECEIVING APPARATUS, AND TRANSMISSION METHOD, SIGNAL SENDING METHOD, AND SIGNAL RECEIVING METHOD - A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal. | 05-05-2011 |
20110102085 | DIFFERENTIAL AMPLIFIER - A high-gain differential amplifier that is capable of high speed operation is provided. A differential amplifier that outputs a signal representing a difference between signals respectively inputted to first and second input terminals and a phase-inverted signal thereof via first and second output terminals respectively, is provided with a first switching element that makes a short-circuit between the first input terminal and the second output terminal when turned on, a second switching element that makes a short-circuit between the second input terminal and the first output terminal when turned on, and a third switching element that makes a short-circuit between the first output terminal and the second output terminal when turned on. The third switching element is set to an ON state for a predetermined period while the first and second switching elements are set to an OFF state. Subsequently, the third switching element is switched to the OFF state and both of the first and second switching elements are switched to the ON state. | 05-05-2011 |
20110101539 | Semiconductor device and manufacturing method of semiconductor device - Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal. | 05-05-2011 |
20110101458 | SOI type semiconductor device having a protection circuit - An SOI type semiconductor device having a silicon substrate and a buried oxide layer formed on the silicon substrate includes an internal circuit formed in a first region having at least one FD type transistor having a SOI structure, the internal circuit performing a function of the semiconductor device and a protection circuit formed in a second region having at least one PD type transistor having a SOI structure, the protection circuit protecting the internal circuit from electro static damage. | 05-05-2011 |
20110095817 | OVERCURRENT DETECTION CIRCUIT AND SIGNAL AMPLIFYING DEVICE - Disclosed is a signal amplifying device which includes an overcurrent detection circuit, a first inverting amplifying circuit amplifying an input signal, and a second inverting amplifying circuit amplifying an output of the first inverting amplifying circuit. The overcurrent detection circuit includes a comparison circuit and a decision circuit. The comparison circuit compares the voltage of the input signal with the voltage of an output of the second inverting amplifying circuit, and generates a signal responsive to the comparison result. The decision circuit detects overcurrent from the signal output by the comparison circuit. | 04-28-2011 |
20110095793 | BIAS POTENTIAL GENERATING CIRCUIT - The present invention provides a bias potential generating circuit including: a clock supply circuit that generates a clock signal having a predetermined frequency; a rising sine wave generating circuit that generates a rising wave form signal having a wave form of a rising portion of a sine wave; a ΔΣ conversion circuit that generates a pulse width modulation signal by pulse width modulating the rising wave form signal; a first resistor, one end connected to a reference potential input terminal of an operational amplifier; a second resistor, one end connected to the first resistor and to the reference potential input terminal of the operational amplifier, and the other end being grounded; and a switch connected to a power supply and to the other end of the first resistor, the switch being turned ON and OFF by the pulse width modulation signal. | 04-28-2011 |
20110092022 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device includes a semiconductor chip having a plurality of electrode pads, and a rewiring pattern having a plurality of interconnects which are connected to the electrode pads and extend over an insulation film. The semiconductor device also includes a plurality of columnar electrodes each of which has a main body section and a protrusion section, and a sealing section which has a top face having a height the same as the top faces of the protrusion sections. The semiconductor device also includes solder balls formed on the protrusion sections. The semiconductor device also has a plurality of trenches in the sealing section. Each trench has a depth which reaches the boundary between the main body and protrusion of the electrode. The side faces of the protrusion section are exposed face defined by the trenches. Each solder ball is electrically connected to the top face and side faces of the protrusion section of each electrode. | 04-21-2011 |
20110090752 | Semiconductor memory device - There is provided a semiconductor memory device including: plural memory cells; a selection signal outputting section; a first precharging section that precharges a potential of a data line that outputs, to an exterior, a signal of a level corresponding to data stored in the memory cell; and a bit line selecting section that has, per bit line, a bit line selecting section that comprises (1) a second precharging section, (2) a potential lowering section, and (3) a third precharging section connected to the bit line selection line and the bit line between the second precharging section and a connection point at which the potential lowering section is connected to the bit line, and when the non-selection signal is inputted, the third precharging section precharges the bit line between the second precharging section and the connection point at which the potential lowering section is connected to the bit line. | 04-21-2011 |
20110090005 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR ELEMENT, AND SUBSTRATE - A semiconductor device, a semiconductor element, and a substrate are provided, which allow the semiconductor element to be provided with a reduced size when combined. The semiconductor device has a rectangular semiconductor element mounted on a substrate formed with an external input terminal, an external output terminal, and a plurality of wiring patterns connected to each of the external input terminal and the external output terminal. The semiconductor element includes a grayscale voltage generating unit for generating a plurality of grayscale voltages by dividing a reference voltage, a plurality of electrodes for the reference voltage formed in the neighborhood of the grayscale voltage generating unit; and an internal wiring for connecting the grayscale voltage generating unit and the reference voltage electrodes. The substrate includes a wiring pattern for the reference voltage for connecting the external input terminal and the reference voltage electrodes. | 04-21-2011 |
20110089569 | Multilayer wiring, method for placing dummy wiring in multilayer wiring, semiconductor device, and semiconductor device manufacturing method - A multilayer wiring in which plural metal wirings and plural interlayer insulating films are layered, each interlayer insulating film being planarized each time formed, is divided into plural regions. The percentage of an area occupied by each of the metal wirings within each region is obtained for each of the metal wirings. An integral percentage is obtained per region by integrating, the percentages. The integral percentages are used to calculate the relative positional relationship of upper surfaces of the interlayer insulating films of plural regions, from the relative values of the integral percentages obtained beforehand and relative positions of the upper surfaces. In regions where the upper surface is of a height lower than a predetermined value, a dummy wiring is disposed, and in regions where the upper surface is of a height equal to or greater than the predetermined value, a dummy wiring is not disposed. | 04-21-2011 |
20110089562 | SEMICONDUCTOR DEVICE HAVING WAFER-LEVEL CHIP SIZE PACKAGE - A semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. The surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is included on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer is included as having openings exposing part of the conductive pattern. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The thickness of the protective layer, which may function as a package of the semiconductor device, is thus reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes. | 04-21-2011 |
20110089494 | Semiconductor device having fuse and protection circuit - A semiconductor device having a semiconductor substrate, an insulating layer, a fuse, a diffusion layer and a resistor. The semiconductor substrate has a first conductivity type. The insulating layer is selectively formed on the surface of the semiconductor substrate. The fuse is formed on the insulating layer. The diffusion layer has a second conductivity type. The diffusion layer is formed on the surface of the semiconductor substrate and electrically connected to the fuse. The first resistor is electrically connected to the fuse. | 04-21-2011 |
20110084740 | POWER-ON RESET CIRCUIT - A power-on reset circuit includes a first-conductive-type MOS transistor having a first source connected to a first power supply, a first drain, and a first gate connected to a second power supply; a second-conductive-type MOS transistor having a second source connected to the second power supply, a second drain connected to the first drain, and a second gate, to which a bias potential which depends on neither a potential of the first power supply nor a potential of the second power supply is applied; and an output node for outputting a reset signal corresponding to a potential of the first drain, in a process that a voltage between the first power supply and the second power supply increases. | 04-14-2011 |
20110074032 | Semiconductor device - A semiconductor device which is capable of preventing interface peeling and a crack from occurring in the vicinity of the edge part of a rewiring layer is provided. The semiconductor device includes a semiconductor substrate, an electrode pad formed on the semiconductor substrate, a first insulation film formed on the semiconductor substrate having a first aperture which exposes the electrode pad, a first conductor film formed on the electrode pad and the first insulation film, an external electrode electrically connected to the first conductor film, and a sealing resin which covers the first conductor film and the first insulation film. The first conductor film includes a plurality of copper layers which are stacked so that an outer edge portion of the first conductor film has a stepped portion. | 03-31-2011 |
20110073916 | GATE ARRAY - A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased. | 03-31-2011 |
20110070729 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device, includes: preparing a semiconductor IC chip and an external electrode terminal which is positioned away from the semiconductor IC chip, wherein the semiconductor IC chip has first and second electrode pads thereon, the second electrode pad being positioned between the first electrode pad and the external electrode terminal; connecting the first electrode pad and the external electrode terminal by a loop-like wire; and pressing a portion of the loop-like wire toward the semiconductor IC chip, thereby connecting the portion of the loop-like wire with the second electrode pad. | 03-24-2011 |
20110069771 | OFDM RECEIVER AND DOPPLER FREQUENCY ESTIMATING CIRCUIT - A radiofrequency signal is converted to an intermediate frequency signal by a tuner, which is amplified by a variable gain amplifier. The so-amplified signal is converted into a digital signal by an ADC, which is supplied to an FFT, where it is separated into signals set every carrier, followed by being supplied to equalizers different in characteristic. The digital signal outputted from the ADC is further supplied to a level converting circuit from which a control signal is generated. The control signal is supplied to a DAC and a Doppler frequency detector. The DAC generates a gain control signal and supplies the same to the variable gain amplifier. The Doppler frequency detector outputs a frequency component of the control signal as a Doppler detection signal. The Doppler detection signal is compared with a threshold value by a comparator. A selector selects one of signals outputted from the equalizers, in accordance with a select signal indicative of the result of comparison. | 03-24-2011 |
20110057685 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE LAYOUT METHOD - There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed. | 03-10-2011 |
20110054831 | MOVEMENT DETECTION DEVICE, ELECTRONIC DEVICE, MOVEMENT DETECTION METHOD AND STORAGE MEDIUM STORED WITH A PROGRAM - A movement detection device that includes an acceleration detection unit, a splitting unit and a movement detection unit is provided. The acceleration detection unit detects each respective acceleration component of acting acceleration for each axis of a three-dimensional orthogonal coordinate system and outputs respective acceleration component data. The splitting unit splits the respective acceleration component data output from the acceleration detection unit into a stationary component obtained by low-pass filter processing and a movement component that is the respective acceleration component data from which the respective stationary component has been removed. The movement detection unit detects which axial direction the acceleration detection unit has moved in for each of the axes based on a movement component indicating the maximum value split by the splitting unit. | 03-03-2011 |
20110051817 | VIDEO DECODER - A video decoder is provided which can convert analog composite video signals into noise-suppressed luminance and color difference signals without increasing the system in size. From the A/D converted composite video data, luminance component data carrying the luminance component and color difference component data carrying the color difference component are acquired. Then, dithering is performed on each piece of the luminance component data and the color difference component data for output as digital luminance and color difference signals. | 03-03-2011 |
20110044122 | WORD LINE DRIVING APPARATUS - A source potential of a pull-up transistor is increased after predetermined time from a rising timing of a word line selection command signal. To this end, a condenser is provided to couple the source potential and gate potential of the pull-up transistor. Preferably a gate potential control transistor that controls the gate potential of the pull-up transistor is a depletion type N-channel field effect transistor that maintains the gate potential at a low level. | 02-24-2011 |
20110037147 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An improved manufacturing method of a semiconductor device is provided. The method includes preparing a semiconductor substrate having an integrated circuit together with connection pads. The method also includes forming a dielectric film on the semiconductor substrate. The method also includes forming connection wires having a predetermined pattern on the dielectric film such that the connection wires are electrically connected to the connection pads. The method also includes forming a surface resin layer to partially cover the connection wire. The method also includes forming a metal film over the exposed connection wires. The method also includes forming a display unit having through holes to present identification information in a region corresponding to the center area of the semiconductor substrate on the surface resin layer. The forming of the metal film and the forming of display unit are carried out simultaneously. | 02-17-2011 |
20110031954 | Driving power-supply circuit - The object of the present invention is reducing power consumption of a driving power supply circuit. In the case where the driving voltage Vi is higher than the reference voltage ViH, The signal S | 02-10-2011 |
20110031615 | Semiconductor device - A semiconductor device having a structure that can reduce stress due to difference in coefficients of thermal expansion and prevent or suppress generation of cracks, and a semiconductor device manufacturing method, are provided. The semiconductor device includes a single crystal silicon substrate having a main face on which semiconductor elements are formed and a side face intersecting with the main face, and a sealing resin provided covering at least a portion of the side face. The side face covered by the sealing resin is equipped with a first face with a plane direction forming an angle of −5° to +5° to the plane direction of the main face. | 02-10-2011 |
20110029696 | INFORMATION PROCESSING DEVICE - An information processing device includes: an address converter including a base address register in which address conversion information is stored and a conversion circuit that converts a PCI Express standard bus address of an inputted packet to a non-PCI Express standard bus address; and a packet generator. When first configuration information of a first device that has a device-unique unique address, is connected to a non-PCI Express standard bus and is unaware of the unique address is stored, the packet generator generates an address setting-use configuration write request packet, and when second configuration information including change information for changing the base address register to a base address register of a second device where at least one of an address width and an internal memory address is a device-unique unique value, the packet generator generates a change setting-use configuration write request packet and outputs the generated packet to the address converter. | 02-03-2011 |
20110024904 | SEMICONDUCTOR PACKAGE, PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a wiring board; a first electrode for external connection; a ball pad; a semiconductor chip; a mold resin; an electrode unit connected with the ball pad and penetrating the mold resin; and a second electrode for external connection connected with a portion of the electrode unit on a side of an outer surface of the mold resin. The electrode unit includes a first ball disposed on the ball pad; a second ball disposed between the first ball and the second electrode; and a solder material connecting between the ball pad and the first ball, between the first ball and the second ball, and between the second ball and the second electrode for external connection; each of the first ball and the second ball including a core part having a glass transition temperature which is higher than a melting point of the solder material. | 02-03-2011 |
20110006438 | SEMICONDUCTOR WAFER, AND SEMICONDUCTOR DEVICE FORMED THEREFROM - A semiconductor wafer has a substrate, and a plurality of active areas formed on the substrate. Integrated circuits are formed in the active areas. The semiconductor wafer also has dicing areas formed between the adjacent active areas. A seal ring is formed along the edge (periphery) of each active area. The semiconductor wafer also has interconnects formed closely to the inside of the seal ring. A protective layer covers the active areas. A protective film is formed on the protective layer at the locations of the active areas. The semiconductor wafer also has other interconnects formed on the protective film for electrical connection to the integrated circuits. Preferably, when the aspect ratio of a groove formed in the protective layer between the seal ring and the interconnect is 0.5 or more, this groove is covered with the protective film. | 01-13-2011 |
20110003026 | Sealing apparatus for semiconductor wafer, mold of sealing apparatus, and semiconductor wafer - A sealing apparatus for sealing by resin a semiconductor wafer having semiconductor elements on its surface. The apparatus includes an upper mold and a tower mold having an area where the semiconductor wafer is mounted, the lower mold having an uneven surface in the area and a shock absorber under the lower mold. | 01-06-2011 |
20110002481 | AUDIO SIGNAL AMPLITUDE ADJUSTING DEVICE AND METHOD - An audio signal amplitude adjusting device and method that can always adjust the amplitude of an input audio signal to such a level as to be easy to hear with making it follow each shift in the level of the input audio signal, thus preventing the occurrence of the sense of aural discomfort and an interruption of a voice. The gain of a variable attenuator for adjusting the amplitude of the audio signal is controlled in various ways. When a momentary large noise sound is contained in the audio signal, the gain reduced state invoked to suppress the effect of the noise sound is detected, and thereafter if the amplitude of the audio signal has become smaller than the reference level due to the noise sound ending, the gain is increased each period that is shortest among the periods of control employed. | 01-06-2011 |
20110001234 | Semiconductor device and fabrication method thereof - Disclosed is a semiconductor device that comprises a first insulating film provided on a main face of a semiconductor substrate; a first pedestal provided at a first wiring layer on the first insulating layer; a second insulating film provided on the first wiring layer; and a second pedestal provided at a second wiring layer on the second insulating film, wherein, when the first and second pedestals are projected in a direction perpendicular to the main face onto a plane parallel to the main face, the second pedestal is larger than the first pedestal, and the whole of the first pedestal is disposed at an inside of the second pedestal. | 01-06-2011 |
20100330811 | Method for forming via holes - An improved method of forming a via hole is provided. This method makes it possible to form a via hole having a highly accurate processed shape in an insulating body. The insulating body has a multi-layer structure made of different kinds of insulating layers. The insulating body has, for example, a first insulating layer and a second insulating layer on the first insulating layer. The first insulating layer is provided on a lower wiring layer. The method includes a step of forming a first through hole in the second insulating layer by dry etching. The first through hole reaches the first insulating layer. The side wall of the first through hole defines an exposed portion of the second insulating layer. The bottom of the first through hole defines an exposed portion of the first insulating layer. The method also includes a step of assimilating the exposed portion of the second insulating layer and the exposed portion of the first insulating layer so that the exposed portions of the first and second insulating layers have the same composition. The method also includes a step of forming a second through hole extending from the first through hole to the lower wiring layer by dry etching. The first and second through holes defines a via hole. The via hole is made by removing the exposed portion of the first insulating layer. | 12-30-2010 |
20100329956 | Exhaust gas treatment method and system - An exhaust gas treatment system treats exhaust gases collected from at least one PFC dealing device that deals with a PFC gas. The exhaust gas treatment system includes: an exhaust emission line through which the exhaust gases collected from the PFC dealing device; an external exhaust gas disposal device connected to the exhaust emission line so as to purify the exhaust gases for exhaust emission; a gas treatment device for eliminating the PFC gas from the exhaust gases; a gas treatment line branched from the exhaust emission line to supply the exhaust gases to the gas treatment device; and an intermediate line for discharge the treated exhaust gases from the gas treatment device to the external exhaust gas disposal device. | 12-30-2010 |
20100329025 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - The present invention provides a readout circuit including: a memory cell array that includes a readout target memory cell that is a data readout target; a reference memory cell having the same configuration as this memory cell; a first constant current source and a second constant current source which have the same characteristics; and a reference current source that generates, as a reference current for determining the logic level of the readout target memory cell, a current obtained by adding one constant current, out of a first constant current flowing through the first constant current source or a second constant current flowing through the second constant current source, with a reference memory cell current flowing in the reference memory cell, and by subtracting the other constant current, out of the first constant current or the second constant current, from the added current. | 12-30-2010 |
20100327919 | DIFFERENTIAL AMPLIFIER CIRCUIT - A differential amplifier main circuit amplifies, while first voltage is applied to drains of first and second transistors via a load circuit and second voltage is applied to source of third transistor, a difference between voltages applied to gates of the first and second transistors, and outputs it from a connection between the load circuit and drains of the first or second transistor. A voltage application circuit applies voltage to the gate of the third transistor so that a current between the source and drain thereof to have a predetermined magnitude. Gates of transistors of the application circuit are connected to a second common-connection of drains thereof to which the first voltage is applied via a load, the second voltage is applied to a first common-connection of sources of the transistors, and a connection of the second common-connection and the load is connected to the gate of the third transistor. | 12-30-2010 |
20100327458 | Semiconductor device - There is provided a semiconductor device including: a metal wiring line formed on a semiconductor substrate; an inside chamfer provided only at the inside of a bend in the metal wiring line, widening the wiring line width at the inside of the bend; and a protection film covering the metal wiring line. | 12-30-2010 |
20100327454 | SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: an insulating layer provided on a substrate and formed with plural cavities; wiring lines provided on the insulating layer; plural branched wiring lines that branch from the wiring lines so as to respectively overlap with the plural cavities when seen in plan view; a conductive portion formed on the wiring lines; an external terminal formed on the conductive portion; and a sealing resin layer that seals the wiring lines and the conductive portion. | 12-30-2010 |
20100323528 | Semiconductor manufacturing apparatus and method for manufacturing a semiconductor - Provided are a semiconductor manufacturing apparatus and method, capable of reliably and rapidly transporting a heated semiconductor wafer. the apparatus is provided for transporting a semiconductor wafer, which has been processed by desired treatment (for example, film formation) and is held by a susceptor equipped with a heater, to the outside by a transport arm which holds the semiconductor wafer by suction, by moving the susceptor to a certain position above a top of a wafer waiting stage and introducing the semiconductor wafer held by the susceptor onto the top of the wafer waiting stage. Then, the susceptor present on the top of the wafer waiting stage is moved in a horizontal direction. After a certain cooling time, the transport arm holds the semiconductor wafer placed on the wafer waiting stage by suction and transports the semiconductor wafer to outside. | 12-23-2010 |
20100323524 | Method of etching the back side of a wafer - To etch the back side of a wafer, the front side of the wafer is first coated with a positive photoresist to form a protective film. The surface of the protective film is hardened by heating, or by heating and ultraviolet curing. The wafer is then placed in a plasma etching apparatus with the hardened surface of the protective film in contact with an electrode of the etching apparatus, and the back side of the wafer is patterned by plasma etching. When the etching is completed, the front side of the wafer is separated from the electrode and the wafer is removed from the plasma etching apparatus. The hardened positive photoresist prevents the wafer from sticking to the electrode. | 12-23-2010 |
20100322002 | EEPROM DEVICE - An EEPROM device which prevents disturbance phenomena when writing data on a memory cell. The device includes an on/off switch element for selectively connecting between an individual source line and a common source line in response to a control signal supplied via a control terminal. | 12-23-2010 |
20100321419 | DRIVER FOR DISPLAY PANEL - A driver for a display panel in which a plurality of light-emitting elements are arranged in a matrix, prevents false emission and/or destruction of the light-emitting elements from being caused when reset control is performed when scanning row lines included in the display panel. A cathode driver includes a plurality of groups composed of a timing circuit and transistors that correspond to a plurality of cathode lines, respectively. Each of the timing circuits controls the timing for switching on the transistors, so that the potentials of all the cathode lines excluding the cathode line that is the target to be scanned are slowly changed from the ground potential to the power supply potential after the reset period elapses. | 12-23-2010 |
20100321367 | DISPLAY DRIVER AND THRESHOLD VOLTAGE MEASUREMENT METHOD - A display driver drives a display in which each pixel includes a light-emitting element, a transistor that supplies current to the light-emitting element, and a capacitor that controls the transistor. To determine the threshold voltage of the transistor, the display driver charges the capacitor to an initial voltage, then allows the capacitor to discharge through the transistor, measures the time that elapses until the capacitor reaches a reference voltage intermediate between the initial voltage and the threshold voltage, and calculates the threshold voltage from the elapsed time. This measurement method is quick and does not require an analog-to-digital converter. The measured values are used to generate correction data to compensate for threshold voltage shifts. | 12-23-2010 |
20100321093 | REFERENCE VOLTAGE OUTPUT CIRCUIT - A first output section of a reference voltage output circuit outputs a negative gradient voltage of a first magnitude. An amplifier includes a non-inverting input terminal connected to the first output section, an inverting input terminal, and an output terminal. One end of a first resistor connected to the output terminal and the other end connected to the inverting input terminal. One end of a second resistor is connected to the other end of the first resistor. A second output section connected to the other end of the second resistor outputs a negative gradient voltage of a second magnitude having an absolute value greater than the first magnitude. A resistance value ratio of the first and second resistors is set such that a temperature gradient of the voltage applied to the first resistor is a positive gradient having an absolute value of the same magnitude as the first magnitude. | 12-23-2010 |
20100320581 | Semiconductor device - The invention provides a semiconductor device including a rectangular chip provided on a mounting region of a substrate, a liquid resin layer provided under the rectangular chip and on a side surface of the chip, and a plurality of dams formed on the substrate so as to extend along the side surface of the rectangular chip. The configuration allows the semiconductor device to be provided with the substrate having a reduced size which is achieved by preventing a liquid resin from flowing out. | 12-23-2010 |
20100307410 | CHEMICAL LIQUID RECOVERY CUP AND CHEMICAL LIQUID COATING DEVICE - In the present invention, at a coater cup | 12-09-2010 |
20100270675 | SEMICONDUCTOR DEVICE HAVING DAMASCENE INTERCONNECTION STRUCTURE THAT PREVENTS VOID FORMATION BETWEEN INTERCONNECTIONS HAVING TRANSPARENT DIELECTRIC SUBSTRATE - A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which includes a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem where the material of the first main interconnection transfers from a portion connected to the second interconnection due to electromigration to form a void, with the result that the first interconnection is disconnected from the second interconnection. | 10-28-2010 |
20100254665 | Semiconductor optical communication module and manufacturing method thereof - A semiconductor optical communication module includes a semiconductor chip mounted on a chip carrier and a lens assembly having an end parallel to and facing the front edge of the chip carrier. The semiconductor chip has a front facet oriented at an acute angle to the front edge of the chip carrier. An optical waveguide in the semiconductor chip transmits an optical signal that propagates on an optical axis extending from the front facet of the semiconductor chip to the end of the lens assembly. The optical axis is orthogonal to the end of the lens assembly and the front edge of the chip carrier. The angled mounting of the semiconductor chip on the chip carrier allows the lens assembly to be placed close to the edge of the chip carrier, and to be moved for optical axis adjustment without striking the chip carrier. | 10-07-2010 |
20100248425 | Chip-size-package semiconductor chip and manufacturing method - A method of manufacturing semiconductor chips includes preparing a semiconductor substrate having on its front side a plurality of chip forming areas; sticking a support to the front surface of the substrate via an adhesive sheet; forming through holes extending from the back surface of the substrate; forming a groove along each of boundaries between the chip forming areas, the groove extending from the back surface of the substrate through the adhesive sheet to the support to expose cross-sections of the adhesive sheet; forming an insulating film over the back surface so as to cover side walls of the through holes and the cross-sections of the adhesive sheet; and dicing the substrate along the grooves with the insulating film remaining. | 09-30-2010 |
20100248410 | Method of fabricating semiconductor device - There is provided a method of fabricating a semiconductor device having plural light receiving elements, and having an amplifying element, the method including: a) forming an active region on the semiconductor substrate for configuring the amplifying element; b) forming a light receiving element region on the semiconductor substrate for forming the plural light receiving elements, with the active region acting as a reference for positioning; c) implanting an impurity into the light receiving element region; d) repeating the process b) and the process c) a number of times that equals a number of diffusion layers in the light receiving element region; e) after implanting the impurity, performing a drive-in process to carry out drive in of the semiconductor substrate; and f) the process e), forming an amplifying element forming process by implanting an impurity in the active region. | 09-30-2010 |
20100246307 | INTERNAL POWER SUPPLY CONTROL CIRCUIT OF SEMICONDUCTOR MEMORY - An internal power supply control circuit of a semiconductor memory includes a periodic signal generating unit that generates a periodic signal to generate a permission signal to intermittently permit supply of power from an internal power supply circuit of the semiconductor memory to an internal circuit thereof with a predetermined period, when a mode changes from a normal operation mode where power is always supplied from the internal power supply circuit to the internal circuit to a standby mode where consumption power is further suppressed as compared with consumption power in the normal operation mode, and a permission signal output unit that outputs the permission signal synchronized with the periodic signal to the internal power supply circuit, when a mode signal indicating any mode of the normal operation mode and the standby mode and the periodic signal are input and the input mode signal indicates the standby mode. | 09-30-2010 |
20100246306 | START-UP CIRCUIT OF INTERNAL POWER SUPPLY OF SEMICONDUCTOR MEMORY - There is provided a start-up circuit of an internal power supply of a semiconductor memory, including: an odd number of inverters that are connected in series and output a signal indicating whether or not to start to supply power from an internal power supply circuit of the semiconductor memory to an internal power supply circuit, and a discharge unit that is connected to an output side of an inverter at an odd-numbered stage and discharges charges remaining at the connection point between the inverter at the odd-numbered stage and the inverter at the stage immediately thereafter, after supply of power to operate the inverters is stopped. | 09-30-2010 |
20100246283 | REFERENCE POTENTIAL GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY - There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input. | 09-30-2010 |
20100245342 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has an output terminal connected to an external load, an internal signal line by which the output terminal is connected to an internal node, and a voltage generator that outputs a voltage to the internal node, for output through the internal signal line and the output terminal to the external load. A voltage attenuating element is connected to the internal signal line to attenuate voltage swings on the internal signal line. A limiting circuit is connected to the internal node to limit the voltage at the internal node to a predetermined range. Moderate voltage swings caused by external electromagnetic interference are kept within the predetermined range by the voltage attenuating element, so that the limiting circuit does not operate and the average output voltage is not changed. | 09-30-2010 |
20100245322 | DISPLAY DRIVING DEVICE - The amount of communication with an external MCU can be reduced to reduce power consumption, and reduced power consumption and reduced cost can also be anticipated in the external MCU. An MCU first transmits old image data and new image data from image memory to a register by serial communication without modifying the data and with substantially no computational processing thereof. Combinations of waveform data necessary for displaying a color is then stored in a waveform latch circuit from a waveform data shift register and a combination of waveform data is selectively outputted by each of a group of 4-to-1 selectors. Data transmission from the external MCU from the waveform data shift register to the waveform latch circuit is thereby restricted to the initial stage. | 09-30-2010 |
20100244930 | SEMICONDUCTOR DEVICE FOR OUTPUT OF PULSE WAVEFORMS - A semiconductor device has multiple high-side field-effect transistors and multiple low-side field-effect transistors connected to a single output terminal to generate an output signal. A driver circuit outputs driving signals that turn the field-effect transistors on and off. The driving signal for the field-effect transistors on each side is conducted by a salicided gate line with salicide block areas that produce successive delays, causing the field-effect transistors to turn on sequentially. Alternatively, the transistors have different threshold voltages, or the driving signals for different transistors are output from drivers with different driving abilities, again causing the transistors to turn on sequentially. The output signal therefore rises and falls gradually, reducing electromagnetic interference. | 09-30-2010 |
20100244861 | PLASMA MONITORING METHOD - A plasma monitoring method measures in-situ a resistance of a side wall in a particular pattern and a current flowing in the side wall in the pattern. A monitoring system has two sensors in a plasma chamber. Each sensor has an upper electrode and a lower electrode. An external resistance element is connected only to one of the two sensors. The external resistance element is connected in parallel to the wires extending from the upper and lower electrodes of the sensor concerned. As a result, a resistance between the upper and lower electrodes is different in the two sensors, and two different values of potential difference between the upper and lower electrodes are obtained in-situ. Because a resistance value of the external resistance element is already known, a resistance value of a side wall of a contact hole per one contact hole is obtained in-situ. When the resistance per one contact hole is obtained, an electric current flowing in the side wall of the contact hole per one contact hole can be obtained. | 09-30-2010 |
20100244145 | Semiconductor memory device using hot electron injection - A semiconductor memory device has a low-resistivity semiconductor substrate on which a higher-resistivity semiconductor layer of the same conductivity type is formed. Memory cell transistors are formed in the semiconductor layer. A diffusion region, also of the same conductivity type, is formed below the memory cell transistors. The resistivity of the diffusion region is lower than the resistivity of the semiconductor layer. In the programming of data into the memory cell transistors by hot electron injection, the diffusion region reduces the voltage drop due to current flow from the part of the semiconductor layer near the memory cell transistors into the semiconductor substrate, thereby reducing unwanted elevation of the potential of the semiconductor layer. | 09-30-2010 |
20100244135 | Semiconductor device - In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region. | 09-30-2010 |
20100240212 | Method of manufacturing a semiconductor device - A semiconductor device manufacturing method includes a process for filling holes in a dielectric film with tungsten. The process deposits tungsten in the holes, partially etches the deposited tungsten, and then deposits additional tungsten in the holes. Voids that may be left by the first tungsten deposition step are made accessible by openings formed in the etching step, and are then filled in by the second tungsten deposition step. Tungsten hexafluoride may be used as both a deposition source gas and an etching gas, providing a simple and inexpensive process that is suitable for high-volume production. | 09-23-2010 |
20100240195 | FABRICATION METHOD FOR DEVICE STRUCTURE HAVING TRANSPARENT DIELECTRIC SUBSTRATE - A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer. | 09-23-2010 |
20100238734 | SEMICONDUCTOR NON-VOLATILE MEMORY, CHARGE ACCUMULATING METHOD FOR SEMICONDUCTOR NON-VOLATILE MEMORY, CHARGE ACCUMULATING PROGRAM STORAGE MEDIUM - There is provided a semiconductor non-volatile memory including: plural memory sections, a voltage application section, and a control section that controls the voltage application section wherein the control section controlling voltage application such that, based on a value of current detected by a current detection section, in a region where the current flowing in a channel region is greater than a predetermined target value at which a amount of charge accumulated has become a specific value in at least one of a first charge accumulating section or a second charge accumulating section, when a value of current flowing in the channel region approaches a target value, a rate of increase in the charge accumulating amount per time is decreased at least once. | 09-23-2010 |
20100238694 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device is configured to reduce data read time. In the semiconductor storage device, an input/output control circuit is formed along one side of a memory cell array disposed between a data input pad and a data output pad. The input/output control circuit is disposed between a hold command input pad and a clock input pad. Accordingly, it is possible to minimize the distances of the wirings from the input/output control circuit to the pads and to make the distances of the wirings equal and thus to minimize the read time of the memory cell array. In addition, since it is also possible to make equal wiring distances from the input/output control circuit to the address decoder and output multiplexer, it is possible to minimize the read time of the memory cell array. | 09-23-2010 |
20100237926 | VOLTAGE GENERATING CIRCUIT - A voltage generating circuit including first and second voltage sources, and a subtracting circuit. The subtraction circuit is configured as a differential amplifier including an op-amp and four resistors, with an inverting input terminal of the op-amp connected to the second voltage source via a first resistor, a second resistor connected between the inverting input terminal and an output terminal of the op-amp, a non-inverting input terminal of the op-amp connected to the first voltage source via a third resistor of the same size as the second resistor, the non-inverting input terminal of the op-amp connected to a reference potential terminal via a fourth resistor of the same size as the first resistor, the first voltage from the first voltage source and the second voltage from the second voltage source inputted to the subtracting circuit, and the subtracting circuit outputting a third voltage having a positive temperature coefficient. | 09-23-2010 |
20100237818 | DRIVING CIRCUIT FOR BRUSHLESS MOTOR USING HALL ELEMENT - A driving circuit feeds driving current to a coil in a brushless motor, and feeds bias current to a Hall element that senses the rotational position of the motor. The driving current and bias current are supplied from the same power supply, but the bias current passes through a load element that reduces power dissipation by the Hall bias circuit by causing some of the power to be dissipated by the load element instead. The Hall bias circuit can therefore be combined with the other driving circuitry into a single integrated circuit, even if the brushless motor is driven at a comparatively high voltage. | 09-23-2010 |
20100237413 | Semiconductor device and method for manufacturing semiconductor device - A semiconductor device has a LOCOS film formed on at least one of a drain side and a source side of a semiconductor substrate surface. A gate oxide film connected to the LOCOS film is formed on the semiconductor substrate surface. A conductive film is formed to cover the gate oxide film and the LOCOS film. A gate electrode is formed by etching the conductive film such that an end portion of the conductive film is positioned above the LOCOS film. The LOCOS film is etched such that an end portion of the LOCOS film is in alignment with an end portion of the gate electrode, thereby forming a recessed portion in a part of the semiconductor substrate surface from which the LOCOS film has been removed. A side wall spacer is formed to cover a side surface of the gate electrode such that a bottom surface of the side wall spacer contacts a surface of the recessed portion. A drain region and a source region are formed by doping a impurity to the semiconductor substrate surface on either side of the gate electrode and the side wall spacer. | 09-23-2010 |
20100233877 | Method of disposing dummy pattern - A method of disposing a dummy pattern includes the steps of obtaining an inter-wiring parasitic capacity and a wiring total parasitic capacity for each wiring using wiring layout data and initial dummy pattern layout data; creating a first data base based on the inter-wiring parasitic capacity; creating a second data base based on the wiring total parasitic capacity; performing dynamic and static simulations for creating a third data base storing the results of the dynamic and static simulations, the result of the dynamic simulation being information about the first wiring, and the result of the static simulation being information about the second wiring; and performing an additional insertion of dummy pattern near a third wiring, the third wiring being determined to be a wiring which is capable of be affected by voltage noise based on the data in the third data base. | 09-16-2010 |
20100221908 | Manufacturing method of semiconductor device - Disclosed is a method of manufacturing a semiconductor device that does not have a defect, such as wire breakage, due to an uplifted portion created at a rewiring pattern in a multilayer wire structure. Before a wiring layer is formed on an insulation layer, the insulation layer is exposed via a mask. The mask has a weak exposure part and a strong exposure part. The mask is positioned such that the weak exposure part corresponds to an arrangement position of a wire line of an underlying wiring layer, and such that the strong exposure part corresponds to an arrangement position of a via part of the underlying wiring layer. The underlying wiring layer is a layer immediately below the insulation layer. | 09-02-2010 |
20100219525 | Semiconductor device - Disclosed is a semiconductor device having improved heat dissipation efficiency. The semiconductor device includes a silicon interposer having a first surface and a second surface opposite the first surface. A plurality of semiconductor chips are provided on the first surface side of the silicon interposer. The silicon interposer has a plurality of via holes extending from the first surface to the second surface. An N type semiconductor and a P type semiconductor constituting a Peltier element are provided in each two of the via holes. | 09-02-2010 |
20100216311 | Trench forming method - A trench forming method for forming trenches without creating gouges at the boundary between a masking oxide film and a semiconductor layer and at the boundary between an oxide film insulating layer and the semiconductor layer, includes at least three etching steps each using, as the etching gas, one of at least two types of etching gases that respectively contain different components. | 08-26-2010 |
20100214277 | OUTPUT CIRCUIT AND DRIVING CIRCUIT FOR DISPLAY DEVICE - The present invention provides an output circuit that can suppress a voltage drop in an output section of the output circuit and that can suppress a phase delay of an output signal which is feedbacked to an input section of the output circuit. An AC component of a data signal output from an output terminal of an operational amplifier to which an input signal is input, is negatively feedbacked via a capacitor, and is input to an inverting input terminal of the operational amplifier. A DC component of the data signal output from the output terminal, is lowered its potential by a second protective resistor to the same potential as the input signal and is output as an output signal to data lines via respective output pads, and is output to an inverting input terminal of the operational amplifier via a first protective resistor. | 08-26-2010 |
20100213963 | SEMICONDUCTOR INTEGRATED CIRCUIT TEST METHOD - A wafer of semiconductor integrated circuits with wafer-level chip-scale packages is tested in two stages. The chip-scale packages include conductive posts extending through a sealing layer and capped by terminals. Measurements strongly affected by contact resistance are carried out before the terminals are formed, using a first probe card having probe pins that contact the ends of the conductive posts. Other measurements are carried out after the terminals are formed, using a second probe card having probe pins that contact the terminals. Accurate measurements can be made in this way even if the terminals are lead-free solder bumps with variable contact resistance. Fabrication yields are improved accordingly. | 08-26-2010 |
20100213615 | Semiconductor device - One wiring width of upper and lower wiring paths formed facing each other sandwiching an interlayer insulating film is large, and another wiring width is small; and the wiring widths of mutually adjacent wiring paths are formed to be large and small in alternating fashion on the same wiring layer. | 08-26-2010 |
20100210103 | Method of manufacturing semiconductor device - There is provided a method of manufacturing a semiconductor device including: preparing a semiconductor substrate, forming a first insulating layer, a first redistribution layer, a second insulating layer, a second redistribution layer, and at least one of first processing, in which, after the first electrically conductive material is filled in the first opening to form a first via interconnect, the first redistribution layer is formed on the first insulating layer with the first electrically conductive material such that the first redistribution layer is electrically connected to the first via interconnect; or second processing, in which, after the second electrically conductive material is filled in the second opening to form a second via interconnect, the second redistribution layer is formed on the second insulating layer with the second electrically conductive material such that the second redistribution layer is electrically connected to the second via interconnect. | 08-19-2010 |
20100208220 | Aligner and self-cleaning method for aligner - When a self-cleaning method for an aligner is carried out, a reflecting plate having a convex lens portion is set in an original plate holder, and exposure light rays are irradiated from a light source. The surface of the lens portion is coated with a reflective film. The light rays are reflected by the reflecting plate, diffused, and emitted onto the surface of a condenser lens, thereby breaking down and removing contaminants that are adhered to the surface of the condenser lens. The light rays also enter the interior of the condenser lens to clean away contaminants that are adhered to locations other than a normal exposure path. When a concave mirror and/or a reflecting plate having 50% transmittance is used as the reflecting plate, the emission range of the light rays (i.e., the locations that are cleaned) can be changed. | 08-19-2010 |
20100203723 | Semiconductor device and method of manufacturing semiconductor device - There is provided a method of manufacturing a semiconductor device, the method including performing at least one of: processing, when forming the first redistribution layer, of forming the first electrically conductive material layer by growing the first electrically conductive material using electroplating, and polishing the first resist film and the first electrically conductive material layer from the main surface side to flatten their surfaces; and processing, when forming the second redistribution layer, forming the second electrically conductive material layer by growing the second electrically conductive material using electroplating, and polishing the second resist film and the second electrically conductive material layer from the main surface side to flatten their surfaces. | 08-12-2010 |
20100201401 | DECODER CIRCUIT - The present invention provides a decoder circuit that can prevent the delay of decoder output. Namely, a switch that is put into an ON state when a node A of an NMOS region is not an output channel of a selected gradation voltage, is connected to the node A. Thus, a voltage raised by electric charges being accumulating by a coupling capacity C | 08-12-2010 |
20100201391 | APPARATUS AND METHOD FOR TESTING SEMICONDUCTOR DEVICES - A test apparatus for testing semiconductor integrated circuits includes a test head, a probe card holder for detachably holding a probe card that probes a semiconductor device, a heater for heating the probe card, and a heater holder that holds the heater in direct contact with the probe card when the probe card is held by the probe card holder. The test apparatus heats the probe card efficiently and thereby reduces test time and cost. | 08-12-2010 |
20100197079 | SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate-such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder. | 08-05-2010 |
20100196136 | PROBE CARD MAINTENANCE METHOD - An improved probe card maintenance method is capable of accurately, rapidly, and easily performing the maintenance of a probe card. The probe card is a jig adapted to test the electrical properties of semiconductor integrated circuits. The electrical properties of the semiconductor integrated circuits are tested at a predetermined test temperature. The probe card has a plurality of probes thereon. The probe card maintenance method includes heating the probe card and the probes on the probe card to the same temperature as the test temperature. The method also includes adjusting positions and postures of the defective probes while maintaining the temperature of the probe card and the probes at the test temperature. | 08-05-2010 |
20100194201 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY CIRCUIT - A semiconductor integrated circuit device includes a power supply circuit that generates one or more internal supply voltages from an external supply voltage, and one or more functional circuits that operate on the one or more internal supply voltages. A step-down converter in the power supply circuit generates one or more stepped-down voltages from the external supply voltage. A control circuit in the power supply circuit compares the external supply voltage with a reference voltage and selects the internal supply voltages from among the external supply voltage and the stepped-down voltages according to the result of the comparison. The semiconductor integrated circuit device can accordingly operate on different external power supplies, and can continue to operate on battery power even if the battery voltage drops. | 08-05-2010 |
20100190338 | Method for manufacturing semiconductor device - An insulator layer is formed on a part of semiconductor substrate to form an isolation layer that insulates and separates active elements from each other in the first region, and to form a dummy portion which is composed of a base material of the semiconductor substrate exposed in the insulator layer in a second region. Active elements are formed in the first region. A silicide layer is formed on the first and second regions excluding at least a portion in which the TSV electrode should be formed. At least one TSV hole extending from a reverse surface side of the semiconductor substrate to an electrode pad via the second region is formed. A conductive film is formed on the inner wall of the TSV hole to form a TSV electrode electrically connected to the electrode pad. | 07-29-2010 |
20100188159 | OSCILLATOR CIRCUIT - There is provided an oscillator circuit including: a current source; a resonant unit; an oscillation amplification unit connected to the current source while being connected in parallel to the resonant unit; a feedback resistor connected in parallel to the oscillation amplification unit; a bypass resistor having a resistance lower than a resistance of the feedback resistor; a switch unit connected between the feedback resistor and the bypass resistor, and configured to switch to the feedback resistor or the bypass resistor; and a control unit configured to control the switch unit such that a current from the current source is bypassed to the bypass resistor during a predetermined oscillation starting period, and to control the switch unit such that the current from the current source flows to the feedback resistor after the predetermined oscillation starting period has ended. | 07-29-2010 |
20100188156 | OSCILLATOR CIRCUIT - There is provided an oscillator circuit including: a current source; a resonant unit; an oscillation amplification unit connected to the current source and connected in parallel to the resonant unit; a feedback resistor connected in parallel to the oscillation amplification unit; a switch unit having a first end connected to the current source side of the oscillation amplification unit; a replica circuit connected between a second end of the switch unit and a ground side of the oscillation amplification unit and having a configuration identical to a configuration of the oscillation amplification unit; and a level detecting unit that detects an input voltage of the oscillation amplification unit, and, when the detected input voltage is higher than a bias voltage level at a time of oscillation, cause the switch unit to allow a current from the current sources to bypass through the replica circuit. | 07-29-2010 |
20100187639 | Semiconductor device and fabrication method - A semiconductor device has a semiconductor substrate in which first and second wells are formed. The substrate and wells are of the same conductivity type, but the second well has a higher impurity concentration than the first well. High-voltage MOS transistors are formed in the first well, and a low-voltage MOS transistor is formed in the second well. The high-voltage MOS transistors include a first transistor having a gate oxide layer with a first thickness and a second transistor having a gate oxide layer with a second thickness less than the first thickness. The low-voltage MOS transistor has a third gate oxide layer with a third thickness less than the first thickness. The second high-voltage MOS transistor provides efficient current conduction. | 07-29-2010 |
20100182094 | CONSTANT CURRENT DRIVEN OSCILLATING CIRCUIT - There is provided a constant current driven oscillating circuit including: an oscillator with first and second ends; a first field effect transistor that turns ON when a signal of a lower level than a first threshold voltage is input to a first gate terminal, and outputs, from a second terminal, current that has been input from a first terminal; a second field effect transistor turning ON when a signal output from the oscillator and is at a higher level than a second threshold voltage is input to a second gate terminal connected to the second end of the oscillator, and outputs, from a fourth terminal, current that has been input from a third terminal connected to the second terminal and to the first end of the oscillator; and an adjusting section that adjusts the first threshold voltage according to the level of the signal output from the oscillator. | 07-22-2010 |
20100182088 | OPERATIONAL AMPLIFIER - An operational amplifier has an input stage that branches a first current according to first and second input signals. An output stage generates an output signal from a second current and one of the branch currents in the input stage. A first transistor supplies the first current to the input stage. A second transistor supplies the second current to the output stage. A first gate line supplies a first bias potential to the gate terminal of the first transistor. A second gate line supplies a second bias potential to the gate terminal of the second transistor. The first gate line and the second gate line are electrically isolated from each other, preventing unwanted feedback of the output signal to the input stage by leakage through the gate lines. | 07-22-2010 |
20100181616 | Semiconductor device and method of manufacturing the same - A semiconductor device where a plurality of DMOS transistors formed in a distributed manner on a semiconductor substrate can operate without being destroyed and a method of manufacturing the same. The on/off threshold voltage of a DMOS transistor at the innermost position from among three or more DMOS transistors formed in a distributed manner on a semiconductor is greater than the on/off threshold voltage of a DMOS transistor at the outermost position. | 07-22-2010 |
20100151628 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - An improved manufacturing method for semiconductor devices is provided. This method can prevent chips and cracks from being generated when the rear face of the semiconductor substrate is polished. The manufacturing method includes preparing a semiconductor substrate having a front face and a rear face. The front face has an inner surface area and a peripheral surface area. Circuit elements are provided in the inner surface area of the semiconductor substrate. The manufacturing method also includes sealing the circuit elements with circuit sealing resin. The manufacturing method also includes providing cured resin in the peripheral surface area of the semiconductor substrate. The manufacturing method also includes polishing the rear face of the semiconductor substrate after the circuit sealing step. The manufacturing method also includes cutting the semiconductor substrate after the substrate polishing step so as to obtain semiconductor devices. | 06-17-2010 |
20100146309 | SEMICONDUCTOR DEVICE FOR SUPPLYING POWER SUPPLY VOLTAGE TO SEMICONDUCTOR DEVICE - A semiconductor device includes first, second and third power supply terminals respectively supplied with first, second and third power supply voltages. The semiconductor device also includes a first terminal connectable to a host device and a second terminal connectable to a peripheral device. The semiconductor device also includes a first circuit block connected to the first terminal and the first power supply terminal and receiving data output from the host device based on the first power supply voltage, a second circuit block connected to the second terminal and the third power supply terminal and receiving data output from the peripheral device based on the third power supply voltage, and a third circuit block connected to the second power supply terminal and controlling operation of the first circuit block and the second circuit block based on the second power supply voltage. | 06-10-2010 |
20100144142 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, forms connection pads electrically connected to integrated circuit portion formed in a semiconductor substrate, lays an insulating film and a protective film one over another, forms sub-lines electrically connected to the connection pads on the protective film, forms a coating film covering the sub-lines and the protective film, sticks a dry film onto the coating film, forms external connection electrodes externally connectable and electrically connected to the sub-lines, and removes the dry film and forms a sealing layer covering the coating film and side surfaces of the external connection electrodes. | 06-10-2010 |
20100141935 | Light amount measuring apparatus - A light amount measuring apparatus including a light amount measuring circuit and a power supply for supplying power to the light amount measuring circuit; wherein the light amount measuring circuit includes a light receiving device for receiving light and outputting an electric signal corresponding to light amount of the received light; a first switch for switching between electrical connection and disconnection between the light receiving device and the power supply; and a drive controller for controlling the first switch so that the first switch electrically connects the light receiving device to the power supply when the light receiving device is set to an activated state and electrically disconnects the light receiving device from the power supply when the light receiving device is set to a deactivated state. | 06-10-2010 |
20100141660 | IMAGE RENDERING PROCESSING DEVICE AND METHOD - An image rendering processing device includes an expanding section, a signal output section, and a writing section. The expanding section reads out font data corresponding to the character code indicated in image rendering data and expands the font data into a size corresponding to horizontal and vertical pixel numbers of the image rendering data. The signal output section (a) reads out a valid range corresponding to the character code, (b) adjusts the valid range based on the pixels of the expanded font data, and counts the pixels in the expanded font data along the specific direction, and (c) outputs a valid signal indicating that a given pixel corresponds to the valid range when a counted pixel number matches the pixel number of a pixel corresponding to the valid range. The writing section writes the pixel that corresponds to the pixel number which is counted when the valid signal is output. | 06-10-2010 |
20100140787 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE FOR USE THEREIN, AND MANUFACTURING METHOD THEREOF - A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin. | 06-10-2010 |
20100136760 | Silicon Carbide Semiconductor Device and Manufacturing Method Thereof - A silicon carbide semiconductor device is fabricated by forming an amorphous layer in a semiconductor layer of a silicon carbide substrate at a boundary between a cell forming area and an outer peripheral area, forming an outer peripheral insulating film over the semiconductor layer in the outer peripheral area, and thermally oxidizing an upper surface of the semiconductor layer in the cell forming area and at least a portion of the amorphous layer exposed by the outer peripheral insulating film to form a gate oxide film including a stepped portion of increased thickness adjacent the outer peripheral insulating film. The gate electrode layer is then formed which extends from the gate oxide film to above the outer peripheral insulating film. | 06-03-2010 |
20100134938 | SEMICONDUCTOR DEVICE WITH ESD PROTECTION FUNCTION AND ESD PROTECTION CIRCUIT - A semiconductor device with an ESD protection function has an SOI substrate, first to fourth diffusion layers, and a gate. The SOI substrate has a semiconductor layer on an insulation layer. The first diffusion layer is of a first conductivity type and is formed on the semiconductor layer. The second diffusion layer is of the first conductivity type and is formed on the semiconductor layer. The third diffusion layer is of a second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first and second diffusion layers. The fourth diffusion layer is of the second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first diffusion layer and electrically connected to the second diffusion layer. The gate is formed over the third diffusion layer. | 06-03-2010 |
20100130258 | Gravity axis determination apparatus and mobile terminal apparatus using the same - A gravity axis determination apparatus which can determine the gravity direction in a short time. The apparatus is low in cost and has a simple construction. Data values of acceleration data trains in a same time zone are mutually compared and one of the three axes is determined as a gravity axis. | 05-27-2010 |
20100128830 | DATA TRANSFER SYSTEM - A data transfer system which can surely transfer data between two function circuits which operate synchronously with different clock frequencies. A data loading signal is generated just before timing when edges of two clocks of different frequencies coincide. Only information data received by the function circuit on a transfer data reception side within an existence period of the data loading signal is determined to be valid. | 05-27-2010 |
20100128027 | DISPLAY PANEL DRIVING VOLTAGE OUTPUT CIRCUIT - A driving voltage output circuit for a matrix display panel includes high-side voltage followers and low-side voltage followers. Each voltage follower includes a differential input stage, a control stage, and an output stage. First and second transistors in the differential input stage receive non-inverting and inverting inputs and produce first and second potentials that control the control stage. Third and fourth transistors of different channel types in the control stage are connected in a push-pull configuration between high-side and low-side power supply potentials to generate a control potential. Fifth and sixth transistors of identical channel types in the output stage are connected in series between an intermediate reference potential and one of the power supply potentials, and are controlled by the first potential and the control potential to generate an output potential. The output potential is fed back as the inverting input. | 05-27-2010 |
20100128026 | DISPLAY PANEL DRIVING APPARATUS - A display panel driving apparatus supplies pixel driving potentials corresponding to pixel data to the source lines of a display panel. The pixels are located at the intersections of the source lines and a set of scanning lines. For each pixel, the driving potentials are alternately positive and negative with respect to a common reference potential supplied to the display panel. While the display driving apparatus is latching the pixel data for the pixels on each scanning line, the output circuits of the display driving apparatus are disconnected from the source lines, allowing the source lines to return to the common reference potential, thereby avoiding unwanted current flows in the output circuits and unwanted distortion of the pixel driving waveforms. | 05-27-2010 |
20100128018 | DISPLAY PANEL DRIVING VOLTAGE OUTPUT CIRCUIT - A driving voltage output circuit for a matrix display panel includes high-side voltage followers and low-side voltage followers. Each voltage follower includes a differential input stage, a control stage, and an output stage. The differential input stage receives non-inverting and inverting inputs and produces first and second potentials. The control stage generates third and fourth potentials from the first and second potentials. The output stage includes three transistors connected respectively to the high-side power supply, the low-side power supply, and an intermediate reference potential, and connected in common to an output terminal. Two of the three transistors are of identical channel type and are controlled by the first and fourth potentials. The third transistor is of the opposite conductive type and is controlled by the third potential. | 05-27-2010 |
20100124267 | APPARATUS AND METHOD FOR DETECTING INTERFERENCE WAVE - An interference wave detecting apparatus includes a first Fourier transformer for frequency-converting a received signal using Fourier transform; an extractor for extracting a known information signal from the frequency-converted received signal; an interpolator for performing interpolation to the known information signal in frequency domain, thereby generating a first transmission path estimation signal as a frequency-domain information signal; an inverse Fourier transformer for inverse-Fourier-transforming the known information signal, thereby generating a time-domain information signal; a waveform shaping section for shaping a waveform of the time-domain information signal; a second Fourier transformer for Fourier-transforming the shaped time-domain information signal, thereby generating a second transmission path estimation signal as a frequency-domain information signal; and a comparing-computing section for comparing the first and second transmission path estimation signals, thereby generating an interference wave detection result which indicates a ratio of an interference wave of the received signal. | 05-20-2010 |
20100123835 | RADIO LSI DEVICE AND INTERFERING WAVE DETECTING CIRCUIT - A radio LSI device includes an interfering wave detecting circuit that receives an RSSI signal for a current transmit/receive channel. The interfering wave detecting circuit includes a field intensity determiner that determines whether or not the value of the RSSI signal is greater than a predetermined threshold value. The interfering wave detecting circuit also includes a duration counter that counts the duration of an interfering wave whose RSSI value is greater than the predetermined threshold value. The interfering wave detecting circuit also includes a duration comparator that, if the duration exceeds a duration comparative value, generates an interrupt signal. The radio LSI device changes the setting of the current transmit/receive channel in response to the interrupt signal. | 05-20-2010 |
20100123472 | Probe card and test method using the same - A test method of a semiconductor device using a probe card includes the steps of performing a self-test and performing a normal-mode test. In the self-test, a quality of the semiconductor device is examined while connecting the first probe needle to the first signal terminal of the semiconductor device, and using the tester connected to the connection terminal. In the normal-mode test, a quality of the semiconductor device is examined while connecting the second probe needle to the second signal terminal of the semiconductor device, and using the tester connected to the connection terminal. | 05-20-2010 |
20100117176 | Camera module and manufacturing method thereof - A manufacturing method of a camera module includes steps of: forming a wafer assembly of a semiconductor wafer and a light transmissible optical wafer which are fixed to each other, wherein the semiconductor wafer has an array of plural sensor units each having a light receiving unit of a photoelectric conversion element, and wherein the light transmissible optical wafer has an array of plural lens units, the lens units being opposite to the respective sensor units while each pair of the lens unit and the sensor unit faces each other across a space, so that the semiconductor wafer and the light transmissible optical wafer are adhered at circumferences of the respective pair of the lens unit and the sensor unit with a spacer unit, cutting the wafer assembly at the spacer unit to individually divide the wafer assembly into a plurality of camera modules each comprising a sensor chip and a lens chip bonded to each other by a spacer, forming a light shieldable mask film to determine a lens aperture of each of the plural lens units on the light transmissible optical wafer; forming a groove in the light transmissible optical wafer of the wafer assembly such that the groove reaches the spacer unit and filling the groove with a light shieldable resin to form a light shieldable resin layer; and cutting the light shieldable resin layer at a width less than the groove to individually divide the camera modules in each of which the light shieldable resin layer is provided at a side of the lens chip. | 05-13-2010 |
20100109114 | Semiconductor device and manufacturing method thereof - A semiconductor device manufacturing method includes etching a silicon on insulator (SOI) from its surface (i.e., semiconductor substrate layer) to form a first trench and a second trench. The first trench extends through the SOI substrate and reaches an electrode pad. The second trench terminates in the semiconductor substrate layer. The manufacturing method also includes forming an insulation film that covers the surface of the semiconductor substrate layer as well as the side walls and bottoms of the first and second trenches. The manufacturing method also includes removing the insulation film from the bottoms of the first and second trenches to expose the electrode pad from the first trench bottom and to expose the semiconductor substrate layer from the second trench bottom. The manufacturing method also includes forming a conductive film that covers the semiconductor substrate layer and the side walls and the bottoms of the first and second trenches to form a through via electrically connected to the electrode pad at the first trench bottom and to form a contact part electrically connected to the semiconductor substrate layer at the second trench bottom. The manufacturing method also includes patterning the conductive film on the semiconductor substrate layer to form the external electrodes and to form a potential fixing external electrode electrically connected to the contact part. | 05-06-2010 |