| OCZ TECHNOLOGY GROUP, INC. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120117309 | NAND FLASH-BASED SOLID STATE DRIVE AND METHOD OF OPERATION - A solid state drive that uses over-provisioning of NAND flash memory blocks as part of housekeeping functionality, including deduplication and coalescence of data for efficient usage of NAND flash memory devices and maintaining sufficient numbers of erased blocks to promote write performance. | 05-10-2012 |
| 20120033370 | PCIe BUS EXTENSION SYSTEM, METHOD AND INTERFACES THEREFOR - A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port. | 02-09-2012 |
| 20120011424 | MEMORY SYSTEM AND METHOD FOR GENERATING AND TRANSFERRING PARITY INFORMATION - A memory system and method for generating and transferring parity information within burst transactions of burst read and write transfers and without dedicated parity chips or parity data lines. | 01-12-2012 |
| 20110320690 | MASS STORAGE SYSTEM AND METHOD USING HARD DISK AND SOLID-STATE MEDIA - Methods and systems for mass storage of data over two or more tiers of mass storage media that include nonvolatile solid-state memory devices, hard disk devices, and optionally volatile memory devices or nonvolatile MRAM in an SDRAM configuration. The mass storage media interface with a host through one or more PCIe lanes on a single printed circuit board. | 12-29-2011 |
| 20110283043 | LARGE CAPACITY SOLID-STATE STORAGE DEVICES AND METHODS THEREFOR - Non-volatile storage devices and methods capable of achieving large capacity solid state drives containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and a memory controller. The bank switching circuitry is integrated onto the memory controller and functionally interposed between the banks of memory devices and the front end of the memory controller. The bank switching circuitry operates to switch accesses by the memory controller among the at least two banks. | 11-17-2011 |
| 20110258355 | MODULAR MASS STORAGE DEVICES AND METHODS OF USING - A modular mass storage device suitable for use with computers and other processing apparatuses. The mass storage device includes a controller board having a system interface connector, a memory controller, a cache device, and a second connector. The mass storage device further includes a daughter board having at least one non-volatile memory device for data storage, a read-only memory device containing firmware of the mass storage device, and a daughter board connector configured to mate with the second connector of the controller board and thereby form command, address and data paths between the memory controller and the memory device of the daughter board. The memory controller and the memory device are configured so that the memory controller reads the firmware of the read-only memory device when the daughter board connector is mated with the second connector of the controller board. | 10-20-2011 |
| 20110255337 | FLASH MEMORY DEVICE AND METHOD OF OPERATION - A NAND flash memory device and method of erasing memory cells thereof, wherein each cell is only subjected to the level of erase voltage needed to restore its nominal “erased” state. Each memory cell of the NAND flash memory device comprises a floating gate, a control gate connected to a wordline and receives a control voltage therefrom to induce a programming charge on the floating gate, and a bitline adapted to apply an erase voltage to deplete the floating gate of the programming charge. Each memory cell further includes circuitry for modulating the erase voltage according to the level of the programming charge on its floating gate. | 10-20-2011 |
| 20110231730 | MASS STORAGE DEVICE AND METHOD FOR OFFLINE BACKGROUND SCRUBBING OF SOLID-STATE MEMORY DEVICES - A solid-state mass storage device and method for its operation that includes performing preemptive scrubbing of data during offline periods or disconnects from a host system to which the mass storage device is attached. The device includes a system interface adapted to connect the drive to a host system, at least one nonvolatile memory device, controller means through which data pass when being written to and read from the memory device, a volatile memory cache, a system logic device, and an integrated power source for powering the drive. The system logic device is configured to operate when the drive is not functionally connected to a host system, execute copy commands without accessing a host system, and prioritize preemptive scrubbing of addresses in the memory device on the basis of risk of data loss based on one or more parameters logged by the internal system logic device. | 09-22-2011 |
| 20110231637 | CENTRAL PROCESSING UNIT AND METHOD FOR WORKLOAD DEPENDENT OPTIMIZATION THEREOF - A central processing unit (CPU) adapted for use in a computing system, such as a personal computer or other processing apparatus. The CPU is implemented to perform hyper-threading (HT), and further enables switching between HT-enabled and HT-disabled modes on the fly (without rebooting the apparatus) based on, for example, performance measurements or entries into a local library. | 09-22-2011 |
| 20110208900 | METHODS AND SYSTEMS UTILIZING NONVOLATILE MEMORY IN A COMPUTER SYSTEM MAIN MEMORY - Methods and systems capable of capitalizing on fast access capabilities (low initial access latencies) of nonvolatile memory technologies for use in a host system, such as computers and other processing apparatuses. The host system has a central processing unit, processor cache, and a system main memory. The system main memory includes first and second memory slots, a volatile memory subsystem having at least one DRAM-based memory module received in the first memory slot and addressed by the central processing unit, and a nonvolatile memory subsystem having at least a first nonvolatile-based memory module in the second memory slot and addressed by the central processing unit. At least one memory controller is integrated onto the central processing unit for controlling the processor cache, the volatile memory subsystem, and the nonvolatile memory subsystem. | 08-25-2011 |
| 20110173484 | SOLID-STATE MASS STORAGE DEVICE AND METHOD FOR FAILURE ANTICIPATION - A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases. | 07-14-2011 |
| 20110173378 | COMPUTER SYSTEM WITH BACKUP FUNCTION AND METHOD THEREFOR - A solid-state mass storage device and method of anticipating a failure of the mass storage device resulting from a memory device of the mass storage device reaching a write endurance limit. A procedure is then initiated to back up data to a second mass storage device prior to failure. The method includes assigning at least a first memory block of the memory device as a wear indicator, using other memory blocks of the memory device as data blocks for data storage, performing program/erase (P/E) cycles and wear leveling on the data blocks, subjecting the wear indicator to more P/E cycles than the data blocks, performing integrity checks and monitoring the bit error rate of the wear indicator, and taking corrective action if the bit error rate increases, including the initiation of the backup procedure and generating a request to replace the device. | 07-14-2011 |
| 20110173372 | METHOD AND APPARATUS FOR INCREASING FILE COPY PERFORMANCE ON SOLID STATE MASS STORAGE DEVICES - A mass storage device and method that utilize storage memory and a shadow memory capable of increasing the speed associated with copying data from one location to another location within the storage memory without the need to access a host computer for the copy transaction. A controller of the mass storage device receives a file copy request for a file to be copied between first and second locations within the storage memory. Data from the first location within the storage memory is then loaded into a shadow memory means of the mass storage device, and then the data is written from the shadow memory means to the second location within the storage memory. | 07-14-2011 |
| 20110138113 | RAID STORAGE SYSTEMS HAVING ARRAYS OF SOLID-STATE DRIVES AND METHODS OF OPERATION - RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value. | 06-09-2011 |
| 20110119462 | METHOD FOR RESTORING AND MAINTAINING SOLID-STATE DRIVE PERFORMANCE - A method of maintaining a solid-state drive so that free space within memory blocks of the drive becomes free usable space to the drive. The drive comprises cells organized in pages that are organized in memory blocks in which at least user files are stored. A defragmentation utility is executed to cause at least some of the memory blocks that are partially filled with data and contain file fragments to be combined or aligned and to cause at least some of the memory blocks that contain only invalid data to be combined or aligned. A block consolidation utility is then executed to eliminate at least some of the partially-filled blocks by consolidating the file fragments into a fewer number of the memory blocks. The consolidation utility also increases the number of memory blocks that contain only invalid memory. All of the memory blocks containing only invalid data are then erased. | 05-19-2011 |
| 20110110158 | MASS STORAGE DEVICE WITH SOLID-STATE MEMORY COMPONENTS CAPABLE OF INCREASED ENDURANCE - A mass storage device that utilizes one or more solid-state memory components to store data for a host system, and a method for increasing the write endurance of the memory components. The memory components are periodically heated above an intrinsic operating temperature thereof to a preselected temperature that is sufficient to thermally recondition the memory component in a manner that increases the write endurance of the memory component. | 05-12-2011 |
| 20110102997 | MASS STORAGE DEVICE AND METHOD OF ACCESSING MEMORY DEVICES THEREOF - A mass storage device configured to enable accessing of an array of solid-state memory devices on the storage device in the event of a memory controller failure on the storage device. The storage device includes a printed circuit board, an array of non-volatile solid-state memory devices on the printed circuit board, a system interface connector on the printed circuit board and adapted to connect the mass storage device to a host system, and an onboard memory controller on the printed circuit board and adapted to communicate between the host system and the memory devices. The mass storage device further includes an auxiliary connector on the printed circuit board that is separate from and in addition to the system interface connector. The auxiliary connector provides a direct path for accessing the memory devices that is separate from the onboard memory controller. | 05-05-2011 |
| 20110084978 | COMPUTER SYSTEM AND PROCESSING METHOD UTILIZING GRAPHICS PROCESSING UNIT WITH ECC AND NON-ECC MEMORY SWITCHING CAPABILITY - Computer systems and methods that utilize a GPU whose operation is able to switch between ECC and non-ECC memory operations on demand. The computer system includes a graphics processing unit and a memory controller and local memory that are functionally integrated with the graphics processing unit. The memory controller has at least two operating modes comprising a first memory access mode that uses error checking and correction when accessing the local memory, and a second memory access mode that does not use error checking and correction when accessing the local memory. The memory controller is further operable to switch the operation of the memory controller between the first and second memory access modes without rebooting the computer system. | 04-14-2011 |
| 20110069526 | HIGH PERFORMANCE SOLID-STATE DRIVES AND METHODS THEREFOR - A nonvolatile storage device adapted for use with computers, workstations and other processing apparatuses. The storage device includes a printed circuit board, a nonvolatile memory array comprising at least two sub-arrays that contain nonvolatile solid-state memory devices, and control circuitry for interfacing with the processing apparatus. The control circuitry includes an abstraction layer and at least two memory control units configured to communicate data, address and control signals with the sub-arrays of the memory devices. A bus connects each memory control unit to a corresponding one of the sub-arrays. The control circuitry further includes a crossbar switch that functionally connects each memory control unit to the abstraction layer. The storage device is capable of overcoming limitations of current SSD designs by enabling independent read and write transfers (accesses) to the memory devices of the storage device, including concurrent read and write accesses. | 03-24-2011 |
| 20110060869 | LARGE CAPACITY SOLID-STATE STORAGE DEVICES AND METHODS THEREFOR - Non-volatile storage devices and methods capable of achieving large capacity SSDs containing multiple banks of memory devices. The storage devices include a printed circuit board, at least two banks of non-volatile solid-state memory devices, bank switching circuitry, a connector, and optionally a memory controller. The bank switching circuitry is functionally interposed between the banks of memory devices and either the connector or the memory controller. The bank switching circuitry operates to switch accesses by a system logic or the memory controller among the at least two banks. | 03-10-2011 |
| 20110053429 | CONNECTOR ASSEMBLY AND METHOD FOR SATA DRIVES - A connector assembly and method suitable for making data and power connections with mass storage devices that use the SATA interface standard. The connector assembly includes a connector having a pair of oppositely-disposed surfaces, a face between the surfaces, and data and power connector portions disposed in the face. The data and power connector portions are adapted to establish data and power connections between the connector and a SATA interface of a mass storage device. The connector assembly further has data and power cables for transmitting, respectively, data and power through the data and power connector portions of the connector. Opposing clips protrude from the oppositely-disposed surfaces of the connector and project beyond the face of the connector. The clips engage opposing sides of the mass storage device and mechanically stabilize the data and power connections between the connector and the SATA interface of the mass storage device. | 03-03-2011 |
| 20110047421 | NAND FLASH-BASED STORAGE DEVICE WITH BUILT-IN TEST-AHEAD FOR FAILURE ANTICIPATION - A test-ahead feature for non-volatile memory-based mass storage devices to anticipate device failure. The test-ahead feature includes a method performed with a solid-state mass storage device having a controller, a cache memory, and at least one non-volatile memory device. At least a first block is reserved on the at least one non-volatile memory device as a wear-indicator block and a plurality of second blocks are used for data storage. Information is stored corresponding to the number of write and erase cycles encountered by the second blocks during usage of the mass storage device, and the information is accessed to perform wear leveling among the second blocks. The wear-indicator blocks are subjected to an offset number of write and erase cycles in excess of the number of write and erase cycles encountered by the second blocks, after which an integrity check of the first block is performed. | 02-24-2011 |
| 20110047322 | METHODS, SYSTEMS AND DEVICES FOR INCREASING DATA RETENTION ON SOLID-STATE MASS STORAGE DEVICES - Methods, systems and devices for increasing the reliability of solid state drives containing one or more NAND flash memory arrays. The methods, systems and devices take into account usage patterns that can be employed to initiate proactive scrubbing on demand, wherein the demand is automatically generated by a risk index that can be based on one or more of various factors that typically contribute to loss of data retention in NAND flash memory devices. | 02-24-2011 |
| 20110044086 | OPTICAL MEMORY DEVICE AND METHOD THEREFOR - A nonvolatile memory device and method using phase changes in a substrate to alter optical properties of the substrate for the purpose of data storage. The memory device includes a substrate containing a phase change material having phases comprising amorphous and crystalline phases. The phase change material has optical properties that change depending on whether the phase change material is in the amorphous phase or the crystalline phase. The memory device is further equipped with one or more devices that generate light and transmit the light into the substrate, and one or more devices that cause the phase change material to change between the amorphous and crystalline phases thereof. At least one optical sensing device detects light that passes into the phase change material to the optical sensing device and generates electrical signals based thereon, which are converted into bit values if they exceed a threshold. | 02-24-2011 |
| 20110004728 | ON-DEVICE DATA COMPRESSION FOR NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES - A non-volatile memory-based mass storage device that includes a host interface attached to a package, at least one non-volatile memory device within the package, a memory controller connected to the host interface and adapted to access the non-volatile memory device in a random access fashion through a parallel bus, a volatile memory cache within the package, and co-processor means within the package for performing hardware-based compression of cached data before writing the cached data to the non-volatile memory device in random access fashion and performing hardware-based decompression of data read from the non-volatile memory device in random access fashion. | 01-06-2011 |
| 20100325352 | HIERARCHICALLY STRUCTURED MASS STORAGE DEVICE AND METHOD - A hierarchically-structured computer mass storage system and method. The mass storage system includes a mass storage memory drive, control logic on the mass storage memory drive that includes a controller and one or more devices for executing a hierarchical storage management technique, a volatile memory cache configured to be accessed by the control logic, and first and second non-volatile storage arrays on the mass storage memory drive and comprising, respectively, first and second non-volatile memory devices. The first and second non-volatile memory devices have properties including access times and write endurance, and at least one of the access time and the write endurance of the first non-volatile memory devices is faster or higher, respectively, than the second non-volatile memory devices. Desired data storage localities on the storage arrays are determined through access patterns and selectively utilizing the properties of the memory devices to match the data storage requirements. | 12-23-2010 |
| 20100312953 | METHOD AND APPARATUS FOR REDUCING WRITE CYCLES IN NAND-BASED FLASH MEMORY DEVICES - A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping. | 12-09-2010 |
| 20100296240 | METHOD AND APPARATUS FOR THERMAL MANAGEMENT OF COMPUTER MEMORY MODULES - A heat spreader and method for thermal management of a computer memory module by promoting natural convection cooling of the memory module. The heat spreader includes a frame surrounding a planar body adapted to be mounted to a memory module of a computer, and a grid defined in the planar body by a plurality of uniformly distributed perforations. The perforations extend through the planar body to allow natural convention between an interior space beneath the planar body and an exterior space above the planar body. | 11-25-2010 |
| 20100296236 | MASS STORAGE DEVICE FOR A COMPUTER SYSTEM AND METHOD THEREFOR - A method and mass storage device that combine multiple solid state drives (SSDs) to a single volume. The device includes a carrier board and at least two solid state drives having power and data connections to the carrier board. The carrier board includes a circuit board functionally connected to a control logic and at least two secondary connectors that are disposed at different edges of the circuit board and functionally connected to the control logic. The solid state drives are connected to the carrier board through the secondary connectors, and each solid state drive has a power and data connector directly connected to one of the secondary connectors of the carrier board. The solid state drives are oriented substantially parallel to the carrier board and to each other. | 11-25-2010 |
| 20100241799 | MODULAR MASS STORAGE SYSGTEM AND METHOD THEREFOR - A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors. | 09-23-2010 |
| 20100142247 | MEMORY MODULES AND METHODS FOR MODIFYING MEMORY SUBSYSTEM PERFORMANCE - Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component. | 06-10-2010 |
| 20100069780 | METHOD AND APPARATUS FOR USING BIOPOTENTIALS FOR SIMULTANEOUS MULTIPLE CONTROL FUNCTIONS IN COMPUTER SYSTEMS - A biosignal-computer-interface apparatus and method. The apparatus includes one or more devices for generating biosignals based on at least one physiological parameter of an individual, and a computer-interface device capable of performing multiple tasks, including converting the biosignals into at least one input signal, establishing a scale encompassing different levels of the input signal, multiplying the input signal into parallel control channels, dividing the scale into multiple zones for each of the parallel control channels, assigning computer commands to each individual zone of the multiple zones, and generating the computer command assigned to at least one of the individual zones if the level of the input signal is within the at least one individual zone. The individual zones can be the same or different among the parallel control channels. | 03-18-2010 |
| 20090037900 | METHOD FOR OPTIMIZING MEMORY MODULES FOR USER-SPECIFIC ENVIRONMENTS - A method for altering and preferably optimizing the performance of system memory of a computer system. The method includes identifying the motherboard and the memory module of the computer system, and then searching multiple SPD update files associated with multiple motherboards and containing data corresponding to physical and operational characteristics of multiple memory modules. From these SPD update files, a compatible SPD update file is identified that is compatible with the motherboard and contains data corresponding to physical and operational characteristics of the memory module. Thereafter, a software utility is used to erase pre-existing SPD data stored on the SPD circuit device and then write and verify installation of the data of the compatible SPD update file on the SPD circuit device. New SPD settings for the memory module are then enabled based on the data of the compatible SPD update file. | 02-05-2009 |
| 20090009475 | WIRELESS COMPUTER MOUSE WITH BATTERY SWITCHING CAPABILITY - A wireless mouse suitable for use with a computing device, and method of using such a mouse. The mouse includes a housing, electronics within the housing for sensing movement of the mouse and wirelessly communicating with the computing device, at least two batteries within the housing, a device for monitoring a power level of each of the batteries, and a device for switching between the batteries to deliver electrical power from one of the batteries to the electronics. Each battery is adapted for individually powering the electronics, and the switching device operates to switch from a first of the batteries to a second of the batteries when the power level of the first battery sensed by the monitoring device drops below a preset depletion threshold value. | 01-08-2009 |
| 20080291630 | METHOD AND APPARATUS FOR COOLING COMPUTER MEMORY - A method and apparatus for cooling chips on a computer memory module. The apparatus includes a primary and secondary heat spreaders, at least a first heatpipe coupled to the primary heat spreader and having a remote portion spaced apart from the primary heat spreader and thermally contacting the secondary heat spreader, and a coolant within the first heatpipe and the primary heat spreader so as to absorb heat from the primary heat spreader and conduct the heat to the secondary heat spreader. The primary heat spreader has at least two panels configured to engage the memory module therebetween, with facing contact surfaces of the panels adapted for thermal contact with the module chips. The secondary heat spreader is configured to increase surface dissipation of heat from the first heatpipe into the environment. The coolant has a boiling point at or below a maximum preselected operating temperature of the module chips. | 11-27-2008 |
| 20080222349 | IEEE 1394 INTERFACE-BASED FLASH DRIVE USING MULTILEVEL CELL FLASH MEMORY DEVICES - A flash drive and method of transferring data from a system to a flash drive. The flash drive includes a casing, a plurality of flash memory devices within the casing, each of the flash memory devices having multilevel cells, an IEEE 1394 interface controller within the casing, coupled to the flash memory devices, and interfacing with the flash memory devices for interleaved multichannel access to and from at least two of the flash memory devices, and at least one IEEE 1394 interface connector projecting from the casing for interfacing the flash memory devices with a system through the controller. The method entails coupling a plurality of multilevel cell flash memory devices to a system through an IEEE 1394 interface controller and at least one IEEE 1394 interface connector, and performing interleaved multichannel access to and from at least two of the flash memory devices. | 09-11-2008 |
