NVIDIA CORPORATION Patent applications |
Patent application number | Title | Published |
20160063676 | Image Scaling Techniques - Image scaling techniques, in accordance with embodiments of the present technology, include directionally interpolating blocks of pixel data of an image, sharpening the directional interpolated blocks of pixel data, and optionally clamping the sharpened, directional interpolated blocks of pixel data. | 03-03-2016 |
20160062390 | Adjusting Clock Frequency - One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a current efficiency of the at least one processor. The clock frequency controller is further configured to receive a request from the processor for a target number of processor instructions to be handled in a particular time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency in dependence thereon. | 03-03-2016 |
20150339209 | DETERMINING OVERALL PERFORMANCE CHARACTERISTICS OF A CONCURRENT SOFTWARE APPLICATION - One embodiment of the present invention includes a dependency extractor and a dependency investigator that, together, facilitate performance analysis of computer systems. In operation, the dependency extractor instruments a software application to generate run-time execution data for each work task. This execution data includes per-task performance data and dependency data reflecting linkages between tasks. After the instrumented software application finishes executing, the dependency investigator evaluates the captured execution data and identifies the critical path of tasks that establishes the overall run-time of the software application. Advantageously, since the execution data includes both task-level performance data and dependencies between tasks, the dependency investigator enables the developer to effectively optimize software and hardware in computer systems that are capable of concurrently executing tasks. By contrast, conventional performance analysis may not correctly identify critical paths in software applications that execute tasks in parallel across multiple processing units and, consequently, may misdirect optimization efforts. | 11-26-2015 |
20150255365 | MICROELECTRONIC PACKAGE PLATE WITH EDGE RECESSES FOR IMPROVED ALIGNMENT - A microelectronic package includes a package substrate with at least one semiconductor die mounted thereon and a plate coupled to the package substrate. The plate is configured with a first recess formed in a first edge of the plate and a second recess formed in a second edge of the plate wherein the first edge and the second edge are formed on opposing sides of the plate. One advantage of the above-described embodiments is that a stiffener plate or heat spreader that is sized to cover most or all of the periphery of a package substrate can be coupled to the package substrate without causing alignment issues in subsequent fabrication processes. | 09-10-2015 |
20150253373 | DYNAMIC YIELD PREDICTION - Dynamic yield prediction. In accordance with a first method embodiment of the present invention, a computer-implemented method includes collecting sample test information from a plurality of test-only structures prior to completion of the first wafer, gathering finished test data from all die of the first wafer, after completion of the first wafer, constructing a yield prediction model based on the sample test information and on the finished test data, and predicting, using the model, a percentage of die of the first wafer that will meet a particular specification. The method may further include a feedback loop to dynamically update the model. | 09-10-2015 |
20150243610 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A HIGH BANDWIDTH BOTTOM PACKAGE - A system, method, and computer program product are provided for producing a high bandwidth bottom package of a die-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer and an integrated circuit die that is coupled to the top layer of the substrate material. A first set of pads is formed on the top layer of the substrate material and a layer of dielectric material is applied on a top surface of the bottom package to cover the integrated circuit die and the first set of pads. | 08-27-2015 |
20150243233 | TECHNIQUES FOR AVOIDING AND REMEDYING DC BIAS BUILDUP ON A FLAT PANEL VARIABLE REFRESH RATE DISPLAY - A method for driving a display panel having a variable refresh rate is disclosed. The method comprises receiving a current input frame from an image source. Next, it comprises determining a number of re-scanned frames to insert between the current input frame and a subsequent input frame, wherein the re-scanned frames repeat the input frame, and wherein the number of re-scanned frames depends on the minimum refresh interval (MRI) of the display panel. Further, it comprises calculating respective intervals at which to insert the re-scanned frames between the current input frame and the subsequent input frame. Subsequently, it comprises determining if a charge accumulation in pixels of the display panel has crossed over a predetermined threshold value. Finally, responsive to a determination that the charge accumulation has crossed over a predetermined threshold value, it comprises performing a counter-measure to remediate the charge accumulation. | 08-27-2015 |
20150243048 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING ONE-DIMESIONAL SEARCHES IN TWO-DIMENSIONAL IMAGES - A system, method, and computer program product are provided for implementing a search of a digital image along a set of paths. The method includes the steps of selecting a set of paths in an image and identifying at least one feature pixel in the set of paths by comparing gradients for each of the pixels in the set of paths. The set of paths includes at least one line of pixels in the image, and a total number of pixels in the set of paths is less than half of a number of pixels in the image. | 08-27-2015 |
20150241976 | WEARABLE FINGER RING INPUT DEVICE AND CONTROLLER - Systems and methods for remotely providing user input to different electronic devices based on user finger motions and/or gestures. A universal user input device assembles a motion sensor, control logic, a memory and a processor into a substantially ring-shaped housing that is wearable on a finger of a user. The input device can identify an associated external device, establish a communication channel therewith, and provide user input instructions to the external device based on user's finger motions or gestures. The motion sensor can detect the finger's motions and/or gestures and generate corresponding detection signals which are converted into instruction signals recognizable by the external device. The instruction signals are communicated to the external device through a wireless communication channel. The input device may include a projector that can optically project a graphic user interface to an external surface as a visual guide for user's finger motions or gestures. | 08-27-2015 |
20150235695 | WRITE ASSIST SCHEME FOR LOW POWER SRAM - A write-assist memory includes a memory supply voltage and a column of SRAM cells that is controlled by a pair of bit lines, during a write operation. Additionally, the write-assist memory includes a write-assist unit that is coupled to the memory supply voltage and the column of SRAM cells and has a separable conductive line located between the pair of bit lines that provides a collapsible SRAM supply voltage to the column of SRAM cells based on a capacitive coupling of a control signal in the pair of bit lines, during the write operation. A method of operating a write-assist memory is also provided. | 08-20-2015 |
20150235681 | PSEUDO-DIFFERENTIAL READ SCHEME FOR DUAL PORT RAM - A memory read system includes a memory column having a plurality of dual port memory cells that are controlled by separate read word lines and a read bit line structure organized into upper and lower read bit line portions. Additionally, the memory read system also includes a pseudo-differential memory read unit coupled to the read bit line structure, wherein the upper and lower read bit line portions respectively control corresponding upper and lower local bit lines to provide a global bit line for the memory column. A method of reading a memory is also included. | 08-20-2015 |
20150234963 | INTERFACE ANALYSIS FOR VERIFICATION OF DIGITAL CIRCUITS - A method for performing an interface analysis. The method includes identifying a first module included in a representation of a digital circuit. The method also includes identifying a first output port associated with the first module. The method further includes identifying a first logic path that extends from the first output port. The method also includes determining that the first logic path extends to a first storage element included in the first module. The method further includes including the first module, the first output port, the first logic path, and the first storage element in interface logic output data. | 08-20-2015 |
20150229921 | INTRA SEARCHES USING INACCURATE NEIGHBORING PIXEL DATA - One embodiment of the present invention sets forth a technique for performing an intra search. The technique includes performing a first intra search based on a first block size associated with a first pixel block included in a video frame to determine a first intra mode. The technique further includes reconstructing the first pixel block based on the first intra mode to generate reconstructed pixel data. The technique further includes performing, based on the reconstructed pixel data, a second intra search based on a second block size associated with a second pixel block included in the video frame. The second block size is smaller than the first block size. The technique further includes determining a second intra mode based on the second intra search. Advantageously, the disclosed technique enables an intra search to be performed based on a previous intra search size, enabling intra searches to be performed in parallel. | 08-13-2015 |
20150229879 | SYSTEM AND METHOD FOR CREATING A VIDEO FRAME FROM A SINGLE VIDEO FIELD - A system and method of producing a frame of a video image from an interlaced field. In one embodiment, the method includes: (1) creating an equal-intensity trace from present samples in the field, (2) recognizing an equal-intensity path in the equal-intensity trace, (3) at least partially straightening the equal-intensity path and (4) using the equal-intensity path to determine an intensity value for a missing sample in the frame. | 08-13-2015 |
20150229848 | METHOD AND SYSTEM FOR GENERATING AN IMAGE INCLUDING OPTICALLY ZOOMED AND DIGITALLY ZOOMED REGIONS - A method for generating images. The method includes capturing first image data representing a first scene taken optically at a first magnification index, wherein the first image data comprises a first region of an image. The method includes capturing second image data representing a second scene taken optically at a second magnification index that is less than the first magnification index, wherein the second image data comprises a second region of the image. The method includes digitally zooming the second image data in the second region to the first magnification index. The method includes digitally stitching the second image data in the second region to the first image data in the first region. | 08-13-2015 |
20150229311 | OSCILLATOR FREQUENCY DIVIDER WITH IMPROVED PHASE NOISE - A gated divider circuit includes a windowing unit configured to generate windowing waveforms from input oscillator waveforms having a fixed duty cycle. Additionally, the gated divider circuit includes a gated output unit coupled to the windowing unit and configured to provide selected ones of the input oscillator waveforms as controlled by corresponding selected ones of the windowing waveforms. Also included are a method of operating a gated divider circuit and a frequency conversion system employing a gated divider circuit as a local oscillator divider. | 08-13-2015 |
20150228226 | POWER-EFFICIENT STEERABLE DISPLAYS - A method for angularly varying backlight illumination of a backlit display device. The method comprises determining at least one subject position and angularly varying a backlight illumination of a displayed image. The backlight illumination is angularly varied based upon and directed towards a determined position of the at least one subject. The angularly varied backlight illumination of the displayed image reduces the backlight illumination of the displayed image that is visible outside of the determined position of the at least one subject. | 08-13-2015 |
20150228055 | LIQUID CRYSTAL DISPLAY OVERDRIVE INTERPOLATION CIRCUIT AND METHOD - A liquid crystal display (LCD) overdrive interpolation circuit and method, and an LCD drive system incorporating the circuit or method. In one embodiment, the circuit includes: (1) a diagonal interpolator operable to perform a diagonal interpolation along a diagonal direction in a lookup table based on TO and FROM gray levels and (2) a further interpolator coupled to the diagonal interpolator and operable to perform a further interpolation based on a result of the diagonal interpolation and the FROM gray level. | 08-13-2015 |
20150228046 | AUTOMATICALLY PERFORMING A TRADE-OFF BETWEEN VISUAL QUALITY AND LATENCY DURING RENDERING OF A VIDEO/GRAPHICS SEQUENCE - A method includes automatically capturing, through a processor of a data processing device communicatively coupled to a memory, one or more parameter(s) related to a visual quality of rendering of a video frame that is part of a sequence on a display unit communicatively coupled to the processor and one or more parameter(s) related to latency associated with the rendering of the video frame on the display unit. The sequence is a video and/or a graphics sequence. The method also includes performing, through the processor, an automatic trade-off between the one or more parameter(s) related to the visual quality and the one or more parameter(s) related to the latency to maintain the one or more parameter(s) related to the visual quality or the one or more parameter(s) related to the latency within a threshold during the rendering of the video frame. | 08-13-2015 |
20150222284 | SYSTEM AND METHOD FOR DYNAMIC FREQUENCY ESTIMATION FOR A SPREAD-SPECTRUM DIGITAL PHASE-LOCKED LOOP - A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first value and the errors accumulated in the second segment accumulator while the use-selection signal has a second value. | 08-06-2015 |
20150222266 | LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE - A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF). | 08-06-2015 |
20150221123 | SYSTEM AND METHOD FOR COMPUTING GATHERS USING A SINGLE-INSTRUCTION MULTIPLE-THREAD PROCESSOR - Systems for, and methods of, computing gathers for processing on a SIMT processor. In one embodiment, the system includes: (1) a thread group creator executing on a processor and operable to assign ray traces pertaining to a single receiver to threads for execution by a SIMT processor and (2) a memory configured to contain at least some of the threads for execution by the SIMT processor. | 08-06-2015 |
20150220675 | SYSTEM AND METHOD FOR ROUTING BUFFERED INTERCONNECTS IN AN INTEGRATED CIRCUIT - A system and method for routing a buffered interconnect in an IC from a source cell to a target cell thereof. In one embodiment, the system includes: (1) a path tracer operable to designate the source cell as a current node and construct a path toward the target node by: (1a) defining a boundary about the current node based on a buffer driving length, (1b) trimming the boundary by any blockage therein to yield a candidate area for placing a buffer, (1c) dividing the boundary into line segments, (1d) selecting a closest, valid one of the line segments to the target cell as the current node and (1e) repeating the defining, trimming, dividing and selecting the closest, valid one until the current node lies within the buffer driving length and (2) a buffer placer associated with the path tracer and operable to select a location along the path to place the buffer. | 08-06-2015 |
20150220341 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING SOFTWARE-BASED SCOREBOARDING - A system, method, and computer program product are provided for implementing a software-based scoreboarding mechanism. The method includes the steps of receiving a dependency barrier instruction that includes an immediate value and an identifier corresponding to a first register and, based on a comparison of the immediate value to the value stored in the first register, dispatching a subsequent instruction to at least a first processing unit of two or more processing units. | 08-06-2015 |
20150220314 | CONTROL FLOW OPTIMIZATION FOR EFFICIENT PROGRAM CODE EXECUTION ON A PROCESSOR - A method includes identifying a divergent region of interest (DRI) not including a post dominator node thereof within a control flow graph, and introducing a decision node in the control flow graph such that the decision node post-dominates an entry point of the DRI and is dominated by the entry point. The method also includes redirecting a regular control flow path within the control flow graph from another node previously coupled to the DRI to the decision node, and redirecting a runaway path from the another node to the decision node. Further, the method includes marking the runaway path to differentiate the runaway path from the regular control flow path, and directing control flow from the decision node to an originally intended destination of each of the regular control flow path and the runaway path based on the marking to provide for program thread synchronization and optimization within the DRI. | 08-06-2015 |
20150219697 | INTEGRATED CIRCUIT DETECTION CIRCUIT FOR A DIGITAL MULTI-LEVEL STRAP AND METHOD OF OPERATION THEREOF - An integrated circuit (IC) based detection circuit for determining a strap value and a method of detecting a digital strap value. In one embodiment, the detection circuit includes: (1) a first receiver including transistors having first electrical characteristics that define a first threshold for the first receiver, the first receiver operable to generate a first binary digit based on an input signal and the first threshold and (2) a second receiver including transistors having second electrical characteristics that differ from the first electrical characteristics and define a second threshold for the second receiver that is lower than the first threshold, the second receiver operable to generate a second binary digit based on the input signal and the second threshold, the first and second binary digits indicating whether the strap value lies above the first threshold, between the first and second thresholds or below the second threshold. | 08-06-2015 |
20150216066 | INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY - One aspect of the present disclosure provides an IC package that includes a printed circuit board (PCB) having a first material layer located thereon. The first material layer has bond pads located therein that form a contact array defined by a perimeter. A second material layer is located at or adjacent an outer edge of the PCB. The second material layer is located outside the perimeter of the contact array and has a higher coefficient of thermal expansion (CTE) value and a greater thickness than the first material layer. | 07-30-2015 |
20150215512 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A QUANTITY OF LIGHT RECEIVED BY AN ELEMENT OF A SCENE - A system, method, and computer program product are provided for determining a quantity of light received by an element of a scene. In use, a quantity of light received by a first element of the scene is determined by averaging a quantity of light received by elements of the scene that are associated with a selected set of light paths. | 07-30-2015 |
20150214963 | PHASE LOCK LOOP (PLL/FLL) CLOCK SIGNAL GENERATION WITH FREQUENCY SCALING TO POWER SUPPLY VOLTAGE - A clock signal generation circuit provides an output clock signal to a digital system. The digital system is powered by a power supply voltage, VDD, that may include transients associated with the impedance of the packaged digital system. The clock signal generation circuit dynamically scales an output clock frequency based on monitored changed to VDD. The output clock frequency may be selected to approximate a maximum (margin-less) system Fmax for the monitored VDD. The average clock frequency may be improved compared with operating at a fixed output clock frequency. | 07-30-2015 |
20150213855 | MODE-CHANGEABLE DUAL DATA RATE RANDOM ACCESS MEMORY DRIVER WITH ASYMMETRIC OFFSET AND MEMORY INTERFACE INCORPORATING THE SAME - A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of | 07-30-2015 |
20150213786 | METHOD FOR CHANGING A RESOLUTION OF AN IMAGE SHOWN ON A DISPLAY - Provided is a method for changing a resolution of an image shown on a display. The method, in one embodiment, includes, providing an image on a display, and detecting a relative distance of an object to the display. The method, in this embodiment, further includes changing a resolution of the image as the relative distance changes. | 07-30-2015 |
20150213776 | COMPUTING SYSTEM AND METHOD FOR AUTOMATICALLY MAKING A DISPLAY CONFIGURATION PERSISTENT - A computing system and method for automatically making a display configuration persistent. One embodiment of the computing system includes: (1) a video adapter coupled to a data bus and operable to interface a display configuration associated with extended display identification data (EDID), (2) a cache configured to store the EDID, and (3) a central processing unit (CPU) coupled to the data bus and the cache, and operable to execute a driver associated with the video adapter and configured to detect the display configuration and cause the EDID to be written to the cache. | 07-30-2015 |
20150213752 | ADJUSTABLE SCREEN DISPLAY SIZE FOR AN ELECTRONIC DEVICE - One aspect provides a method for image display. The method for image display, in accordance with one embodiment, includes providing a display, the display having a maximum display area (A | 07-30-2015 |
20150213638 | HIERARCHICAL TILED CACHING - One embodiment of the present invention includes a method for processing graphics objects. The method includes receiving a first draw-call and a second draw-call. The method also includes dividing the first draw-call into a first set of sub-draw-calls and the second draw-call into a second set of sub-draw-calls. The method further includes identifying a first screen tile. The method also includes identifying a first group of sub-draw-calls included in the first set of sub-draw-calls that overlap the first screen tile and a second group of sub-draw-calls included in the second set of sub-draw-calls that overlap the second screen tile. The method further includes causing the first group of sub-draw-calls and the second group of sub-draw-calls to be processed together. | 07-30-2015 |
20150213303 | IMAGE PROCESSING WITH FACIAL REFERENCE IMAGES - Systems and methods are provided for capturing and processing digital images. During a capture session, an image capture system is configured to capture one or more subject images and one or more calibration images potentially containing the user's face under common lighting conditions. The subject images and the calibration images are captured using two differently-aimed cameras within a common enclosure. The one or more calibration images are compared to one or more previously-captured reference images containing the user's face and captured under specified lighting conditions. The comparison yields one or more calibration outputs that are applied to the one or more subject images to generate adjusted subject images, for example, images that have been white-balanced to remove color casts caused by the lighting conditions. | 07-30-2015 |
20150212933 | METHODS FOR REDUCING MEMORY SPACE IN SEQUENTIAL OPERATIONS USING DIRECTED ACYCLIC GRAPHS - Various disclosed embodiments are directed to methods and systems for reducing memory space in sequential computer-implemented operations. The method includes generating a directed acyclic graph (DAG) having a plurality of vertices and directed edges, wherein each edge connects a predecessor vertex to a successor vertex. Each vertex represents one of the computer-implemented operations and each directed edge represents output data generated by the operations. The method includes merging one of the predecessor vertex with one of the successor vertex by combining the operations of the predecessor vertex and the successor vertex if the predecessor and successor vertices are connected by a directed edge and there is only one directed edge originating from the predecessor vertex. The merger of the predecessor and the successor vertices reduces the number of directed edges in the DAG, resulting in a reduction of intermediate buffer memory required to store the output data. | 07-30-2015 |
20150212890 | GRAPHICS PROCESSING SUBSYSTEM AND METHOD FOR RECOVERING A VIDEO BASIC INPUT/OUTPUT SYSTEM - A graphics processing subsystem and a method for recovering a video basic input/output system (VBIOS). One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a VBIOS, and (2) a processor coupled to the memory and configured to employ a bridge to gain access to the VBIOS and cause the VBIOS to be written to the memory. | 07-30-2015 |
20150212819 | SYSTEM AND PROCESSOR FOR IMPLEMENTING INTERRUPTIBLE BATCHES OF INSTRUCTIONS - A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution. | 07-30-2015 |
20150212815 | METHODS AND SYSTEMS FOR MAINTENANCE AND CONTROL OF APPLICATIONS FOR PERFORMANCE TUNING - Methods and systems for maintenance and control of multiple versions of an application are disclosed. The method includes creating a first version of the application comprising computer-executable instructions and executing the first version of the application. The first version of the application and related performance metrics are stored in a memory. The method includes creating at least one modified version of the application by making changes to the computer-executable instructions and executing the modified version of the application. The modified version of the application and related performance metrics are stored in the memory. The method includes comparing the performance of the modified version of the application to the performance of the first version of the application by comparing their respective performance metrics and deleting the lower performing version. | 07-30-2015 |
20150212631 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MULTIPLE STIMULUS SENSORS FOR AN INPUT DEVICE - A system, method, and computer program product are provided for sensing input stimulus at an input device. The method includes the steps of configuring an input device comprising a first sensor layer and a second sensor layer to activate the first sensor layer and to deactivate the second sensor layer, where the second sensor layer is layered above the first sensor layer and associated with a stimulus device. When a request to activate the second sensor layer is received, the input device is configured to activate the second sensor layer to respond to stimulus received by the stimulus device and to deactivate the first sensor layer. A third sensor layer may be included in the input device and the third sensor layer may be associated with a different stimulus device. | 07-30-2015 |
20150212601 | STYLUS TOOL WITH DEFORMABLE TIP - A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a chisel shaped tip disposed at the first end of the body is provided. The chisel shaped tip includes a deformable material such that the chisel shaped tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the chisel shaped tip. The chisel shaped tip is operable to interface with the touch sensitive surface with a second detectable surface area, this one different from the first detectable surface area, when a second pressure is exerted on the body and translated to the chisel shaped tip. The stylus may include a second tip on the back end for providing an erase function. | 07-30-2015 |
20150212600 | STYLUS TOOL WITH DEFORMABLE TIP - A passive stylus with a deformable tip is described herein. In one embodiment, a thin annular body configured to be hand-held with a tip disposed at the first end of the body is provided. The tip includes a deformable material such that the tip is operable to interface with a touch a sensitive surface with a detectable surface area when a first pressure is exerted on the body and translated to the tip. The tip is operable to interface with the touch sensitive surface with a second detectable surface area, this one different from the first detectable surface area, when a second pressure is exerted on the body and translated to the tip. The stylus may include a second tip on the back end for providing an erase function. | 07-30-2015 |
20150212569 | USER SPACE BASED PERFORMANCE STATE SWITCHING OF A PROCESSOR OF A DATA PROCESSING DEVICE - A method includes capturing an interaction of a user of a data processing device therewith at a level of a user space through a process executing on the data processing device, and communicating the captured user interaction as an event from the user space to a kernel space associated with an operating system executing on the data processing device. The method also includes incorporating, through the kernel space, the communicated event as a feedback to an algorithm executing on a processor of the data processing device communicatively coupled to a memory. The algorithm is configured to modify a current performance state of the processor based on threshold levels of utilization of the processor. Further, the method includes automatically switching, based on the algorithm execution, the current performance state of the processor to a higher power state or a lower power state thereof additionally in accordance with the communicated event. | 07-30-2015 |
20150212154 | METHODS AND APPARATUS FOR DEBUGGING LOWEST POWER STATES IN SYSTEM-ON-CHIPS - Methods and apparatus for debugging finite state machine are disclosed. The method includes implementing a debug logic circuit and connecting the debug logic circuit to a system on chip (SoC) voltage source. The method includes operating a finite state machine that sequences the SoC from a low power state to a next low power state and generating respective output signals corresponding to the low power states and wherein the finite state machine is connected to Always On voltage source. The method includes masking the output signals to generate respective masked output signals, and applying the masked output signals to SoC circuit elements to prevent from transitioning into low power states and hence keeping the debug logic circuitry alive. The method includes debugging the finite state machine in the lowest power state by the debug logic circuit. | 07-30-2015 |
20150212149 | DEGRADATION DETECTOR AND METHOD OF DETECTING THE AGING OF AN INTEGRATED CIRCUIT - A degradation detector for an integrated circuit (IC), a method of detecting aging in an IC and an IC incorporating the degradation detector or the method. In one embodiment, the degradation detector includes: (1) an offline ring oscillator (RO) coupled to a power gate and a clock gate, (2) a frozen RO coupled to a clock gate, (3) an online RO and (4) an analyzer coupled to the offline RO, the frozen RO and the online RO and operable to place the degradation detector in a normal state in which the offline RO is disconnected from both the drive voltage source and the clock source, the frozen RO is connected to the drive voltage source but disconnected from the clock source and the online RO is connected to both the drive voltage source and the clock source. | 07-30-2015 |
20150209662 | CLOUD GAMING SYSTEM AND METHOD OF INITIATING A GAMING SESSION - A gaming cloud gaming system and a method of initiating a gaming session. One embodiment of the gaming cloud gaming system includes a computing system having: (1) an entry point operable to receive a game session request and generate instructions for establishing a connection between a client and a game server, and (2) a dynamically configurable reverse proxy operable to proxy for the game server and configured to employ the instructions to create a route to a randomly selected port on the game server through which the connection is makeable. | 07-30-2015 |
20150208354 | SYSTEM AND METHOD FOR EXTENDING BATTERY LIFE OF A MOBILE DEVICE PROVIDING CONTENT WIRELESSLY TO A REMOTE DISPLAY - A system for, and method of, extending the battery life of a mobile device providing content wirelessly and a mobile device incorporating the system or the method. In one embodiment, the system includes: (1) a power manager operable to generate a signal indicating that a low battery condition exists and (2) an audio/video subsystem operable to receive the signal and adjust at least one parameter controlling an encoding of the content to decrease a quality of the encoding. | 07-23-2015 |
20150208079 | ADAPTIVE FRAME TYPE DETECTION FOR REAL-TIME LOW-LATENCY STREAMING SERVERS - An enhanced display encoder system for a video stream source includes an enhanced video encoder that has parallel intra frame and inter frame encoding units for encoding a video frame, wherein an initial number of macroblocks is encoded to determine a scene change status of the video frame. Additionally, a video frame history unit determines an intra frame update status for the video frame from a past number of video frames, and an encoder selection unit selects the intra frame or inter frame encoding unit for further encoding of the video frame to support a wireless transmission based on the scene change status and the intra frame update status. A method of enhanced video frame encoding for video stream sourcing is also provided. | 07-23-2015 |
20150208075 | MEMORY MANAGEMENT OF MOTION VECTORS IN HIGH EFFICIENCY VIDEO CODING MOTION VECTOR PREDICTION - In one embodiment of the present invention, a high efficiency video coding codec optimizes the memory resources used during motion vector (MV) prediction. As the codec processes block of pixels, known as coding units (CUs), the codec performs read and write operations on a fixed-sized neighbor union buffer representing the MVs associated with processed CUs. In operation, for each CU, the codec determines the indices at which proximally-located “neighbor” MVs are stored within the neighbor union buffer. The codec then uses these neighbor MVs to compute new MVs. Subsequently, the codec deterministically updates the neighbor union buffer—replacing irrelevant MVs with those new MVs that are useful for computing the MVs of unprocessed CUs. By contrast, many conventional codecs not only redundantly store MVs, but also retain irrelevant MVs. Consequently, the codec reduces memory usage and memory operations compared to conventional codecs, thereby decreasing power consumption and improving codec efficiency. | 07-23-2015 |
20150208072 | ADAPTIVE VIDEO COMPRESSION BASED ON MOTION - One embodiment of the present invention sets forth a technique for adaptively compressing video frames. The technique includes monitoring a motion vector associated with a video stream and encoding a first plurality of video frames included in the video stream based on a first video compression algorithm to generate first encoded video frames. The technique further includes determining that the motion vector has reached a threshold level and, in response, switching from the first video compression algorithm to a second video compression algorithm. The technique further includes encoding a second plurality of video frames included in the video stream based on the second video compression algorithm to generate second encoded video frames. Advantageously, the disclosed technique enables a video compression algorithm to be dynamically selected based on an amount of motion detected in a video stream that is to be compressed. | 07-23-2015 |
20150207988 | INTERACTIVE PANORAMIC PHOTOGRAPHY BASED ON COMBINED VISUAL AND INERTIAL ORIENTATION TRACKING - A panoramic image is generated from a plurality of source images. A panoramic analysis engine samples a first source image and a second source image included in the plurality of source images to generate a first proxy image and a second proxy image, respectively. The panoramic analysis engine samples inertial measurement information associated the two proxy images. The panoramic analysis engine detects a feature that is present in both the first proxy image and the second proxy image. The panoramic analysis engine blends the second proxy image into the first proxy image based on the inertial measurement information and a first position of the feature within the second proxy image relative to a second position of the feature within the first proxy image to generate a preview image. Finally, the panoramic analysis engine renders the preview image according to a first panoramic mode to generate a first partial display image. | 07-23-2015 |
20150207975 | DCT BASED FLICKER DETECTION - One embodiment of the present invention sets forth a technique for reducing flicker in image frames captured with a rolling shutter. A flicker detection and correction engine selects a first channel from a first image frame for processing. The flicker detection and correction engine subtracts each pixel value in the first channel from a corresponding pixel value in a prior image frame to generate a difference image frame. The flicker detection and correction engine identifies a first alternating current (AC) component based on a discrete cosine transform (DCT) associated with the difference image frame. The flicker detection and correction engine reduces flicker that is present in the first image frame based on the first AC component. One advantage of the disclosed techniques is that the flicker resulting from fluctuating light sources is correctly detected and reduced or eliminated irrespective of the frequency of the fluctuating light source. | 07-23-2015 |
20150207501 | SYSTEM AND METHOD FOR A DYNAMIC VOLTAGE CONTROLLED OSCILLATOR - A system and method are provided for generating an adaptive clock signal, configured to track prevailing operating conditions within an integrated circuit. The method comprises transmitting a first signal edge to a row of cells within a memory instance, waiting for two or more selected cells within the row of cells to propagate corresponding responses based on the first signal edge, and generating a memory delay signature signal edge based on the corresponding responses. The adaptive clock signal is generated based on the delay signature signal edge. | 07-23-2015 |
20150207231 | CO-LOCATED ANTENNAS AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna system. The antenna system, in this aspect, includes a loop antenna element, the loop antenna element having a positive loop antenna terminal end and a negative loop antenna terminal end. The antenna system, in this embodiment, further includes an inverted-F antenna element co-located with the loop antenna element, the inverted-F antenna element having a positive inverted-F antenna terminal end and a negative inverted-F antenna terminal end located proximate the positive loop antenna terminal end and the negative loop antenna terminal end. In this antenna system embodiment, the positive loop antenna terminal end, negative loop antenna terminal end, positive inverted-F antenna terminal end and negative inverted-F antenna terminal end alternate between positive and negative terminals. | 07-23-2015 |
20150207230 | WIDEBAND LOOP ANTENNA AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna. In one aspect, the antenna includes a feed element having a first feed element end and a second feed element end, the first feed element end configured to electrically connect to a positive terminal of a transmission line. The antenna, in this aspect, further includes a loop antenna element having a first loop antenna element end and a second loop antenna element end, wherein the first loop antenna element end is coupled to the second feed element end and the second loop antenna element end is configured to electrically connect to a negative terminal of the transmission line. The antenna, of this aspect, further includes a monopole antenna element having a first monopole antenna element end and a second monopole antenna element end, wherein the first monopole antenna element end is coupled to the second feed element end. | 07-23-2015 |
20150207228 | SINGLE ELEMENT DUAL-FEED ANTENNAS AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna. The antenna, in this aspect, includes an inverted-F GPS antenna structure, the inverted-F GPS antenna structure embodying a GPS feed element, a GPS extending arm, and a ground element. The antenna, in this aspect, further includes a loop WiFi antenna structure, the loop WiFi antenna structure embodying a WiFi feed element, the ground element, and a WiFi connecting arm coupling the WiFi feed element to the ground element. In this particular aspect, the ground element is located between the GPS feed element and the WiFi feed element. | 07-23-2015 |
20150207219 | WIDEBAND ANTENNA AND AN ELECTRONIC DEVICE INCLUDING THE SAME - Provided is an antenna. The antenna, in one embodiment, includes a feed element having a first feed element end and a second feed element end, the first feed element end configured to electrically connect to a positive terminal of a transmission line. The antenna, in this embodiment, further includes a ground element having a first ground element end and a second ground element end, the first ground element end configured to electrically connect to a negative terminal of the transmission line. In this particular embodiment, the first ground element end is located proximate and inside the first feed element end, and the second ground element end is located proximate and outside the second feed element end. | 07-23-2015 |
20150206848 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A CAVITY PACKAGE-ON-PACKAGE STRUCTURE - A system, method, and computer program product are provided for producing a cavity bottom package of a package-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer including a first set of pads configured to be electrically coupled to a second set of pads of an integrated circuit die. A layer of non-conductive material is applied to the top layer of the bottom package and a cavity is formed in the layer of non-conductive material to expose the first set of pads, where the cavity is configured to contain the integrated circuit die oriented such that the second set of pads face the first set of pads. | 07-23-2015 |
20150206596 | MANAGING A RING BUFFER SHARED BY MULTIPLE PROCESSING ENGINES - A technique for managing data processed by multiple processing engines comprises storing a first data block associated with a first processing engine in a first portion of a ring buffer memory, subsequent to storing the first data block, storing a second data block associated with a second processing engine in a second portion of the ring buffer memory, and receiving a second process complete signal from the second processing engine while waiting for a first process complete signal from the first processing engine. The technique further comprises receiving the first process complete signal from the first processing engine once the first processing engine completes processing of the first data block, and, upon receiving the first process complete signal, indicating that the first portion of the ring buffer memory is available for storing data other than the first data block. | 07-23-2015 |
20150206577 | HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY - A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided. | 07-23-2015 |
20150206576 | NEGATIVE BIT LINE WRITE ASSIST FOR MEMORY ARRAY - A negative bit line write assist system includes an array voltage supply and a static random access memory (SRAM) cell that is coupled to the array voltage supply and controlled by bit lines during a write operation. Additionally, the negative bit line write assist system includes a bit line voltage unit that is coupled to the SRAM cell, wherein a distributed capacitance is controlled by a write assist command to provide generation of a negative bit line voltage during the write operation. A negative bit line write assist method is also provided. | 07-23-2015 |
20150206511 | LEVERAGING COMPRESSION FOR DISPLAY BUFFER BLIT IN A GRAPHICS SYSTEM HAVING AN INTEGRATED GRAPHICS PROCESSING UNIT AND A DISCRETE GRAPHICS PROCESSING UNIT - A graphics system includes an integrated graphics processor and a discrete graphics processing unit. An intra-system bus coupled data from the discrete graphics processing unit to the integrated graphics processor. In a high performance mode the discrete graphics processing unit is used to render frames. Compression techniques are used to aid in the data transfer over an intra-system bus interface. | 07-23-2015 |
20150206271 | SYSTEM AND METHOD FOR INCREASING A GRAPHICS PROCESSING CAPABILITY OF A MOBILE DEVICE - A system for, and method of, increasing a graphics processing capability of a mobile device and a mobile device incorporating the system or the method. In one embodiment, the system includes: (1) a graphics application programming interface (API) operable to cause a graphics processing resource of the mobile device to render data generated by an application to yield rendered data and (2) a network interface associated with the mobile device and operable to: (2a) transmit at least some of the rendered data via a network link for postprocessing to yield postprocessed data and (2b) receive the postprocessed data for display on the mobile device. | 07-23-2015 |
20150206270 | SYSTEM AND METHOD FOR WIRELESSLY SHARING GRAPHICS PROCESSING RESOURCES AND GPU TETHERING INCORPORATING THE SAME - A system and method for wirelessly sharing graphics processing resources and a mobile device incorporating the system or the method. In one embodiment, the system includes: (1) a call evaluator operable to receive a graphics call from an application and determine whether the call should be wirelessly directed to a shared graphics processing resource and (2) a tether interface associated with the call evaluator and operable to receive calls from the call evaluator that the call evaluator has determined should be wirelessly directed to the shared graphics processing resource and wirelessly direct the calls to the shared graphics processing resource. | 07-23-2015 |
20150205757 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR EXECUTING CASTING-ARITHMETIC INSTRUCTIONS - A system, method, and computer program product are provided for executing casting-arithmetic instructions. The method comprises receiving a casting-arithmetic instruction that specifies an arithmetic operation to be performed on input data and at least one casting operation of an input casting operation and an output casting operation. Upon determining that the casting-arithmetic instruction specifies the input casting operation, the input casting operation is performed on identified terms comprising the input data. Then the arithmetic operation is performed on the input data to generate an arithmetic result. Upon determining that the casting-arithmetic instruction specifies the output casting operation, the output casting operation is performed on the arithmetic result. | 07-23-2015 |
20150205711 | METHODS AND SYSTEMS FOR MONITORING AND LOGGING SOFTWARE AND HARDWARE FAILURES - Methods and systems monitor and log software and hardware failures (i.e. errors) over a communication network. In one embodiment, the method includes detecting an event caused by an error, and generating a log of the event in response to the detection. The method further includes generating a first message prompting if a user consents to allowing a third party provider track the error and transmitting the log to the third party provider over the communication network if the user consents to allowing the third party provider track the error. The method yet further includes generating a second message prompting if the user wants to provide additional information relating to the error. The method still further includes providing a user interface including an error reporting portal to the user if the user wants to provide additional information and transmitting the portal to the third party provider. | 07-23-2015 |
20150205636 | USING HIGH PRIORITY THREAD TO BOOST CPU CLOCK RATE - When a computing system is running at a lower clock rate, in response to an event that triggers the computing system to increase the clock rate, a list of threads pending execution by the computing system is accessed. The list includes a thread that, when executed, causes the clock rate to increase. That thread is selected and executed before any other thread in the list is executed. | 07-23-2015 |
20150205607 | TREE-BASED THREAD MANAGEMENT - In one embodiment of the present invention, a streaming multiprocessor (SM) uses a tree of nodes to manage threads. Each node specifies a set of active threads and a program counter. Upon encountering a conditional instruction that causes an execution path to diverge, the SM creates child nodes corresponding to each of the divergent execution paths. Based on the conditional instruction, the SM assigns each active thread included in the parent node to at most one child node, and the SM temporarily discontinues executing instructions specified by the parent node. Instead, the SM concurrently executes instructions specified by the child nodes. After all the divergent paths reconverge to the parent path, the SM resumes executing instructions specified by the parent node. Advantageously, the disclosed techniques enable the SM to execute divergent paths in parallel, thereby reducing undesirable program behavior associated with conventional techniques that serialize divergent paths across thread groups. | 07-23-2015 |
20150205606 | TREE-BASED THREAD MANAGEMENT - In one embodiment of the present invention, a streaming multiprocessor (SM) uses a tree of nodes to manage threads. Each node specifies a set of active threads and a program counter. Upon encountering a conditional instruction that causes an execution path to diverge, the SM creates child nodes corresponding to each of the divergent execution paths. Based on the conditional instruction, the SM assigns each active thread included in the parent node to at most one child node, and the SM temporarily discontinues executing instructions specified by the parent node. Instead, the SM concurrently executes instructions specified by the child nodes. After all the divergent paths reconverge to the parent path, the SM resumes executing instructions specified by the parent node. Advantageously, the disclosed techniques enable the SM to execute divergent paths in parallel, thereby reducing undesirable program behavior associated with conventional techniques that serialize divergent paths across thread groups. | 07-23-2015 |
20150205590 | CONFLUENCE ANALYSIS AND LOOP FAST-FORWARDING FOR IMPROVING SIMD EXECUTION EFFICIENCY - One embodiment of the present invention sets forth a method for causing thread convergence. The method includes determining that a control flow graph representing a first section of a program includes at least two non-overlapping paths that extend from a first divergent node to a candidate node. The method also includes determining that the first divergent node is not a dominator of the candidate node or that the candidate node is not a post-dominator of the first divergent node. The method further includes identifying an external node and inserting a first instruction configured to cause a predicate variable to be set to true for a first set of threads that is to execute the external node. The method additionally includes inserting into the program a second divergent node configured to cause various threads to execute or not execute a first control flow path associated with the external node. | 07-23-2015 |
20150205589 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPROVED POWER EFFICIENCY DURING PROGRAM CODE EXECUTION - A system, method, and computer program product are provided for compiling a computer program comprising arithmetic operations having different requirements with respect to numeric dynamic range, numeric resolution, or any combination thereof. The method comprises generating a transformed graph representation of the computer program by applying propagation rules that provide for relaxed numeric requirements, where applicable, and generating output code based on the transformed graph representation. Relaxing numeric requirements, such as dynamic range and resolution requirements, may advantageously lower power consumption during execution of the computer program. | 07-23-2015 |
20150205586 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR BULK SYNCHRONOUS BINARY PROGRAM TRANSLATION AND OPTIMIZATION - A system, method, and computer program product are provided for. The method includes the steps of executing a block of translated binary instructions by multiple threads and gathering profiling data during execution of the block of translated binary instructions. The multiple threads are then synchronized at a barrier instruction associated with the block of translated binary instructions and the block of translated binary instructions is replaced with optimized binary instructions, where the optimized binary instructions are produced based on the profiling data. | 07-23-2015 |
20150205572 | DETERMINATION AND APPLICATION OF AUDIO PROCESSING PRESETS IN HANDHELD DEVICES - One embodiment of the present invention sets forth techniques for selecting an audio environment for a handheld device. A widget detects a first input via a specially designated input mechanism. The widget enters an audio processing environment select mode based on the first input. The widget detects a second input via either the specially designated input mechanism or a second input mechanism. The widget changes an audio processing environment from a first setting to a second setting based on the second input. One advantage of the disclosed techniques is that users may change audio processing environments quickly and intuitively using existing input mechanisms such as a mute button, volume rocker control, and touch screen interface on a handheld device. | 07-23-2015 |
20150205381 | MOBILE GAMING CONTROLLER WITH INTEGRATED VIRTUAL MOUSE - A method is enacted in a computer system operatively coupled to a hand-actuated input device. The method includes the action of determining automatically which form of user input to offer a process running on the computer system, the user input including position data from the input device. The method also includes the action of offering the position data to the process in the form determined. | 07-23-2015 |
20150204945 | HYBRID ON-CHIP CLOCK CONTROLLER TECHNIQUES FOR FACILITATING AT-SPEED SCAN TESTING AND SCAN ARCHITECTURE SUPPORT - Various aspects described or referenced herein are directed to different methods, systems, and computer program products for implementing hybrid on-chip clock controller techniques for facilitating at-speed scan testing and scan architecture support. | 07-23-2015 |
20150202533 | MAPPING TOUCHSCREEN GESTURES TO ERGONOMIC CONTROLS ACROSS APPLICATION SCENES - A technique of implementing on-screen gestures associated with a software application comprises receiving a first control input that relates to a first scene associated with the software application, translating the first control input into a first set of instructions based on a first mapping, and providing the first set of instructions to an operating system that includes the first set of instructions in the software application, receiving a second control input that relates to a second scene associated with the software application, translating the second control input into a second set of instructions based on a second mapping, and providing the second set of instructions to the operating system, wherein the operating system is configured to include the second set of instructions in the software application. | 07-23-2015 |
20150201219 | SYSTEM AND METHOD FOR PIXEL DATA COMPRESSION - A system for, and method of, pixel data compression and a smartphone incorporating the system or the method. In one embodiment, the system includes: (1) a differential pulse code modulation encoder operable differentially to compress the two pixel values losslessly to yield two losslessly compressed pixel values and (2) an entropy encoder coupled to the differential pulse code modulation encoder and configured to receive and entropy-encode the losslessly compressed pixel values using a tiered technique to yield entropy-encoded, losslessly compressed pixel values. values using a tiered technique to yield Huffman-encoded, losslessly compressed pixel values. | 07-16-2015 |
20150200541 | INPUT RAIL DYNAMIC POWER BALANCING AND MERGING - A dynamic multiple input rail switching unit includes a plurality of DC input voltage rails and a rail switching section coupled to the plurality of DC input voltage rails that is configured to individually connect selected ones of the plurality of DC input voltage rails to a switched rail output. The dynamic multiple input rail switching unit also includes a rail selection section that is coupled to the rail switching section and configured to dynamically choose the selected ones by balancing rail supply currents from the plurality of DC input voltage rails based on rail supply current capacity margins and a switched rail output current. A dynamic multiple input rail switching unit operating method, and a dynamic multiple input rail power converter are also provided. | 07-16-2015 |
20150200020 | INTEGRATED CIRCUIT HAVING AN ENHANCED FUSELESS FUSE STRUCTURE, A METHOD OF MANUFACTURING THE SAME AND A DATA STRUCTURE FOR USE WITH THE FUSELESS FUSE STRUCTURE - An enhanced fuseless fuse structure is provided herein. Additionally, an IC with an enhanced fuseless fuse structure, a data structure that can be used with this structure and a method of manufacturing an IC are disclosed herein. In one embodiment, the IC includes: (1) a fuse wrapper configured to decode fuseless fuse data for controlling the fuses, (2) JTAG registers configured to store fuse register values in designated blocks, wherein the fuse register values and the designated blocks are determined from the fuseless fuse data and (3) options registers configurable by software to store fuse override data for modifying the fuse register values. | 07-16-2015 |
20150200006 | SRAM WRITE DRIVER WITH IMPROVED DRIVE STRENGTH - A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted. | 07-16-2015 |
20150199833 | HARDWARE SUPPORT FOR DISPLAY FEATURES - One embodiment of the present invention sets forth a system for displaying images including a hardware display controller engine that receives a rendered image. The system also includes an output compositor that composites a first image and the rendered image to create a second composited image. Finally, the system includes a display to display the second composited image. | 07-16-2015 |
20150199822 | PCIE CLOCK RATE STEPPING FOR GRAPHICS AND PLATFORM PROCESSORS - Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate. | 07-16-2015 |
20150199464 | FLOORPLAN ANNEAL USING PERTURBATION OF SELECTED AUTOMATED MACRO PLACEMENT RESULTS - A method of designing a floorplan for an integrated circuit comprises executing one or more automated placement processes on one or more seed floorplans to generate at least one output floorplan for each of the one or more seed floorplans, wherein the one or more automated placement processes are included in a plurality of pre-selected automated placement processes. The method further comprises computing a quality score for each output floorplan and, based on the quality scores, selecting at least one of the output floorplans for further execution via at least one automated placement process included in the plurality of pre-selected automated placement processes. | 07-16-2015 |
20150199280 | METHOD AND SYSTEM FOR IMPLEMENTING MULTI-STAGE TRANSLATION OF VIRTUAL ADDRESSES - A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory. | 07-16-2015 |
20150199223 | APPROACH TO PREDICTIVE VERIFICATION OF WRITE INTEGRITY IN A MEMORY DRIVER - A subsystem is configured to apply an offset voltage to a test, or canary, SRAM write driver circuit to create a condition that induces failure of the write operation. The offset voltage is incrementally increased until failure of the test write operation occurs in the canary SRAM circuit. The subsystem then calculates a probability of failure for the actual, non-test SRAM write operation, which is performed by an equivalent driver circuit with zero offset. The subsystem then compares the result to a benchmark acceptable probability figure. If the calculated probability of failure is greater than the benchmark acceptable probability figure, corrective action is initiated. In this manner, actual failures of SRAM write operations are anticipated, and corrective action reduces their occurrence and their impact on system performance. | 07-16-2015 |
20150199176 | POWER SUPPLY FOR RING-OSCILLATOR BASED TRUE RANDOM NUMBER GENERATOR AND METHOD OF GENERATING TRUE RANDOM NUMBERS - A true random number generator, a method of generating a true random number and a system incorporating the generator or the method. In one embodiment, the generator includes: (1) a ring oscillator including inverting gates having power inputs and (2) a time-varying power supply coupled to the power inputs to provide power thereto and including power perturbation circuitry operable to perturb the power provided to at least one of the power inputs. | 07-16-2015 |
20150199165 | AUTOMATIC PROXIMITY DISPLAY SWITCHING FOR A MIRACAST ENVIRONMENT - A proximity display system includes a mobile device that is enabled for Miracast sourcing and that provides a screen display. The proximity display system also includes a plurality of display units, which is enabled for Miracast sinking and is also coupled to the mobile device. Additionally, the proximity display system further includes a proximity sensing unit, which is coupled to the plurality of display units and enables a presentation of the screen display on a selected one of the plurality of display units based on a transmission signal strength received from the mobile device at the selected one. A method of operating a proximity display system is also included. | 07-16-2015 |
20150195521 | CANDIDATE MOTION VECTOR SELECTION SYSTEMS AND METHODS - The present invention facilitates efficient and effective encoding and motion detection. A system and method can include: receiving graphics frame information; performing a motion vector analysis including candidate selection utilizing motion vectors that processing has previously been initiated for; and performing an encoding utilizing results of the motion vector analysis. A candidate motion vector is selected based upon balancing of performance and accuracy. The candidate motion vector can be associated with a macro-block that is spatially and temporally close to the left in the same row as the current macro-block. In one exemplary implementation, the candidate motion vector can be within 1 to 8 macro-blocks to the left of the current macro-block. A motion vector candidate selection process for a current macro-block can be performed in which a motion vector associated with another macro-block that has completed motion vector analysis is included as a candidate for the current macro-block. | 07-09-2015 |
20150195482 | METHOD, SYSTEM AND SMARTPHONE THAT CHOOSES OPTIMAL IMAGE TO REDUCE SHUTTER SHAKE - An image capturer for reducing the effect of shutter shake of a digital camera in a smartphone, a method of capturing an image employing a digital camera, and a smartphone. In one embodiment, the image capturer includes: (1) a control interface configured to receive a command to photograph a scene and (2) a best shot determiner, coupled to the control interface and configured to select, after a focused image of the scene has been acquired and in response to receiving the command, a captured image of the scene based on sharpness metrics. | 07-09-2015 |
20150195342 | REMOTE CONFIGURATION OF DATA PROCESSING DEVICES IN A CLUSTER COMPUTING SYSTEM - A method includes implementing a cluster computing system including a number of data processing devices coupled to one another in a daisy-chain configuration and communicatively coupled to a server, executing a process on the server and executing an instance of the process on each data processing device. The method also includes remotely configuring, through the server, one or more specific parameter(s) of a display unit associated with a first data processing device, a screen of the display unit, a processor thereof, a memory communicatively coupled to the processor, an algorithm executing thereon and/or a power supply of the first data processing device based on the execution of the process. Further, the method includes remotely configuring, through the server, a same one or more specific parameter(s) associated with a sequentially next data processing device of the cluster computing system based on the remote configuration associated with the first data processing device. | 07-09-2015 |
20150194951 | TOGGLING A CLOCKED COMPONENT USING A SLOW CLOCK TO ADDRESS BIAS TEMPERATURE INSTABILITY AGING - While a clocked component is not idle, the component receives a clock signal that is at a first frequency. When the clocked component is idle, the clock signal is changed to a non-zero second frequency that is less than the first frequency. In effect, clock gating is replaced with clock slowdown. | 07-09-2015 |
20150194360 | INTEGRATED CIRCUIT PACKAGE HAVING IMPROVED COPLANARITY - One aspect of the present disclosure provides an IC substrate, comprising a first material layer located on a first side of the IC substrate, and a second material layer located on a second, opposing side of the IC substrate, wherein the second material layer has a higher coefficient of thermal expansion CTE value than the first material layer. | 07-09-2015 |
20150194157 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ARTIFACT REDUCTION IN HIGH-FREQUENCY REGENERATION AUDIO SIGNALS - A system, method, and computer program product are provided for artifact reduction in high-frequency regeneration audio signals. In operation, a high-frequency regeneration (HFR) audio signal is received. Additionally, one or more artifacts are detected in the received HFR audio signal, utilizing a spectral energy associated with the received HFR audio signal. Further, the received HFR audio signal is modified to at least partially correct the one or more artifacts in the received HFR audio signal. | 07-09-2015 |
20150194137 | METHOD AND APPARATUS FOR OPTIMIZING DISPLAY UPDATES ON AN INTERACTIVE DISPLAY DEVICE - A solution is proposed to perform display updates in a lower power user interface. According to one embodiment, the display panel is placed in the lower possible refresh rate that can be supported. Rendered updates are presented to the displays at the fasted possible pixel rates the communication interface between the rendering component to the display panel can support, and a buffer on the receiving end of the display receives and stores updated frames as they are rendered and transmitted. Subsequent display updates (generated in response to subsequent sensor input, for example) may be created and transmitted as soon as the preceding display frames are buffered. In the meantime, as soon as the update frame is transmitted, the timing controller of the display panel is instructed to interrupt the current refresh period and to immediately rescan the frame. | 07-09-2015 |
20150194136 | METHOD AND SYSTEM FOR KEYFRAME DETECTION WHEN EXECUTING AN APPLICATION IN A CLOUD BASED SYSTEM PROVIDING VIRTUALIZED GRAPHICS PROCESSING TO REMOTE SERVERS - A method for switching, including initializing an instantiation of an application and performing graphics rendering to generate a plurality of rendered frames through execution of the application in order to generate a first video stream comprising the plurality of rendered frames. The method includes sequentially loading the plurality of rendered frames into one or more frame buffers, and determining when a first bitmap of a frame that is loaded into a corresponding frame buffer matches an application signature comprising a derivative of a master bitmap associated with a keyframe of the first video stream. | 07-09-2015 |
20150194128 | GENERATING A LOW-LATENCY TRANSPARENCY EFFECT - One embodiment of the present invention sets forth a technique for generating a transparency effect for a computing device. The technique includes transmitting, to a camera, a synchronization signal associated with a refresh rate of a display. The technique further includes determining a line of sight of a user relative to the display, acquiring a first image based on the synchronization signal, and processing the first image based on the line of sight of the user to generate a first processed image. Finally, the technique includes compositing first visual information and the first processed image to generate a first composited image, and displaying the first composited image on the display. | 07-09-2015 |
20150194111 | DC BALANCING TECHNIQUES FOR A VARIABLE REFRESH RATE DISPLAY - A method for driving a display panel having a variable refresh rate is disclosed. The method comprises detecting a condition that results in a charge accumulation in the display panel using an accumulated difference in time duration between frames of positive polarity and frames of negative polarity received from an image source. The DC imbalance is a result of a frame pattern comprising alternating frames of differing polarities, wherein frames of positive polarity within the frame pattern are of a different time duration than frames of negative polarity, and wherein the frame pattern results in an accumulation of charge in pixels of the display panel. The method also comprises correcting for the charge accumulation by disrupting the frame pattern. | 07-09-2015 |
20150193915 | TECHNIQUE FOR PROJECTING AN IMAGE ONTO A SURFACE WITH A MOBILE DEVICE - A mobile device includes a projector configured to project images onto a target surface that resides within a projectable area. The mobile device identifies the target surface within the projectable area and then tracks that target surface as the mobile device is subject to different types of motion, including translation and rotation, among others. The mobile device then compensates for that motion when projecting the images, potentially eliminating distortion in the projected images. Additionally, the mobile device may compensate for geometric differences between the projected image and the target surface by cropping the images to fit within the target surface. One advantage of the disclosed technique is that the mobile device is capable of projecting images with reduced distortion despite movement associated with the mobile device. | 07-09-2015 |
20150193907 | EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE - A surface cache stores pixel data on behalf of a pixel processing pipeline that is configured to generate screen tiles. The surface cache assigns hint levels to cache lines storing pixel data according to whether that pixel data is likely to be needed again. When the pixel data is needed to process a subsequent tile, the corresponding cache line is assigned a higher hint value. When the pixel data is not needed again, the corresponding cache line is assigned a lower hint value. The surface cache is configured to preferentially evict cache lines having a lower hint value, thereby preserving cache lines that store pixel data needed for future processing. In addition, a fetch controller is configured to throttle the rate at which fetch requests are issued to the surface cache to prevent situations where pixel data needed for future operations becomes prematurely evicted. | 07-09-2015 |
20150193903 | EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE - A surface cache stores pixel data on behalf of a pixel processing pipeline that is configured to generate screen tiles. The surface cache assigns hint levels to cache lines storing pixel data according to whether that pixel data is likely to be needed again. When the pixel data is needed to process a subsequent tile, the corresponding cache line is assigned a higher hint value. When the pixel data is not needed again, the corresponding cache line is assigned a lower hint value. The surface cache is configured to preferentially evict cache lines having a lower hint value, thereby preserving cache lines that store pixel data needed for future processing. In addition, a fetch controller is configured to throttle the rate at which fetch requests are issued to the surface cache to prevent situations where pixel data needed for future operations becomes prematurely evicted. | 07-09-2015 |
20150193358 | Prioritized Memory Reads - A system includes a processing unit and a memory system coupled to the processing unit. The processing unit is configured to mark a memory access in the series of instructions as a priority memory access as a consequence of the memory access having a dependent instruction following less than a threshold distance after the memory access in the series of instructions. The processing unit is configured to send the marked memory access to the memory system. | 07-09-2015 |
20150193272 | SYSTEM AND PROCESSOR THAT INCLUDE AN IMPLEMENTATION OF DECOUPLED PIPELINES - A system and apparatus are provided that include an implementation for decoupled pipelines. The apparatus includes a scheduler configured to issue instructions to one or more functional units and a functional unit coupled to a queue having a number of slots for storing instructions. The instructions issued to the functional unit are stored in the queue until the functional unit is available to process the instructions. | 07-09-2015 |
20150193203 | EFFICIENCY IN A FUSED FLOATING-POINT MULTIPLY-ADD UNIT - A four cycle fused floating point multiply-add unit includes a radix 8 Booth encoder multiplier that is partitioned over two stages with the compression element allocated to the second stage. The unit further includes an improved shifter design. Processing logic analyzes the input operands, detects values of zero and one, and inhibits portions of the processing logic accordingly. When one of the multiplicand inputs has a value of zero or one, the required multiplication becomes trivial, and the unit inhibits the associated coding logic and data transfer to reduce power consumption. The unit then performs an add-only operation. When the addend input has a value of zero, the addition becomes trivial, and the unit inhibits the improved shifter and data transfer to further reduce power consumption. The unit then performs a multiply-only operation. | 07-09-2015 |
20150193062 | METHOD AND APPARATUS FOR BUFFERING SENSOR INPUT IN A LOW POWER SYSTEM STATE - A solution is proposed for processing input in a lower power user interface of touch-sensitive display panels. According to an embodiment, a mobile computing device is placed in the low power mode. During this mode, the sensor controller produces a raw event/interrupts on a detected touch. Upon detecting a touch, the sensor controller also automatically increases the scan rate of the touch sensor, while the triggered event or interrupt proceeds to wake the system into a higher power state. Subsequent touch data received while the system is booting into the higher power state is buffered by the timing controller, or by a bridge chipset, while the processor(s) in the power up. When awake, the processor(s) collect the touch samples from the buffer, and processes the touch samples, generating updated displays where necessary. | 07-09-2015 |
20150192942 | VOLTAGE OPTIMIZATION CIRCUIT AND MANAGING VOLTAGE MARGINS OF AN INTEGRATED CIRCUIT - A voltage margin controller, an IC included the same and a method of controlling voltage margin for a voltage domain of an IC are disclosed herein. In one embodiment, the voltage margin controller includes: (1) monitoring branches including circuit function indicators configured to indicate whether circuitry in the voltage domain could operate at corresponding candidate reduced voltage levels and (2) a voltage margin adjuster coupled to the monitoring branches and configured to develop a voltage margin adjustment for a voltage regulator of the voltage domain based upon an operating number of the circuit function indicators. | 07-09-2015 |
20150189126 | CONTROLLING CONTENT FRAME RATE BASED ON REFRESH RATE OF A DISPLAY - A video frame producer, a method of generating content frames and a video viewing device are disclosed herein. In one embodiment, the video frame producer includes: (1) a content provider configured to generate content frames for a display and (2) a viewing smoother configured to direct the content provider to generate the content frames at a frame rate based on a display refresh rate of the display. | 07-02-2015 |
20150189012 | WIRELESS DISPLAY SYNCHRONIZATION FOR MOBILE DEVICES USING BUFFER LOCKING - One embodiment of the present invention includes techniques for synchronizing displays of a plurality of mobile devices over a wireless network. A processing unit renders an image frame related to a software application into an application image buffer associated with a first mobile device and causes a second mobile device to render a second image frame into a second application image buffer of the second mobile device. The processing unit receives an acknowledgement over a wireless network indicating that the second mobile device has completed rendering the second image frame. The processing unit displays contents of the application image buffer on a first display device associated with the first mobile device and transmits a signal to the second mobile device over a wireless network that causes the second mobile device to display contents of the second application image buffer on a second display device associated with the second mobile device. | 07-02-2015 |
20150187256 | PREVENTING FETCH OF OCCLUDED PIXELS FOR DISPLAY PROCESSING AND SCAN-OUT - One embodiment of the present invention includes techniques for compositing image surfaces to generate a display image for display. A display engine receives a first set of parameters associated with a first image surface stored in a memory. The display engine receives a second set of parameters associated with a second image surface stored in the memory, wherein the second image surface overlaps at least a portion of the first image surface. The display engine selects a first pixel group that is associated with the first image surface and does not contribute visually to the display image. The display engine prevents the first pixel group from being retrieved from the first image surface. One advantage of the disclosed embodiments is that power consumption is reduced and memory performance is improved by preventing retrieval of pixel information that does not contribute to the final visual display transmitted to the display device. | 07-02-2015 |
20150187135 | GENERATING INDIRECTION MAPS FOR TEXTURE SPACE EFFECTS - Embodiments of the present invention are directed to a novel approach for realistically modeling sub-surface scattering effects in three-dimensional objects of graphically rendered images. In an embodiment, an indirection map is generated for an image by analyzing the triangle mesh of one or more three-dimensional objects in the image and identifying pairs of edges between adjacent triangles in the mesh that have the same spatial locations in the three-dimensional representations, but which have different locations in the texture map. For each of these edges, the opposite triangle in each pair is projected into their corresponding edge's two-dimensional space. This allows samples which cross a seam in the two dimensional representation that would otherwise sample out into invalid data to be redirected to the spatially correct region of the texture and generate consistent results with non-seam areas. | 07-02-2015 |
20150187129 | TECHNIQUE FOR PRE-COMPUTING AMBIENT OBSCURANCE - One embodiment of the present invention includes techniques for pre-computing ambient shadowing parameters for a computer-generated scene. A processing unit retrieves a reference object associated with the computer-generated scene and comprising a plurality of vertices. For each vertex in the plurality of vertices, the processing unit computes a local ambient shadowing parameter, and stores the local ambient shadowing parameter in a memory. For each instance of the reference object included in the computer-generated scene, the processing unit computes a first global ambient shadowing parameter based on the position of the instance within the computer-generated scene, and stores the first global ambient shadowing parameter in the memory. One advantage of the disclosed embodiments is that ambient obscurance is applied to instance objects in a scene in real time while reducing memory space dedicated to storing the AO parameters. | 07-02-2015 |
20150187126 | USING INDIRECTION MAPS FOR RENDERING TEXTURE SPACE EFFECTS - Embodiments of the present invention are directed to a novel approach for realistically modeling sub-surface scattering effects in three-dimensional objects of graphically rendered images. In an embodiment, an indirection map is generated for an image by analyzing the triangle mesh of one or more three-dimensional objects in the image and identifying pairs of edges between adjacent triangles in the mesh that have the same spatial locations in the three-dimensional representations, but which have different locations in the texture map. For each of these edges, the opposite triangle in each pair is projected into their corresponding edge's two-dimensional space. This allows samples which cross a seam in the two dimensional representation that would otherwise sample out into invalid data to be redirected to the spatially correct region of the texture and generate consistent results with non-seam areas. | 07-02-2015 |
20150187041 | GPU AND GPU COMPUTING SYSTEM FOR PROVIDING A VIRTUAL MACHINE AND A METHOD OF MANUFACTURING THE SAME - Disclosed herein is a GPU for improved multitasking by a user, a GPU computing system including the GPU and a method of manufacturing a GPU system. In one embodiment, the GPU includes: (1) a video overlayer configured to create an operating area over a portion of a video image generated by the graphical processing unit and (2) an overlay interface configured to provide a virtual space input to the video overlayer to operate a virtual machine within the operating area. | 07-02-2015 |
20150180694 | RADIO FREQUENCY CIRCUIT FOR INTRA-BAND AND INTER-BAND CARRIER AGGREGATION - A radio frequency (RF) circuit for intra-band and inter-band carrier aggregation includes a receive path configured to receive an input signal. The RF circuit includes a low noise amplifier which has multiple separate input stages and multiple separate output stages. Each input stage has multiple separate input paths, wherein each separate input path is configured to be separately activated and connected to one of the output stages. Each separate output stage is configured to be separately activated and connected to a signal mixer that provides signal demodulation of the input signal employing aggregation of carriers corresponding to intra-band or inter-band signals. Methods of operating the RF circuit for intra-band and inter-band carrier aggregation are also provided. | 06-25-2015 |
20150179232 | SYSTEM AND METHOD FOR PERFORMING SRAM ACCESS ASSISTS USING VSS BOOST - A method and a system are provided for performing memory access assist using voltage boost. A memory access request is received at a storage cell array that comprises two or more subarrays, each subarray including at least one row of storage cells. The voltage boost is applied, during the memory access, to a first negative supply voltage of a first storage cell subarray of the two or more storage cell subarrays. The first negative supply voltage of the first storage cell subarray is lower than a second negative supply voltage of a second storage cell subarray of the two or more storage cell subarrays. | 06-25-2015 |
20150179142 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR REDUCED-RATE CALCULATION OF LOW-FREQUENCY PIXEL SHADER INTERMEDIATE VALUES - A system, method, and computer program product are provided for calculating shader program intermediate values. The method includes the steps of receiving a graphics primitive for processing according to a shader program including a first set of instructions and a second set of instructions, executing the first set of instructions by a processing pipeline to calculate multi-pixel intermediate values, executing the second set of instructions by the processing pipeline to calculate per-pixel values based on at least the multi-pixel intermediate values, and repeating the receiving and executing of the first and second sets of instructions for one or more additional graphics primitives. | 06-25-2015 |
20150178961 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ANGULAR SUBDIVISION OF QUADRATIC BEZIER CURVES - A system, method, and computer program product are provided for subdividing a quadratic Bezier curve. The method includes the steps of receiving a quadratic Bezier curve defined by a plurality of control points including at least a first endpoint and a second endpoint. The quadratic Bezier curve is uniformly subdivided based on an angle between a first tangent at the first endpoint and a second tangent at the second endpoint to produce a piecewise representation of the quadratic Bezier curve including two or more Bezier curve segments. | 06-25-2015 |
20150178932 | IMAGE ANALYSIS OF DISPLAY CONTENT FOR DYNAMIC ADJUSTMENT OF A CONTINUOUS SCAN DISPLAY - Various embodiments relating to reducing memory bandwidth consumed by a continuous scan display screen are provided. In one embodiment, scoring criteria are applied to a reference image of a first image format having a first bit depth to generate an image conversion score. The scoring criteria are based on a histogram of one or more characteristics of the reference image. If the image conversion score is greater than a threshold value, then the reference image is converted to a modified image of a second image format having a second bit depth less than the first bit depth, and the modified image is scanned onto the continuous scan display screen. If the image conversion score is less than the threshold value, then the reference image is scanned onto the continuous scan display screen. | 06-25-2015 |
20150178879 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SIMULTANEOUS EXECUTION OF COMPUTE AND GRAPHICS WORKLOADS - A system, method, and computer program product are provided for allocating processor resources to process compute workloads and graphics workloads substantially simultaneously. The method includes the steps of allocating a plurality of processing units to process tasks associated with a graphics pipeline, receiving a request to allocate at least one processing unit in the plurality of processing units to process tasks associated with a compute pipeline, and reallocating the at least one processing unit to process tasks associated with the compute pipeline. | 06-25-2015 |
20150178085 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR REMAPPING REGISTERS BASED ON A CHANGE IN EXECUTION MODE - A system, method, and computer program product are provided for remapping registers based on a change in execution mode. A sequence of instructions is received for execution by a processor and a change in an execution mode from a first execution mode to a second execution mode within the sequence of instructions is identified, where a first register mapping is associated with the first execution mode and a second register mapping is associated with the second execution mode. Data stored in a set of registers within a processor is reorganized based on the first register mapping and the second register mapping in response to the change in the execution mode. | 06-25-2015 |
20150177514 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR A PINLIGHT SEE-THROUGH NEAR-EYE DISPLAY - A system, method, and computer program product are provided for implementing a pinlight see-through near-eye display. Light cones configured to substantially fill a field-of-view corresponding to a pupil are generated by an array of pinlights positioned between a near focus plane and the pupil. Overlap regions where two of more light cones intersect at a display layer positioned between the array of pinlights and the pupil are determined. The two or more light cones are modulated based on the overlap regions to produce a target image at or beyond the near focus plane. | 06-25-2015 |
20150163324 | APPROACH TO ADAPTIVE ALLOCATION OF SHARED RESOURCES IN COMPUTER SYSTEMS - A request management subsystem is configured to establish service classes for clients that issue requests for a shared resource on a computer system. The subsystem also is configured to determine the state of the system with respect to bandwidth, current latency, frequency and voltage levels, among other characteristics. Further, the subsystem is configured to evaluate the requirements of each client with respect to latency sensitivity and required bandwidth, among other characteristics. Finally, the subsystem is configured to schedule access to shared resources, based on the priority class of each client, the demands of the application, and the state of the system. With this approach, the subsystem may enable all clients to perform optimally or, alternatively, may cause all clients to experience an equal reduction in performance. | 06-11-2015 |
20150161810 | POSITION BASED FLUID DYNAMICS SIMULATION - Systems and methods for providing a mechanism of simulating fluid dynamics while maintaining the incompressibility of a fluid based on a position based dynamics (PBD) framework. A set of constraint equations that enforce constant density of the particles in a fluid object are formulated in terms of neighbor particle positions. The formulated constraint equations can be solved iteratively in a Jacobi method to obtain a new position and new velocity of each particle in large time steps. Voracity confinement may be introduced to simulate turbulent motions of the fluid object based on an unnormalized curl of the particle velocities. A positive artificial pressure term can be incorporated in particle position updates to reduce particle clustering or clumping effect caused by negative pressures related to neighbor deficiencies. | 06-11-2015 |
20150160911 | ENABLING HARDWARE ACCELERATION IN A COMPUTING DEVICE DURING A MOSAIC DISPLAY MODE OF OPERATION THEREOF - A method includes providing a memory unit in a computing device already including a number of processors communicatively coupled to a memory through a system bus, and providing a non-system bus based dedicated channel between the number of processors and the memory unit. The method also includes rendering a different video frame and/or a surface on each processor of the number of processors, and leveraging the memory unit to store a video frame and/or a surface rendered on a processor therein through the non-system bus based dedicated channel. Further, the method includes copying, to other processors, the stored video frame and/or the surface rendered on the processor from the memory unit through the non-system bus based dedicated channel, and scanning out, through the number of processors, the video frame and/or the surface rendered on the processor following the copying to enable display thereof on a corresponding number of displays. | 06-11-2015 |
20150156483 | PROVIDING A CAPABILITY TO SIMULTANEOUSLY VIEW AND/OR LISTEN TO MULTIPLE SETS OF DATA ON ONE OR MORE ENDPOINT DEVICE(S) ASSOCIATED WITH A DATA PROCESSING DEVICE - A method includes interleaving, through a processor of a data processing device communicatively coupled to a memory and/or a processor of a data source communicatively coupled to the data processing device, each of a data and another data within a data frame. The each of the data and the another data corresponds to a distinct set of video data, image data and/or audio data. The method also includes rendering, through the processor of the data processing device, the data frame on a display unit and/or one or more audio endpoint device(s) associated with the data processing device following the interleaving therewithin, and providing a capability to view and/or listen to solely the data or the another data from the rendered data frame on the display unit and/or the one or more audio endpoint device(s). | 06-04-2015 |
20150156143 | SYSTEM AND METHOD FOR SIDE DISPLAY ON A MULTI-DISPLAY MOBILE DEVICE - Embodiments of the present invention are operable to display content related to an application using side display screens installed on a multi-display mobile device. As such, embodiments of the present invention can make use of the display surface areas associated with side display screens to render content (e.g., notifications associated with an application) in a power efficient manner. Also, by using separate display buffers for side display screens, embodiments of the present invention can independently render content while other components of the mobile device (e.g., the main display screen) operate within low power mode or “sleep state.” As such, by using side display screen in this fashion, embodiments of the present invention can efficiently utilize the power and computational resources of the mobile device. | 06-04-2015 |
20150154934 | METHOD AND SYSTEM FOR CUSTOMIZING OPTIMAL SETTINGS USING END-USER PREFERENCES - Embodiments of the present invention provide a novel solution that uses subjective end-user input to generate optimal image quality settings for an application. Embodiments of the present invention enable end-users to rank and/or select various adjustable application parameter settings in a manner that allows them to specify which application parameters and/or settings are most desirable to them for a given application. Based on the feedback received from end-users, embodiments of the present invention may generate optimal settings for whatever performance level the end-user desires. Furthermore, embodiments of the present invention may generate optimal settings that may be benchmarked either on a server farm or on an end-user's client device. | 06-04-2015 |
20150154733 | STENCIL BUFFER DATA COMPRESSION - A raster operations (ROP) unit is configured to compress stencil values included in a stencil buffer. The ROP unit divides the stencil values into groups, subdivides each group into two halves, and selects an anchor value for each half. If the difference between each of the stencil values and the corresponding anchor lies within an offset range, and the difference between the two anchors lies within a delta range, then the group is compressible. For a compressible group, the ROP unit encodes the anchor value, offsets from anchors, and an anchor delta. This encoding enables the ROP unit to operate on the compressed group instead of the uncompressed stencil values, reducing the number of memory and computational operations associated with the stencil values. Consequently, the ROP unit reduces memory bandwidth use, reduces power consumption, and increases rendering rate compared to conventional ROP units that implement less flexible compression techniques. | 06-04-2015 |
20150154732 | COMPOSITING OF SURFACE BUFFERS USING PAGE TABLE MANIPULATION - One embodiment of the present invention sets forth a method for compositing surface buffered data for display. The method includes identifying a first set of memory mappings that associates a first set of contiguous virtual addresses with a first set of image data. The method also includes identifying a second set of memory mappings that associates a second set of contiguous virtual addresses with a second set of image data. The method further includes generating a third set of memory mappings based on the first set of memory mappings and the second set of memory mappings that associates a third set of contiguous virtual addresses with both the first set of image data and the second set of image data. Further embodiments provide, among other things, a computing device, a display subsystem, and a non-transitory computer-readable medium configured to carry out method steps set forth above. | 06-04-2015 |
20150153805 | DYNAMIC VOLTAGE-FREQUENCY SCALING TO LIMIT POWER TRANSIENTS - A clocked electronic device includes first and second control systems. The first control system is configured to decrease clock frequency in the device in response to decreasing supply voltage. The second control system is responsive to clock lag in the device and to an amount of current drawn through the device. It is configured to increase the supply voltage in response to increasing clock lag, but to decrease the supply voltage when the current drawn through the device exceeds an operational threshold. | 06-04-2015 |
20150153777 | ELECTRONIC DEVICE WITH BOTH INFLEXIBLE DISPLAY SCREEN AND FLEXIBLE DISPLAY SCREEN - Systems and methods for providing a user interface by using a flexible display screen as well as an inflexible display screen. The dual display screens are installed on the same electronic device and may be used to display information simultaneously or alternatively. The flexible display screen can display information in an expanded position and is substantially compacted in size in a retracted position. In response to a user request, the flexible display screen can automatically wind around a rotatable axial connector. The inflexible touchscreen may serve to receive user input with respect to the content displayed on the flexible display screen. An instant size of the flexible display screen can be detected by a sensor and used to adapt a format of the content displayed on the flexible display screen. | 06-04-2015 |
20150153544 | METHOD AND APPARATUS FOR AUGMENTING AND CORRECTING MOBILE CAMERA OPTICS ON A MOBILE DEVICE - Embodiments of the present invention utilize an attachable lens board that can be secured to the back of a mobile device and placed in a position that is proximate to the built-in camera lens associated with the camera system of the mobile device. As such, the lens board can be positioned to accurately align several different auxiliary camera lenses, each installed within various camera lens receivers formed within the lens board, with the built-in camera lens for focusing and/or image capture. Additionally, embodiments of present invention can include circuitry within the lens board that can be used to identify the types of lenses currently installed within each camera lens receiver. In this manner, embodiments of the present invention can correct possible optical imperfections of resultant images produced by the combination of the built-in camera lens and auxiliary lens selected for focusing and/or image capture by the user. | 06-04-2015 |
20150149788 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR OPTIMIZING DATA ENCRYPTION AND DECRYPTION BY IMPLEMENTING ASYMMETRIC AES-CBC CHANNELS - A system, method, and computer program product are provided for implementing asymmetric AES-CBC (Advanced Encryption Standard-Cipher Block Chaining) channels usage between encryption and decryption of data. In operation, data to be written to memory is identified. In addition, the data is encrypted utilizing a first AES-CBC channel. Additionally, at least one of a plurality of AES-CBC channels is utilized to decrypt the data to achieve a determined performance target. | 05-28-2015 |
20150149713 | MEMORY INTERFACE DESIGN - An improved memory interface design is provided. In some implementations, an integrated circuit includes a first cache memory unit, a second cache memory unit located in parallel with the first cache memory unit, and a floorsweeping module configured to be able to select between the first cache memory unit and the second cache memory unit for cache requests, wherein the selection is based at least partially on the presence or absence of one or more manufacturing defects in the first cache memory unit or the second cache memory unit. | 05-28-2015 |
20150146993 | GENERALIZATION OF METHODS AND SYSTEMS FOR IMAGE COMPRESSION WHILE ENCODING AT LEAST ONE EXTRA BIT - A method for encoding at least one extra bit in an image compression and decompression system. The method includes accessing an input image, and compressing the input image into a compressed image using an encoder system, wherein said encoding system implements an algorithm for encoding at least one extra bit. The method further includes communicatively transferring the compressed image to a decoding system, and decompressing the compressed image into a resulting uncompressed image that is unaltered from said input image, wherein the algorithm for encoding enables the recovery of the at least one extra bit. | 05-28-2015 |
20150145871 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT TO ENABLE THE YIELDING OF THREADS IN A GRAPHICS PROCESSING UNIT TO TRANSFER CONTROL TO A HOST PROCESSOR - A method, system, and computer-program product are provided to enable the yielding by threads executing in a processing unit to transfer control to a host processor. The method includes the steps of receiving an intermediate representation of a program, replacing a yield instruction in the intermediate representation with a yield operation that includes one or more instructions, and compiling at least a portion of the modified intermediate representation into a machine code for execution on a parallel processing unit. | 05-28-2015 |
20150143347 | SOFTWARE DEVELOPMENT ENVIRONMENT AND METHOD OF COMPILING INTEGRATED SOURCE CODE - A software development environment (SDE) and a method of compiling integrated source code. One embodiment of the SDE includes: (1) a parser configured to partition an integrated source code into a host code partition and a device code partition, the host code partition including a reference to a device variable, (2) a translator configured to: (2a) embed device machine code, compiled based on the device code partition, into a modified host code, (2b) define a pointer in the modified host code configured to be initialized, upon execution of the integrated source code, to a memory address allocated to the device variable, and (2c) replace the reference with a dereference to the pointer, and (3) a host compiler configured to employ a host library to compile the modified host code. | 05-21-2015 |
20150143061 | PARTITIONED REGISTER FILE - A system includes a processing unit and a register file. The register file includes at least a first memory structure and a second memory structure. The first memory structure has a lower access energy than the second memory structure. The processing unit is configured to address the register file using a single logical namespace for both the first memory structure and the second memory structure. | 05-21-2015 |
20150143058 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR UTILIZING A DATA POINTER TABLE PRE-FETCHER - A system, method, and computer program product are provided for utilizing a data pointer table pre-fetcher. In use, an assembly of a data pointer table within a main memory is identified. Additionally, the data pointer table is pre-fetched from the main memory. Further, data is sampled from the pre-fetched data pointer table. Further still, the sampled data is stored within a data pointer table cache. | 05-21-2015 |
20150141092 | Electronic Device and Associated Protective Cover - Provided for herein is an electronic device. The electronic device, in one example, includes a housing having a housing width, housing height, housing thickness, and a front and a back, and a display positioned proximate the front of the housing. The electronic device, in this aspect, further includes a magnetic or ferromagnetic rail positioned proximate the back of the housing, the magnetic or ferromagnetic rail configured to assist in providing multiple viewing angles for the electronic device. | 05-21-2015 |
20150139543 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ENHANCING AN IMAGE UTILIZING A HYPER-CLARITY TRANSFORM - A system, method, and computer program product are provided for enhancing an image utilizing a hyper-clarity transform. In use, an image is identified. Additionally, the identified image is enhanced, utilizing a hyper-clarity transform. Further, the enhanced image is returned. | 05-21-2015 |
20150138697 | Protective Cover for an Electronic Device and Method of Manufacturing the Same - Provided for herein is a protection device for an electronic device, comprising (1) a cover having a cover width, cover height and cover thickness; and (2) a spindle attached to an edge of the cover, the spindle configured to cooperatively engage a groove formed in a housing of the electronic device and couple the cover to the electronic device. | 05-21-2015 |
20150138228 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING ANTI-ALIASING OPERATIONS USING A PROGRAMMABLE SAMPLE PATTERN TABLE - A system, method, and computer program product are provided for implementing anti-aliasing operations using a programmable sample pattern table. The method includes the steps of receiving an instruction that causes one or more values to be stored in one or more corresponding entries of the programmable sample pattern table and performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table. At least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels. | 05-21-2015 |
20150138065 | HEAD-MOUNTED INTEGRATED INTERFACE - A head mounted integrated interface (HMII) is presented that may include a wearable head-mounted display unit supporting two compact high resolution screens for outputting a right eye and left eye image in support of the stereoscopic viewing, wireless communication circuits, three-dimensional positioning and motion sensors, and a processing system which is capable of independent software processing and/or processing streamed output from a remote server. The HMII may also include a graphics processing unit capable of also functioning as a general parallel processing system and cameras positioned to track hand gestures. The HMII may function as an independent computing system or as an interface to remote computer systems, external GPU clusters, or subscription computational services, The HMII is also capable linking and streaming to a remote display such as a large screen monitor. | 05-21-2015 |
20150134916 | CACHE FILTER - A cache filter is described. More specifically, some implementations include techniques for classification of memory requests including calculating a probability that one or more memory regions are associated with a particular memory request, selecting one or more regions of the memory to receive memory requests based on the probability associated with the one or more regions, receiving one or more memory requests, determining that at least one of the memory requests is associated with one of the one or more selected regions of the memory, and providing the at least one memory request to the memory. | 05-14-2015 |
20150130967 | ADAPTIVE DYNAMIC RANGE IMAGING - In an apparatus according to one embodiment of the present invention, a video system is disclosed. The video system comprises a pre-processing module, an auto-exposure module, and an image sensor. The image sensor is operable to simultaneously capture a first image at a long exposure and a second image at a short exposure capture. The auto-exposure module is operable to determine an average brightness of a scene for video/image capturing, wherein the determined brightness achieves a desired image quality. The auto-exposure module is further operable to select a dynamic range necessary to preserve desired details in a captured scene. The auto-exposure module is further operable to instruct the image sensor to capture the first image and the second image with a selected exposure ratio to achieve the desired dynamic range. The pre-processing module is operable to combine the first image and the second image into a final image with the desired dynamic range. | 05-14-2015 |
20150130915 | APPARATUS AND SYSTEM FOR DYNAMIC ADJUSTMENT OF DEPTH FOR STEREOSCOPIC VIDEO CONTENT - An apparatus and system are provided for adjusting the depth of stereoscopic video content. The apparatus comprises a frame that supports a first lens and a second lens. The first lens is associated with a first image in a stereoscopic image pair and the second lens is associated with a second image in the stereoscopic image pair. An interface for controlling a parameter associated with the stereoscopic image pair is integrated into the frame of the apparatus. The system includes a display device configured to display stereoscopic video content and coupled to the apparatus for controlling the stereoscopic video content. | 05-14-2015 |
20150130850 | METHOD AND APPARATUS TO PROVIDE A LOWER POWER USER INTERFACE ON AN LCD PANEL THROUGH LOCALIZED BACKLIGHT CONTROL - A system and method are provided for displaying a lower power user interface on an liquid crystal display (LCD) panel using localized backlight control. The method includes the step of identifying a subset of light emitting elements included in a backlight for the LCD panel, where the backlight includes a plurality of light emitting elements. The subset of light emitting elements consumes less power when operated individually or in combination with other subsets of light emitting elements than the total backlight with all light emitting elements simultaneously active. The method also includes the steps of activating the subset of light emitting elements to at least partially illuminate the LCD panel while at least one light emitting element is not activated, adjusting an image for a user interface based on a compensation map corresponding to the subset of light emitting elements, and displaying the adjusted image on the LCD panel. | 05-14-2015 |
20150127860 | SETTING A PCIE DEVICE ID - One embodiment of the present invention includes a hard-coded first device ID. The embodiment also includes a set of fuses that represents a second device ID. The hard-coded device ID and the set of fuses each designate a separate device ID for the device, and each device ID corresponds to a specific operating configuration of the device. The embodiment also includes selection logic to select between the hardcoded device ID and the set of fuses to set the device ID for the device. One advantage of the disclosed embodiments is providing flexibility for engineers who develop the devices while also reducing the likelihood that a third party can counterfeit the device. | 05-07-2015 |
20150127335 | VOICE TRIGGER - Voice trigger. In accordance with a first method embodiment, a long term average audio energy is determined based on a one-bit pulse-density modulation bit stream. A short term average audio energy is determined based on the one-bit pulse-density modulation bit stream. The long term average audio energy is compared to the short term average audio energy. Responsive to the comparing, a voice trigger signal is generated if the short term average audio energy is greater than the long term average audio energy. Determining the long term average audio energy may be performed independent of any decimation of the bit stream. | 05-07-2015 |
20150127333 | EFFICIENT DIGITAL MICROPHONE RECEIVER PROCESS AND SYSTEM - A method for processing a bitstream starts by shifting a bitstream of a first sample of a signal into a buffer. The buffer also holds bits of one or more additional bitstreams for one or more additional samples of the signal. Bits of a first half of the buffer are incrementally compared to corresponding bits of a second half of the buffer. Each bit of the first half of the buffer is compared to a corresponding bit of the second half of the buffer. A computation is performed on each bit of the first half of the buffer that is equal to a corresponding bit of the second half of the buffer. The results of the computations are summed to determine an output value for the first sample of the signal. | 05-07-2015 |
20150125091 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING FAST, NON-RIGID REGISTRATION FOR HIGH DYNAMIC RANGE IMAGE STACKS - A system, method, and computer program product are provided for performing fast, non-rigid registration for at least two images of a high-dynamic range image stack. The method includes the steps of generating a warped image based on a set of corresponding pixels, analyzing the warped image to detect unreliable pixels in the warped image, and generating a corrected pixel value for each unreliable pixel in the warped image. The set of corresponding pixels includes a plurality of pixels in a source image, each pixel in the plurality of pixels associated with a potential feature in the source image and paired with a corresponding pixel in a reference image that substantially matches the pixel in the source image. | 05-07-2015 |
20150123977 | LOW LATENCY AND HIGH PERFORMANCE SYNCHRONIZATION MECHANISM AMONGST PIXEL PIPE UNITS - A method for synchronizing a plurality of pixel processing units is disclosed. The method includes sending a first trigger to a first pixel processing unit to execute a first operation on a portion of a frame of data. The method also includes sending a second trigger to a second pixel processing unit to execute a second operation on the portion of the frame of data when the first operation has completed. The first operation has completed when the first operation reaches a sub-frame boundary. | 05-07-2015 |
20150120674 | VIRTUAL PROGRAM INSTALLATION AND STATE RESTORATION - The description is directed to systems and methods for restoring a program state retained from a prior execution session on a virtual machine. On receiving a request to execute a program an image of user-independent files are mounted to a virtual machine. Specified user-modifiable files are copied from a particular user storage location to put the program in a condition to execute the program so that it begins from the previously-existing program state. During the session at least some of the files are modified and on a session end the user-modifiable files are saved to the particular user storage location to retain the updated program state. | 04-30-2015 |
20150119149 | METHOD AND SYSTEM FOR GATHERING TIME-VARYING METRICS - Embodiments of the present invention provide a novel solution which can be used to detect and analyze instances of micro stutter within a given game, GPU and/or driver version. Embodiments of the present invention may be operable to divide an application session into a set of sub-sessions and perform multiple derivative calculations on time-varying application parameters (e.g., frame rates) measured during each sub-session. Embodiments of the present invention may also be operable to generate separate histograms for each derivative calculation performed. As such, based on calculations performed, embodiments of the present invention may synchronously increment histogram bins representing a corresponding range of performance in real-time. Upon the completion of the application session, sub-session histograms may be compressed and then saved into a log which can be fetched and uploaded to a host computer system for aggregation and storage into a database for server-side optimization analysis. | 04-30-2015 |
20150117666 | PROVIDING MULTICHANNEL AUDIO DATA RENDERING CAPABILITY IN A DATA PROCESSING DEVICE - A method includes distinctly assigning, through a driver component, each audio channel of multichannel audio data in a memory of a data processing device to one or more audio endpoint device(s) of a number of audio endpoint devices communicatively coupled to the data processing device. Each audio endpoint device of the number of audio endpoint devices is capable of supporting a number of audio channels less than a number of audio channels of the multichannel audio data. The method also includes routing, through a processor of the data processing device communicatively coupled to the memory, audio data related to the each audio channel to the appropriate one or more audio endpoint device(s) based on the assignment through the driver component to enable rendering of the multichannel audio data on the number of audio endpoint devices. | 04-30-2015 |
20150117536 | VIDEO DECODER TECHNIQUES - AVC decoding techniques include parsing a set of alternating slices of one or more picture frames and parsing another set of alternating slices of the one or more picture frames. The parsed set of alternating slices of the one or more picture frames are buffered separately from the parsed other set of alternating slices of the one or more picture frames. The buffered parsed set of alternating slices and the other buffered parsed set of alternating slices are alternating decoded. | 04-30-2015 |
20150116879 | IN-RUSH CURRENT LIMITING SWITCH CONTROL - A subsystem is configured to apply a voltage source to a gated circuit domain in a manner that limits in-rush current and affords minimal time delay. A control signal turns on a wake-up switch that connects the voltage source to the domain. The equivalent series resistance of the wake-up switch has a magnitude that limits the transient charge current to the gated domain. A digital control circuit monitors the resulting rising domain voltage and determines when the domain voltage reaches operating level, at which point additional transient current will be minimal. The control circuit then activates a primary switch that connects the voltage source to the domain through a series resistance of negligible magnitude. An adjustment element provides the option to permanently set a control signal that marginally reduces the time at which the control circuit activates the primary switch to compensate for variations in circuit parameters. | 04-30-2015 |
20150116523 | IMAGE SIGNAL PROCESSOR AND METHOD FOR GENERATING IMAGE STATISTICS - An image signal processor (ISP) and a method of generating image statistics. One embodiment of the ISP includes: (1) a client configured to employ image statistics to process a current frame of a scene if changes in the current frame relative to a previous frame of the scene rise above a threshold, and (2) a statistics engine associated with the client and configured to generate the image statistics based on the current frame if the changes rise above the threshold. | 04-30-2015 |
20150116294 | POWER-EFFICIENT CONTROL OF DISPLAY DATA CONFIGURED TO BE RENDERED ON A DISPLAY UNIT OF A DATA PROCESSING DEVICE - A method includes scanning, through a processor of a data processing device communicatively coupled to a memory, display data to be rendered on a display unit communicatively coupled to the data processing device for boundaries of one or more virtual object(s) therein. The method also includes rendering, through the processor, a portion of the display data outside the boundaries of the one or more virtual object(s) at a reduced level compared to a portion of the display data within the boundaries on the display unit. | 04-30-2015 |
20150113538 | HIERARCHICAL STAGING AREAS FOR SCHEDULING THREADS FOR EXECUTION - One embodiment of the present invention is a computer-implemented method for scheduling a thread group for execution on a processing engine that includes identifying a first thread group included in a first set of thread groups that can be issued for execution on the processing engine, where the first thread group includes one or more threads. The method also includes transferring the first thread group from the first set of thread groups to a second set of thread groups, allocating hardware resources to the first thread group, and selecting the first thread group from the second set of thread groups for execution on the processing engine. One advantage of the disclosed technique is that a scheduler only allocates limited hardware resources to thread groups that are, in fact, ready to be issued for execution, thereby conserving those resources in a manner that is generally more efficient than conventional techniques. | 04-23-2015 |
20150113300 | BATTERY OPERATED COMPUTER SYSTEM - Disclosed herein is a computer system operating on a local power supply of finite capacity has a plurality of system components each connected to a voltage supply system to draw current for their operation. The computer system includes a measuring circuit connected to detect prevailing usage of the local power supply, for example, a battery. The supply system is connected to receive an indication from the measuring circuit of excessive usage and is adapted to reduce the available supply voltage to selected ones of the system components. Each system component is associated with a clock controller which selects a clock frequency for operation of a component in dependence on the available voltage supply. Also disclosed is a supply system for a computer device operating on a local power supply of finite capacity. | 04-23-2015 |
20150113254 | EFFICIENCY THROUGH A DISTRIBUTED INSTRUCTION SET ARCHITECTURE - A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction. | 04-23-2015 |
20150112690 | LOW POWER ALWAYS-ON VOICE TRIGGER ARCHITECTURE - The description is directed to systems and methods for a low-power, hands-free voice triggering of a main processing complex of a computing system to wake from a suspended state. An always-on voice activity detection module samples output received from a microphone in the computing system and determines whether a portion of the sampled output potentially contains a triggering keyphrase. A special purpose audio processing engine is turned on to confirm the presence of the triggering keyphrase in the sampled output before triggering the main processing complex of the computing system to wake from the suspended state. | 04-23-2015 |
20150110455 | UTILITY AND METHOD FOR CAPTURING COMPUTER-GENERATED VIDEO OUTPUT - A video capture utility and method for a computer system. In one embodiment, the video capture utility includes: (1) a circular buffer allocated in a memory of the computer system to store at most a predefined video length, (2) a video output interceptor executable in a processor of the computer system and operable to receive and store video output most recently generated by an application program and (3) a video output extractor executable in the processor and operable to prompt contents of the circular buffer to be copied from the circular buffer to another location. | 04-23-2015 |
20150109486 | FILTERING EXTRANEOUS IMAGE DATA IN CAMERA SYSTEMS - In one embodiment of the present invention a camera system includes a frame screener that configures an image signal processor (ISP) to ignore pixel data that does not contribute to image quality. For each image frame, the frame screener processes packets of pixel data. If the pixel data included in a particular packet is associated with an overflow state, then the frame screener determines whether the image frame should be discarded based on the number of processed pixels associated with the image frame and a minimum pixel threshold. If the frame screener determines that the image frame should be discarded, then the frame screener configures the ISP to bypass any memory and computational operations associated with the packet of pixel data. Advantageously, because the ISP disregards extraneous pixel data, the ISP may perform fewer operations and consume less power than an ISP included in a conventional camera system. | 04-23-2015 |
20150109473 | PROGRAMMING A CAMERA SENSOR - One embodiment of the present invention sets forth a method for performing camera startup operations substantially in parallel. The method includes programming graphics hardware to perform one or more processing functions for a camera. The method also includes allocating resources for one or more camera operations. The method also includes programming the camera sensor to capture an image and initiating a preview of the image on a display associated with the camera. Finally, the steps of allocating resources and programming the camera sensor are performed substantially in parallel. One advantage of the disclosed technique is that the launch time for the camera is reduced. This allows a user to take a picture more quickly and thus improves the user experience. | 04-23-2015 |
20150109315 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MAPPING TILES TO PHYSICAL MEMORY LOCATIONS - A system, method, and computer program product are provided for mapping tiles to physical memory locations. In use, a plurality of virtual tiles associated with a texture is identified. Additionally, a request to perform a mapping of the plurality of virtual tiles to one or more physical memory locations is received. Further, the plurality of virtual tiles is mapped to the one or more physical memory locations, utilizing a page table. | 04-23-2015 |
20150109309 | UNIFIED POSITION BASED SOLVER FOR VISUAL EFFECTS - A method for simulating visual effects is disclosed. The method comprises modeling each visual effect within a simulation as a set of associated particles with associated constraints applicable thereto. It also comprises predicting first velocities and first positions of a plurality of particles being used to simulate a visual effect based on an external force applied to the plurality of particles. Next, it comprises identifying a set of neighboring particles for each of the plurality of particles. The method also comprises solving a plurality of constraints related to the visual effect, wherein each of the plurality of constraints is solved for the plurality of particles in parallel. Lastly, responsive to the solving, the method comprises determining second velocities and second positions for the plurality of particles. | 04-23-2015 |
20150109300 | SYSTEM AND METHOD FOR COMPUTING REDUCED-RESOLUTION INDIRECT ILLUMINATION USING INTERPOLATED DIRECTIONAL INCOMING RADIANCE - A system for, and method of, computing reduced-resolution indirect illumination using interpolated directional incoming radiance and a graphics processing subsystem incorporating the system or the method. In one embodiment, the system includes: (1) a cone tracing shader executable in a graphics processing unit to compute directional incoming radiance cones for sparse pixels and project the directional incoming radiance cones on a basis and (2) an interpolation shader executable in the graphics processing unit to compute outgoing radiance values for untraced pixels based on directional incoming radiance values for neighboring ones of the sparse pixels. | 04-23-2015 |
20150109298 | COMPUTING SYSTEM AND METHOD FOR REPRESENTING VOLUMETRIC DATA FOR A SCENE - A computing system and method for representing volumetric data for a scene. One embodiment of the computing system includes: (1) a memory configured to store a three-dimensional (3D) clipmap data structure having at least one clip level and at least one mip level, and (2) a processor configured to generate voxelized data for a scene and cause the voxelized data to be stored in the 3D clipmap data structure. | 04-23-2015 |
20150109297 | GRAPHICS PROCESSING SUBSYSTEM AND METHOD FOR COMPUTING A THREE-DIMENSIONAL CLIPMAP - A graphics processing subsystem and method for computing a 3D clipmap. One embodiment of the subsystem includes: (1) a renderer operable to render a primitive surface representable by a 3D clipmap, (2) a geometry shader (GS) configured to select respective major-plane viewports for a plurality of clipmap levels, the major-plane viewports being sized to represent full spatial extents of the 3D clipmap relative to a render target (RT) for the plurality of clipmap levels, (3) a rasterizer configured to employ the respective major-plane viewports and the RT to rasterize a projection of the primitive surface onto a major plane corresponding to the respective major-plane viewports into pixels representing fragments of the primitive surface for each of the plurality of clipmap levels, and (4) a plurality of pixel shader (PS) instances configured to transform the fragments into respective voxels in the plurality of clipmap levels, thereby voxelizing the primitive surface. | 04-23-2015 |
20150109296 | GRAPHICS PROCESSING SUBSYSTEM AND METHOD FOR UPDATING VOXEL REPRESENTATION OF A SCENE - A graphics processing subsystem and method for updating a voxel representation of a scene. One embodiment of the graphics processing subsystem includes: (1) a memory configured to store a voxel representation of a scene having first and second regions to be updated, and (2) a graphics processing unit (GPU) operable to: (2a) unify the first and second regions into a bounding region if a volume thereof does not exceed summed volumes of the first and second regions by more than a tolerance, and (2b) generate voxels for the bounding region and cause the voxels to be stored in the voxel representation. | 04-23-2015 |
20150109289 | METHOD AND APPARATUS FOR SIMULATING STIFF STACKS - A computer implemented method of simulating a stack of objects represented as data within memory of a computer system is disclosed. The method comprises modeling the stack within a computer simulation as a set of associated primitives with associated constraints thereto in the memory, wherein the stack comprises a plurality of layers and wherein each layer comprises at least one primitive. The method further comprises estimating a height for each of the primitives in the stack and determining a respective scaling factor for each of the primitives in parallel, wherein each scaling factor is operable to adjust a mass value of each of the primitives. Also, the method comprises scaling a mass value of each of the primitives in accordance with a respective scaling factor in parallel. Finally, the method comprises solving over a plurality of constraints iteratively using a scaled mass value for each of the primitives. | 04-23-2015 |
20150109286 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR COMBINING LOW MOTION BLUR AND VARIABLE REFRESH RATE IN A DISPLAY - A system, method, and computer program product are provided for combining low motion blur and variable refresh rate in a display. In one embodiment, a hold-type display is operated in a first mode of operation where the hold-type display is dynamically refreshed such that the hold type display handles updates to image frames at unpredictable times and where for each of the image frames a backlight of the hold-type display is activated for an entire duration of display of the image frame. Additionally, it is determined that at least one predefined condition has been met. Further, in response to the determination, the hold-type display is operated in a second mode of operation where the hold-type display is statically refreshed such that the hold-type display handles updates to image frames at regular intervals and where for each of the image frames the backlight of the hold-type display is flashed. | 04-23-2015 |
20150108934 | DISTRIBUTED FAN CONTROL - A device for processing graphics data may include a plurality of graphics processing units. The device may include a fan to dissipate thermal energy generated during the operation of the plurality of graphics processing units. Each of the plurality of graphics processing units may generate a pulse width modulated signal to control the speed of the fan. The device may include one or more monitoring units configured to monitor a signal controlling the speed of the fan. One or more of the plurality of pulse width modulated signals may be adjusted based on the monitored signal. One or more of the plurality of pulse width modulated signals may be adjusted such that a signal controlling the fan maintains a desired duty cycle. | 04-23-2015 |
20150106729 | REMOTELY CONTROLLING ONE OR MORE DISPLAY UNIT(S) COMMUNICATIVELY COUPLED TO A DATA PROCESSING DEVICE AND/OR DISPLAY DATA RENDERED THEREON - A method includes executing a process on a data processing device, and defining, through a driver component, mapping between: the process and a display unit communicatively coupled to the data processing device, and one or more other processes executing on the data processing device and one or more other display unit(s) communicatively coupled to the data processing device. Based on the execution of the process on the data processing device, the method also includes providing a capability to: preview display data rendered on the one or more other display unit(s) through the display unit in a user interface provided through the process, and configure the display data rendered on the one or more other display unit(s) and/or one or more parameter(s) associated with the display data rendered on the one or more other display unit(s) and/or the one or more other display unit(s) directly through the preview. | 04-16-2015 |
20150106634 | SYSTEM AND METHOD FOR PROVIDING LOW-VOLTAGE, SELF-POWERED VOLTAGE MULTI-SENSING FEEDBACK - A system and method are provided for regulating a supply voltage of a device. The method includes the steps of determining whether a supply voltage for an analog multiplexor is below a threshold voltage. If the supply voltage for the analog multiplexor is below the threshold voltage, then the method includes the step of shorting the supply voltage to an output of the analog multiplexor. However, if the supply voltage for the analog multiplexor is above or equal to the threshold voltage, then the method includes the step of transmitting at least one input signal coupled to the analog multiplexor to the output of the analog multiplexor. A system configured to implement the method may include a power management integrated circuit configured to generate a supply voltage for a device and a device that includes a self-powered analog multiplexor with voltage sensing bypass switch. | 04-16-2015 |
20150103894 | SYSTEMS AND METHODS TO LIMIT LAG BETWEEN A CLIENT AND A SERVER FOR REMOTE COMPUTING - Novel solutions are described herein for providing a consistent quality of service, latency-wise, for remote processing by managing the process queues in a processing server and temporarily pausing frame production and delivery to limit the lag experienced by a user in a client device. The claimed embodiments limit the latency (lag) experienced by a user by preventing the production rate of rendered frames at the server from significantly outperforming the decoding and display of the received frames in the client device and avoiding the resultant lag. | 04-16-2015 |
20150103880 | ADAPTIVE VIDEO COMPRESSION FOR LATENCY CONTROL - One embodiment of the present invention sets forth a technique for adaptively compressing video frames. The technique includes encoding a first plurality of video frames based on a first video compression algorithm to generate first encoded video frames and transmitting the first encoded video frames to a client device. The technique further includes receiving a user input event, switching from the first video compression algorithm to a second video compression algorithm in response to the user input event, encoding a second plurality of video frames based on the second video compression algorithm to generate second encoded video frames, and transmitting the second encoded video frames to the client device. | 04-16-2015 |
20150103584 | CONFIGURABLE DELAY CIRCUIT AND METHOD OF CLOCK BUFFERING - A configurable delay circuit and a method of clock buffering. One embodiment of the configurable delay circuit includes: (1) a first delay stage electrically couplable in series to a second delay stage, the first delay stage and the second delay stage each having an input port electrically coupled to a signal source, and (2) a delay path select circuit electrically coupled between the first delay stage and the second delay stage, and operable to select between a delay path including the first delay stage and another delay path including the first delay stage and the second delay stage. | 04-16-2015 |
20150103252 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GAMMA CORRECTION IN A VIDEO OR IMAGE PROCESSING ENGINE - A system and method are provided for generating a gamma adjusted value. The method comprises generating a logarithm space representation of an input value by computing a logarithm of the input value, computing a logarithm space gamma-adjusted value by multiplying the logarithm space representation with a current gamma value, and generating the gamma adjusted value by computing an antilogarithm of the logarithm space gamma-adjusted value. | 04-16-2015 |
20150103193 | METHOD AND APPARATUS FOR LONG TERM IMAGE EXPOSURE WITH IMAGE STABILIZATION ON A MOBILE DEVICE - A method for displaying a live preview image on a mobile device is disclosed. The method comprises computing a history color value and confidence value for each pixel of a sensor of a camera on the device. Further, it comprises obtaining a new frame of pixels from the camera. Subsequently, for each pixel in the new frame, the method comprises: (a) determining if a pixel color is similar to a corresponding history color value and if a confidence corresponding to a pixel is above a predetermined threshold; (b) if the pixel color is not similar to the history color value and the confidence is above the predetermined threshold, displaying the history color value on the preview when displaying the new frame; and (c) if the pixel color is similar to the history color value or the confidence is below the threshold, displaying the pixel color on the preview instead. | 04-16-2015 |
20150103184 | METHOD AND SYSTEM FOR VISUAL TRACKING OF A SUBJECT FOR AUTOMATIC METERING USING A MOBILE DEVICE - Embodiments of the present invention provide a novel solution that enables mobile devices to continuously track interesting subjects by creating dynamic visual models that can be used to detect and track subjects in-real time through total occlusion or even if a subject temporarily leaves the mobile device's field of view. Additionally, embodiments of the present invention use an online learning scheme that dynamically adjusts tracking procedures responsive to any appearance and/or environmental changes associated with an interesting subject that may occur over a period of time. In this manner, embodiments of the present invention can determine a more optimal focus position that allows movement by either the mobile device or the subject during the performance of auto-focusing procedures and also enables other camera parameters to properly calibrate (meter) themselves based on the focus position determined. | 04-16-2015 |
20150103183 | METHOD AND APPARATUS FOR DEVICE ORIENTATION TRACKING USING A VISUAL GYROSCOPE - A method for tracking device orientation on a portable device is disclosed. The method comprises initializing a device orientation to a sensor orientation, wherein the sensor orientation is based on information from an inertial measurement unit (IMU) sensor. It also comprises initiating visual tracking using a camera on the portable device and capturing a frame. Next, it comprises determining a plurality of visual features in the frame and matching the frame to a keyframe, wherein capture of the keyframe precedes capture of the frame. Subsequently, it comprises computing a rotation amount between the frame and the keyframe. Responsive to a determination that a rotational distance between the frame and the keyframe exceeds a predetermined threshold, promoting the frame to a keyframe status and adding it to a first orientation map and adjusting the frame with all prior captured keyframes. | 04-16-2015 |
20150103087 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DISCARDING PIXEL SAMPLES - A system, method, and computer program product are provided for discarding pixel samples. The method includes the steps of completing shading operations for a pixel set including one or more pixels to generate per-sample shaded attributes according to a shader program executed by a processing pipeline. Discard information for the pixel set is evaluated and one or more per-sample shaded attributes for at least one pixel in the pixel set are discarded based on the evaluated discard information. | 04-16-2015 |
20150102799 | JITTER DETERMINATION OF NOISY ELECTRICAL SIGNALS - A jitter analysis system includes an electronic circuit having a noisy electrical signal with jitter along a baseline of the signal. The jitter analysis system also includes a sampling unit coupled to the noisy electrical signal that provides waveform samples of the noisy electrical timing signal and a jitter detection unit coupled to the sampling unit that provides baseline crossings of the noisy electrical signal, wherein the baseline crossings are determined from a selection of the waveform samples proximate the baseline of the signal. A jitter determination method is also provided. | 04-16-2015 |
20150102788 | Energy-Based Control Of A Switching Regulator - A system and method are provided for controlling a switching voltage regulator circuit. An energy difference between a stored energy of a switching voltage regulator and a target energy is determined. A control variable of the switching voltage regulator is computed based on the energy difference and the control variable is applied to a current control mechanism of the switching voltage regulator. In one embodiment, the control variable is pulse width of a control signal. | 04-16-2015 |
20150102483 | MICROELECTRONIC PACKAGE WITH STRESS-TOLERANT SOLDER BUMP PATTERN - A microelectronic package includes larger diameter solder bumps and smaller diameter solder bumps for coupling an interposer to a packaging substrate. The larger diameter solder bumps are positioned on a peripheral surface of the interposer and the smaller diameter solder bumps are positioned on a center surface of the interposer. The solder bumps positioned in the peripheral region can more reliably withstand the higher mechanical stresses that occur in this peripheral region during operation of the microelectronic package. | 04-16-2015 |
20150100884 | HARDWARE OVERLAY ASSIGNMENT - An aspect of the present invention proposes a novel approach that can reduce the total number of the overlays to be composited during the display of graphical output in a mobile computing device. As a result, the total number of memory bandwidth and the usage of a graphics processing unit by a pre-compositor can be decreased significantly. According to one embodiment, this new approach is implemented with a display panel with embedded memory which supports a partial update, or refresh feature. Which such a feature, the layer compositor (typically either the display controller or GPU) is able to keep track of actively updating regions of a display panel by checking if each layer has new content to be displayed. | 04-09-2015 |
20150100840 | SCAN SYSTEMS AND METHODS - Efficient scan system presented can comprise: an array including a plurality of array non scannable components and a plurality of array quasi-scannable components wherein each column of the array includes at least one of the plurality of array quasi-scannable components; and an input interface configured to receive and selectively forward data and scan information to at least a portion of the array. At least a portion of the plurality of array quasi-scannable components can form a diagonal pattern in the array. The input interface can include: an input interface selection component wherein an output of the input interface selection component is communicatively coupled to an input of the input interface quasi-scannable component associated with one row and an input of the input interface selection component is communicatively coupled to an output of one of the plurality of array quasi-scannable components associated with another row. | 04-09-2015 |
20150100802 | REDUCING POWER CONSUMPTION IN MULTI-DISPLAY ENVIRONMENTS - The disclosure is directed to a system and method for selectively controlling display power consumption in a system with a first and second display. While the system is in a non-idle state and while an application that is actively executing has an active window on the first display, a determination is made that the second display is inactive. In response to the determination, and while the system is still in the non-idle state, the second display is switched from a full power state to a low power state. | 04-09-2015 |
20150100764 | DYNAMICALLY DETECTING UNIFORMITY AND ELIMINATING REDUNDANT COMPUTATIONS TO REDUCE POWER CONSUMPTION - One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of threads, the SM designates one thread as the anchor thread. The SM disables execution units assigned to all of the threads except the anchor thread. The anchor execution unit, assigned to the anchor thread, executes the operation on the uniform set of input operands. Subsequently, the SM sets the outputs of the non-anchor threads included in the uniform group of threads to equal the value of the anchor execution unit output. Advantageously, by exploiting the uniformity of data to reduce the number of execution units that execute, the SM dramatically reduces the power consumption compared to conventional SMs. | 04-09-2015 |
20150100324 | AUDIO ENCODER PERFORMANCE FOR MIRACAST - A method for encoding audio comprises receiving an unencoded audio signal and monitoring a user interface for user interface events. The method continues by selecting one of a plurality of transform windows to hold a defined quantity of audio samples based upon a detected one or more user interface interaction events and associated transient information. The plurality of transform windows comprises a long window sequence comprising a single window with a first quantity of samples, and a short window sequence comprising a plurality of second windows each comprising a second quantity of samples. A sum of samples of the plurality of second windows equals the first plurality of samples. The short window sequence is selected when a particular user interface interaction event is received from the user interface. | 04-09-2015 |
20150098020 | METHOD AND SYSTEM FOR BUFFER LEVEL BASED FRAME RATE RECOVERY - Embodiments of the present invention can measure internal buffer levels (e.g., queue levels) within the sink device and dynamically adjust step size values responsive to buffer level conditions that dynamically alter the sink frame rate. As such, embodiments of the present invention can find an equivalent of the source device frame rate on the sink device based on the sink device's own clock speed. In this manner, transmission bandwidth may be preserved as clocking information does not to need to be continuously communicated between the source device and the sink device. | 04-09-2015 |
20150097851 | APPROACH TO CACHING DECODED TEXTURE DATA WITH VARIABLE DIMENSIONS - A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map. | 04-09-2015 |
20150097847 | MANAGING MEMORY REGIONS TO SUPPORT SPARSE MAPPINGS - One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management. | 04-09-2015 |
20150097845 | HEURISTICS FOR IMPROVING PERFORMANCE IN A TILE-BASED ARCHITECTURE - One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled. | 04-09-2015 |
20150097844 | SPLIT DRIVER TO CONTROL MULTIPLE GRAPHICS PROCESSORS IN A COMPUTER SYSTEM - A computer system includes an operating system having a kernel and configured to launch a plurality of computing processes. The system also includes a plurality of graphics processing units (GPUs), a front-end driver module, and a plurality of back-end driver modules. The GPUs are configured to execute instructions on behalf of the computing processes subject to a GPU service request. The front-end driver module is loaded into the kernel and configured to receive the GPU service request from one of the computing processes. Each back-end driver module is associated with one or more of the GPUs and configured to receive the GPU service request from the front-end driver module and pass the GPU service request to an associated GPU. | 04-09-2015 |
20150095980 | CONTROLLING SHARING OF CONTENT BETWEEN DATA PROCESSING DEVICES - A method includes executing an instance of a process on each of a data processing device and one or more another data processing device(s), and authenticating, registering or pairing the one or more another data processing device(s) with the data processing device through a Personal Area Network (PAN) associated with a user of the data processing device and/or a computer network based on an identifier. The method also includes sharing content generated and/or stored in the data processing device with the one or more another data processing device(s) through the PAN and/or the computer network, and providing, through the execution of the instance of the process, a capability to the user of the data processing device to control the sharing of the content with the one or more another data processing device(s). The control of the sharing includes restricting the sharing based on controlling a parameter of the sharing. | 04-02-2015 |
20150095394 | MATH PROCESSING BY DETECTION OF ELEMENTARY VALUED OPERANDS - One embodiment of the present invention includes a method for simplifying arithmetic operations by detecting operands with elementary values such as zero or 1.0. Computer and graphics processing systems perform a great number of multiply-add operations. In a significant portion of these operations, the values of one or more of the operands are zero or 1.0. By detecting the occurrence of these elementary values, math operations can be greatly simplified, for example by eliminating multiply operations when one multiplicand is zero or 1.0 or eliminating add operations when one addend is zero. The simplified math operations resulting from detecting elementary valued operands provide significant savings in overhead power, dynamic processing power, and cycle time. | 04-02-2015 |