| NEWPORT FAB, LLC DBA JAZZ SEMICONDUCTOR Patent applications |
| Patent application number | Title | Published |
|---|
| 20110018109 | Deep silicon via for grounding of circuits and devices, emitter ballasting and isolation - According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die. | 01-27-2011 |
| 20100127326 | MOS transistor with a reduced on-resistance and area product - According to an exemplary embodiment, a MOS transistor, such as an LDMOS transistor, includes a gate having a first side situated immediately adjacent to at least one source region and at least one body tie region. The MOS transistor further includes a drain region spaced apart from a second side of the gate. The MOS transistor further includes a body region in contact with the at least one body tie region, where the at least one body tie region is electrically connected to the at least one source region. The MOS transistor further includes a lightly doped region separating the drain region from the second side of the gate. The lightly doped region can isolate the body region from an underlying substrate. | 05-27-2010 |
| 20090149213 | Semiconductor on insulator (SOI) switching circuit - A disclosed embodiment is a switching circuit including a number of transistors fabricated in a device layer situated over a buried oxide layer and a bulk semiconductor layer. Each transistor has a source/drain junction that does not contact the buried oxide layer, thus forming a source/drain junction capacitance. The disclosed switching circuit also includes at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thus electrically isolating at least one of the transistors in the switching circuit so as to reduce voltage and current fluctuations in the device layer. The disclosed switching circuit may be coupled to a power amplifier or a low noise amplifier and an antenna in a wireless communications device, and be controlled by a switch control signal in the wireless communications device. | 06-11-2009 |
| 20090146210 | Semiconductor on insulator (SOI) structure and method for fabrication - A disclosed embodiment is a semiconductor on insulator (SOI) structure comprising a buried oxide layer over a bulk semiconductor layer, and a device layer over the buried oxide layer. At least one transistor is fabricated in the device layer, wherein a source/drain junction of the transistor does not contact the buried oxide layer, thereby causing the source/drain junction to have a source/drain junction capacitance. The SOI structure also comprises at least one trench extending through the device layer and contacting a top surface of the buried oxide layer, thereby electrically isolating the at least one transistor. In one embodiment the at least one trench is formed after fabrication of the at least one transistor and is filled with only dielectric. In one embodiment, one or more wells may be formed in the device layer. In one embodiment the bulk semiconductor layer has a high resistivity of typically about 1000 ohms-centimeter or greater. | 06-11-2009 |
| 20090128768 | Self-planarized passivation dielectric for liquid crystal on silicon structure and related method - According to an exemplary embodiment, a liquid crystal on silicon (LCoS) structure includes a number of pixel electrodes overlying an interlayer dielectric, where diagonally adjacent pixel electrodes are separated by a gap. The LCoS structure further includes a self-planarizing passivation dielectric situated over the pixel electrodes and in the gap, where the self-planarizing passivation dielectric has a selected thickness. The self-planarizing passivation dielectric can be an Oxide-Nitride-Oxide (ONO) stack. The selected thickness of the self-planarizing passivation dielectric causes the self-planarizing passivation dielectric to have a substantially planar top surface. In one embodiment, the thickness of the self-planarizing passivation dielectric can be approximately equal to twice a width of the gap. | 05-21-2009 |
| 20090085066 | Method for integrating high voltage and high speed bipolar transistors on a substrate and related structure - According to an exemplary embodiment, a method for integrating a high speed bipolar transistor in a high speed transistor region of a substrate with a high voltage transistor in a high voltage transistor region of the substrate includes forming a buried subcollector in the high speed transistor region of the substrate. The method further includes forming a first high energy implant region in the high voltage transistor region of the substrate, where the first high energy implant region extends to a depth greater than a depth of a peak dopant concentration of the buried subcollector, thereby increasing a collector-to-emitter breakdown voltage of the high voltage transistor. The collector-to-emitter breakdown voltage of the high voltage transistor can be greater than approximately 5.0 volts. The high speed bipolar transistor can have a cutoff frequency of greater approximately 200.0 GHz. | 04-02-2009 |
