| NETLOGIC MICROSYSTEMS, INC. Patent applications |
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| 20120089762 | DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 04-12-2012 |
| 20120066477 | ADVANCED PROCESSOR WITH MECHANISM FOR PACKET DISTRIBUTION AT HIGH LINE RATE - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 03-15-2012 |
| 20120046925 | MODEL BASED DISTORTION REDUCTION FOR POWER AMPLIFIERS - A method of processing a signal is disclosed. The method comprises generating a digital signal, converting the digital signal to an analog signal, and generating an amplified analog signal having distortions. The method further comprises converting the amplified analog signal to a feedback digital signal at a sample rate and updating a model of the distortions based on the feedback digital signal. | 02-23-2012 |
| 20120030445 | ADVANCED PROCESSOR TRANSLATION LOOKASIDE BUFFER MANAGEMENT IN A MULTITHREADED SYSTEM - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 02-02-2012 |
| 20120029881 | DISTORTION CANCELLATION USING ADAPTIVE LINEARIZATION - An adaptive distortion reduction system comprising: an input interface to receive a distorted signal comprising a distorted component and an undistorted component, the distorted component being at least in part attributed to an exogenous signal; and an adaptive distortion reduction module coupled to the input interface, to perform linearization based at least in part on the distorted signal and information associated with the exogenous signal, to obtain a corrected signal that is substantially similar to the undistorted component; wherein the adaptive self-linearization module includes: a first digital signal processor (DSP) that is adapted to obtain a filter transfer function that approximates a transfer function to be corrected; and a second DSP that is configured using configuration parameters of the first DSP. | 02-02-2012 |
| 20120027029 | SYSTEM AND METHOD FOR OFFLOADING PACKET PROTOCOL ENCAPSULATION FROM SOFTWARE - A method is provided for offloading packet protocol encapsulation from software. In operation, pointer information is received. Furthermore, packet protocol encapsulation is offloaded from software by assembling packets in hardware, using the pointer information. | 02-02-2012 |
| 20120017049 | METHOD AND APPARATUS FOR IMPLEMENTING CACHE COHERENCY OF A PROCESSOR - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 01-19-2012 |
| 20110085553 | OUTPUT QUEUED SWITCH WITH A PARALLEL SHARED MEMORY, AND METHOD OF OPERATING SAME - A network switch includes an input layer to receive a data stream with a set of cells. Each cell includes data and a header to designate a destination device. The input layer includes a set of input layer circuits. A selected input layer circuit of the set of input layer circuits receives the data stream. The selected input layer circuit includes a set of queues corresponding to a set of destination devices. The selected input layer circuit is configured to assign a selected cell from the data stream to a selected queue of the set of queues. The selected queue corresponds to a selected destination device specified by the header of the selected cell. An intermediate layer includes a set of intermediate layer circuits, each intermediate layer circuit has a set of buffers corresponding to the set of destination devices. A selected intermediate layer circuit of the set of intermediate layer circuits receives the selected cell and assigns the selected cell to a selected buffer corresponding to the selected destination device. An output layer includes a set of output layer circuits corresponding to the set of destination devices. A selected output layer circuit of the set of output layer circuits stores the selected cell prior to routing the selected cell to a selected output layer circuit output node. | 04-14-2011 |
| 20110013643 | ADVANCED TELECOMMUNICATIONS ROUTER AND CROSSBAR SWITCH CONTROLLER - The invention relates to a crossbar switch controller including an input terminal configured to receive a set of service request signals from a set of virtual output queues each comprising a set of packets. The invention also includes a matrix circuit coupled to the input terminal and configured to represent the set of service request signals in the form of a matrix, wherein each service request signal is described by a row position M and a column position N. The invention further includes an output terminal configured to receive a portion of the set of packets during an epoch, an arbiter circuit configured to iteratively scan the matrix during the epoch and issue the set of grant signals to the virtual output queues to determine which service requests are granted, and an arbiter controller configured to initiate the arbiter circuit with an array of non-conflicting matrix elements. Whereby, the arbiter circuit scans the matrix during a first epoch, issues the set of grant signals, allows the set of granted service requests to substantially complete, and if necessary, scans the matrix during subsequent epochs. The invention also relates to a crossbar switch controller including an arbitration pre-processor coupled to the input terminal and the matrix circuit, and configured to represent the set of service request signals in the form of a mapping matrix, and further configured to transform a first mapping position of the service request signal to a second mapping position based, in part, on a mapping algorithm. The invention also includes an arbitration post-processor coupled to the output terminal and the matrix circuit, and further configured to transform the second mapping position of the service request signal back to the first mapping position. | 01-20-2011 |
| 20100318763 | SYSTEMS AND METHODS FOR UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE - Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses. | 12-16-2010 |
| 20100318703 | DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 12-16-2010 |
| 20100254709 | System and Method for Performing Concatenation of Diversely Routed Channels - A system and method are provided for performing Local Centre Authorization Service (LCAS) in a network system, the system having a data aligner configured to align bytes of input data according to groups of members. The system also including an LCAS control manager configured to generate de-sequencing control commands in response to data input from the data aligner. The system further including a de-sequencer configured to de-sequence the input data input from the data aligner according to de-sequencing control commands received from the LCAS control manager. | 10-07-2010 |
