NEC ELECTRONICS CORPORATION Patent applications |
Patent application number | Title | Published |
20130234285 | INDUCTOR ELEMENT, INDUCTOR ELEMENT MANUFACTURING METHOD, AND SEMICONDUCTOR DEVICE WITH INDUCTOR ELEMENT MOUNTED THEREON - An inductor element is formed in a multiple layer lead structure including a lead, an insulative layer that insulates leads above and below, and a via provided in the insulative layer and connecting leads above and below wherein lead layers are multiply laminated layers, characterized in that: at least a portion of at least a pair of vertically adjacent leads are coiled leads; the coiled leads are connected in series, wherein current directions of vertically adjacent coiled leads are the same by a via provided on an end portion thereof, and form a serial inductance; and an inter-lead capacitance of the vertically adjacent coiled leads is larger than an inter-lead capacitance between other coiled leads formed in the same lead layer. | 09-12-2013 |
20130044530 | LAYOUT OF MEMORY CELLS AND INPUT/OUTPUT CIRCUITRY IN A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit. | 02-21-2013 |
20120108060 | SEMICONDUCTOR DEVICE HAVING SILICON-DIFFUSED METAL WIRING LAYER AND ITS MANUFACTURING METHOD - In a semiconductor device, an insulating interlayer having a groove is formed on an insulating underlayer. A silicon-diffused metal layer including no metal silicide is buried in the groove. A metal diffusion barrier layer is formed on the silicon-diffused metal layer and the insulating interlayer. | 05-03-2012 |
20120096421 | SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS, DATA PROCESSING METHOD THEREOF, AND CONTROL PROGRAM THEREOF - A semiconductor integrated circuit design apparatus ( | 04-19-2012 |
20110131397 | MULTIPROCESSOR SYSTEM AND MULTIPROCESSOR CONTROL METHOD - A multiprocessor system includes a memory that stores a program; an address notification register; a first processor; and a second processor, in which the first processor stores address information indicating an address from which the program is executed in the address notification register, when the first processor notifies an interrupt request to the second processor and causes the second processor to execute the program, and the second processor obtains the interrupt request notified from the first processor and the address information stored in the address notification register, and starts to execute the program from the address indicated by the obtained address information. | 06-02-2011 |
20110070741 | METHOD OF CLEANING PLASMA ETCHING APPARATUS - Method of cleaning a plasma etching apparatus capable of suppressing variation in line width among wafers in a single lot, and improving throughput in the cleaning process, includes steps of supplying a cleaning gas into a chamber of a plasma etching apparatus; igniting a plasma of the cleaning gas in the chamber; and allowing plasma cleaning to proceed in the chamber, by bringing the cleaning gas in plasma form into contact with a deposit adhered on the inner wall of the chamber so as to etch off the deposit, wherein in the step of plasma cleaning in the chamber, intensity of plasma emission ascribable to the deposit adhered on the inner wall of the chamber is detected in a time-dependent manner, and the plasma cleaning in the chamber is terminated based on changes in the intensity of the plasma emission. | 03-24-2011 |
20110062585 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip, an electrode pad provided in the semiconductor chip, in which the electrode pad includes Al as a major constituent and further includes Cu, a coupling member coupled to the electrode pad, in which the coupling member primarily includes Cu, a plurality of layers of Cu and Al alloys formed between the electrode pad and the coupling member, and an encapsulating resin that includes a halogen of less than or equal to 1000 ppm, in which the encapsulating resin encapsulates the semiconductor chip, the electrode pad, and the coupling member. The plurality of layers of Cu and Al alloys includes a CuAl | 03-17-2011 |
20110051934 | DATA RECEIVING DEVICE, DATA RECEIVING METHOD AND PROGRAM - A data receiving device includes an elastic buffer which receives data as receiving data and adjusts timing with a sender, the data being scrambled and sent from the sender, an interpolation circuit which performs predetermined interpolation processing on the data subjected to timing adjustment by the elastic buffer to output the data, and a descramble circuit which descrambles the data output from the interpolation circuit. The receiving data includes data set for adjusting timing. The data set is for adjusting timing with the sender. The interpolation circuit replaces existing data with data for adjusting timing and outputs the data for adjusting timing as required after first receiving normal data for adjusting timing so that a desired number of data for adjusting timing is included in the data set for adjusting timing. | 03-03-2011 |
20110051576 | Optical disk device - An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced. | 03-03-2011 |
20110051541 | Semiconductor device - A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal. | 03-03-2011 |
20110051534 | Semiconductor storage device and its control method - A semiconductor storage device, in which successive reading and successive writing of data having a predetermined length from and to a memory cell specified by a certain address are performed, includes a plurality of memory cells, address input terminals through which the address is input, data output terminals through which read data having the predetermined length is output, and data input terminals through which write data having the predetermine length is input. Part of the address input terminals are also used as the data output terminals. In this way, the operation of successive reading and successive writing performed in succession at the same address can be made faster without increasing the number of terminals. | 03-03-2011 |
20110051488 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device to an exemplary aspect of the present invention includes a plurality of memory cells, a plurality of word lines, a plurality of bit line pairs, a plurality of column selectors, a common signal line pair including one common line commonly connected to one of each of the plurality of bit line pairs, and the other common line commonly connected to the other of each of the plurality of bit line pairs, a sense amplifier amplifying the potential difference of the common signal line pair, and a plurality of capacitance adding circuits that balance with parasitic capacitances of the column selectors which are not selected, the capacitance adding circuits being provided respectively between the one of each of the bit line pairs and the other common line and between the other of each of the bit line pairs and the one common line. | 03-03-2011 |
20110050983 | Apparatus, method, and program product for autofocus - An exemplary embodiment of the present invention is an autofocus method that includes moving a focus lens according to an image signal generated from an image of a subject formed by an imaging optical system with a focus lens, obtaining a focus contrast of each of multiple image signals generated in a case of moving a position of the focus lens; and determining a moving direction of the focus lens according to the multiple obtained focus contrasts in response to a focus instruction. | 03-03-2011 |
20110050761 | PIXEL CIRCUIT AND DISPLAY DEVICE - A display device uses a plurality of pixel circuits each of which includes a light-emitting element; a light-emission control switching element; a current control circuit for supplying a driving current, which corresponds to gray-level display data, to the light-emitting element via the light-emission control switching element; and a voltage control circuit, which includes a first capacitance element for storing a voltage corresponding to the gray-level display data, and controls ON/OFF operation of the light-emission switching element in accordance with the voltage stored. If the gray-level display data is data for causing the light-emitting element to display less than a certain luminance, the current control circuit supplies the light-emitting element with a constant driving current corresponding to the gray-level display data for displaying the certain luminance, and the voltage control circuit controls the ON time of the light-emission control switching element in accordance with a voltage stored. | 03-03-2011 |
20110050746 | LEVEL SHIFT CIRCUIT, AND DRIVER AND DISPLAY DEVICE USING THE SAME - A level shift circuit includes a first circuit connected between a first power supply terminal (PST) and an output terminal (OT) of the level shift circuit to set OT to a first voltage (V | 03-03-2011 |
20110050342 | Push-pull amplifier circuit and operational amplifier circuit using the same - A push-pull amplifier including first to third current paths. The first current path includes first transistor allowing first current to flow through the first current path according to input signal. The second current path includes second transistor allowing second current having opposite phase to the first current to flow through the second current path according to the first current; first resistor; and third transistor connected to one end of the first resistor and having control terminal connected to the other end of the first resistor. The third current path includes output terminal; fourth transistor allowing current having the same phase as the first current to flow through the third current path according to the input signal; and fifth transistor allowing current having the same phase as the second current to flow through the third current path according to voltage of first node between the first resistor and the third transistor. | 03-03-2011 |
20110050327 | Semiconductor device - Provided is a semiconductor device including: a first charge pump circuit that generates a first control signal based on electric charge of a first pumping capacitor accumulated through a first drive transistor; a second charge pump circuit that generates a second control signal based on electric charge of a second pumping capacitor accumulated through a second drive transistor; a third charge pump circuit that transfers electric charge between an output terminal and a reference voltage terminal through a third drive transistor; and a fourth charge pump circuit that transfers electric charge between the output terminal and the reference voltage terminal through a fourth drive transistor. Conductive states of the first and third drive transistors are controlled based on the second control signal, and conductive states of the second and fourth drive transistors are controlled based on the first control signal. | 03-03-2011 |
20110050197 | Reference current or voltage generation circuit - A reference current or voltage generation circuit which forms a self feedback circuit with a plurality of transistors and generates a reference current or a reference voltage, the reference current or voltage generation circuit including a normally-on type transistor that has a gate connected to a first power supply and is connected between a node and a second power supply. Moreover, a voltage of the node is substantially equal to a voltage of the first power supply when the reference current or voltage generation circuit does not operate, and the voltage of the node fluctuates from the voltage of the first power supply toward a voltage of the second power supply by a predetermined value or more when the reference current or voltage generation circuit operates. | 03-03-2011 |
20110049632 | SEMICONDUCTOR DEVICE - A semiconductor device capable of dissipating heat, which has been produced in an ESD protection element, to the exterior of the device rapidly and efficiently includes an ESD protection element having a drain region, a source region and a gate electrode, and a thermal diffusion portion. The thermal diffusion portion, which has been formed on the drain region, has a metal layer electrically connected to a pad, and contacts connecting the drain region and metal layer. The metal layer has a first wiring trace extending along the gate electrode, and second wiring traces intersecting the first wiring trace perpendicularly. The contacts are connected to intersections between the first wiring trace and the second wiring traces. Heat that has been produced at a pn-junction of the ESD protection element and transferred through a contact is diffused simultaneously in three directions through the first wiring trace and second wiring trace in the metal layer and is released into the pad. | 03-03-2011 |
20110044007 | Heat sink, semiconductor device, and method of manufacturing heat sink - A heat sink | 02-24-2011 |
20110043295 | Semiconductor device having an ESD protection circuit - A semiconductor integrated circuit, includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, a first transistor which has a source-drain route connected between an external terminal and a first voltage, and a gate terminal connected to the output terminal of the operational amplifier; and a second transistor which has a source-drain route connected between the first input terminal of the operational amplifier and the first voltage, and a gate terminal connected to the output terminal of the operational amplifier. | 02-24-2011 |
20110043262 | Input interface circuit - An input interface circuit according to the present invention includes an input first stage circuit that is connected to a signal terminal, where the signal terminal receives external data, and a phase adjustment circuit that adjusts an external input clock and a latch timing signal to be in phase, where the latch timing signal is output to latch circuits included in the input first stage circuit. The phase adjustment circuit adjusts delay time of the latch timing signal that passes through the clock tree circuit and is supplied to the latch circuit in response to a comparison result between the clock and an output from a replica delay circuit which is replicated from the clock. | 02-24-2011 |
20110042802 | Semiconductor device, external connection terminal, method of manufacturing semiconductor device, and method of manufacturing external connection terminal - A semiconductor device includes an electrode pad and an external connection terminal. The external connection terminal contains Sn equal to or more than 50 wt %, Sn and Pb equal to or more than 90 wt % in total, or Pb equal to or more than 85 wt %, and the surface thereof is coated with an Au layer. The thickness of the Au layer is preferably equal to or more than 10 nm and equal to or less than 1 μm. The weight of the Au layer is preferably equal to or less than 0.6% of the weight of the external connection terminal. | 02-24-2011 |
20110039396 | Semiconductor device and method of fabricating semiconductor device - A method of fabricating a semiconductor device from a semiconductor wafer, having external connecting terminals on one side of the semiconductor wafer and a cover layer on another side of the semiconductor wafer, includes forming a groove with a first width from the one side to at least an interface between the semiconductor wafer and the cover layer in the semiconductor wafer, and cutting the cover layer with a second width from a bottom side of the groove. The second width is narrower than the first width. | 02-17-2011 |
20110038979 | Die unit and method of manufacturing die unit - A die unit that maintains uniform quality of a work despite continuous operation is provided. The die unit includes a lower die holder including a base hole, an upper die holder including a through hole, a pillar having an end portion inserted to the base hole and the other end portion slidably inserted through the through hole, so as to allow the upper die holder to slide toward and away from the lower die holder, an annular bushing attached to the through hole so as to slide along the pillar, and a die element and a punch attached to one of the lower die holder and the upper die holder respectively. A spacer is provided at least one of between an inner circumferential surface of the through hole and the bushing, and between an inner circumferential surface of the base hole and the pillar, and the spacer has lower thermal conductivity than the upper die holder or the lower die holder on which the spacer is provided. | 02-17-2011 |
20110033982 | Lead-forming die and method of manufacturing semiconductor device utilizing lead-forming die - Provided is that a lead-forming die includes an upper die and a lower die disposed so as to oppose the upper die; a supporting unit for semiconductor package, provided on an upper face of the lower die; a moving unit provided on a lower face of the upper die and movable in a direction that the upper die and the lower die oppose each other; a plurality of shafts supported by the moving unit so as to axially move with respect thereto; a presser provided above the supporting unit for semiconductor package, and at a lower end portion of the shaft; and a locking device that stops a movement of the shaft, provided between the upper die and the moving unit. | 02-10-2011 |
20110032647 | Semiconductor device including esd protection field effect transistor with adjustable back gate potential - A semiconductor device includes a first circuit block powered by voltages at first and second power supply terminals, a second circuit block powered by voltages at third and fourth power supply terminals, a first ESD (electrostatic discharge) protection circuit including a first field effect transistor having a source, a drain, and a gate, where the gate and one of the source and the drain are connected to the first power supply terminal, the other of the source and the drain is connected to the third power supply terminal, and a first back gate potential adjusting circuit adapted to adjust a potential at a back gate of the first field effect transistor. The first field effect transistor includes a first conductivity type transistor formed in a first well of a second conductivity type serving as the back gate of the first field effect transistor. | 02-10-2011 |
20110032135 | D/A CONVERTER - A D-A converter includes a resistor string that generates a plurality of voltages including an upper limit voltage, a lower limit voltage, and an intermediate voltage, a first selector that selects and outputs a first voltage among the plurality of voltages according to a lower bit, the first voltage being selected from the intermediate voltage and a voltage lower than the intermediate voltage, a second selector that selects and outputs a second voltage according to a higher bit, the second voltage being one of a lower power supply voltage and the intermediate voltage or a voltage higher than the intermediate voltage, a third selector that selects and outputs a third voltage according to the higher bit, the third voltage being selected from the lower limit voltage and the lower power supply voltage; and an amplifier that adds the first voltage and the second voltage and subtracts the third voltage. | 02-10-2011 |
20110032128 | ANALOG-DIGITAL CONVERTER CIRCUIT AND CALIBRATION METHOD - Provided is an analog-digital converter circuit having a normal mode for converting a received analog signal into a digital signal, and a calibration mode for adjusting an offset voltage of a comparator, the analog-digital converter including: a first comparator having a first analog signal input terminal supplied with an analog signal, and a first reference signal input terminal supplied with a first reference signal, in the normal mode; and a first calibration circuit that adjusts an offset voltage of the first comparator. In the calibration mode, assuming that a calibration resolution of the first calibration circuit is Δ | 02-10-2011 |
20110032031 | AMPLIFIER CIRCUIT AND LIGHT RECEIVING AMPLIFIER CIRCUIT USING THE SAME - An amplifier circuit includes an amplifier unit that amplifies a signal received by an input terminal and outputs the amplified signal to an output terminal, a feedback capacitor that is connected between the input terminal of the amplifier and the output terminal, and a controller that varies a capacitance in the feedback capacitor for a certain period when a potential of the output terminal in the amplifier unit becomes higher or lower than a certain potential. | 02-10-2011 |
20110032014 | Delay locked loop circuit and signal delay method - A multiplier PLL multiplies a reference clock and outputs the multiplied clock. A DLL compares the clock output from the multiplier PLL with a clock obtained by delaying the clock output from the multiplier PLL. The DLL generates a delay signal having a given amount of delay based on the comparison result. A delay control signal operation circuit generates a delay control signal based on the delay signal generated by the DLL. A first delay circuit delays an input signal based on the delay control signal generated by the delay control signal operation circuit. | 02-10-2011 |
20110032004 | Light-receving circuit and semiconductor device having same - A light-receiving circuit includes a photodiode that converts an input optical signal to a current signal; a current-voltage converting circuit that outputs an output voltage signal obtained by adding a reference voltage to a voltage signal proportional to the current value of the current signal; and an input current limiting unit that supplies the current-voltage converting circuit with the current signal upon limiting the current value of this current signal based upon the reference voltage in such a manner that the output voltage signal will not exceed a constant value irrespective of the value of the reference voltage. | 02-10-2011 |
20110031553 | Semiconductor device having transistors each having gate electrode of different metal ratio and production process thereof - A semiconductor device with integrated MIS field-effect transistors includes a first transistor including a first gate electrode having a composition represented by MAx, and a second transistor including a second gate electrode having a composition represented by MAy, in which M includes at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co, and Ti, A includes at least one of silicon and germanium, and 002-10-2011 | |
20110029757 | STREAM PROCESSOR AND TASK MANAGEMENT METHOD THEREOF - A stream processor includes a programmable main processor MP, and a coprocessor CP that executes an extension instruction, the extension instruction being different from a basic instruction executed by the main processor MP. The main processor MP includes a coprocessor controller CPC outputting the extension instruction to the coprocessor CP, and the coprocessor CP includes a task controller TC, the task controller controlling a task performed based on the extension instruction and outputting status information ST of the task on every clock. The coprocessor controller CPC controls the coprocessor CP based on the status information ST and a basic instruction executed by the main processor MP in background in advance. | 02-03-2011 |
20110027987 | Method and apparatus for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment. | 02-03-2011 |
20110026312 | Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor - A semiconductor device includes a memory cell which includes a first inverter and a second inverter, the first inverter includes a first drive transistor and a first load transistor, the second inverter includes a second drive transistor and a second load transistor, and an input terminal and an output terminal thereof, respectively, connected to an input terminal and an output terminal of the first inverter, a first transmission transistor provided between the output terminal of the first inverter and a line of a first bit line pair, a second transmission transistor provided between the output terminal of the second inverter and another line of the first bit line pair, a third transmission transistor provided between the output terminal of the first inverter and a line of a second bit line pair, a fourth transmission transistor provided between the output terminal of the second inverter and another line of the second bit line pair, and a first isolation transistor which isolates the second drive transistor and the first transmission transistor. A first active region in which the first transmission transistor, the second transmission transistor, the second drive transistor, and the first isolation transistor are formed, is formed in a continuous region. The first isolation transistor is provided between the second drive transistor and the first transmission transistor. | 02-03-2011 |
20110025416 | Differential amplifier - A differential amplifier including: 1st transistor that is connected between 1st power-supply terminal and 1st output terminal, and has a control terminal receiving one of the differential input signals; 2nd transistor that is connected between 2nd power-supply terminal and 1st output terminal, and has a control terminal receiving the other of the differential input signals; 1st switch that is connected between 1st power-supply terminal and 1st transistor; 3rd transistor that is connected between 2nd power-supply terminal and 2nd output terminal, and has a control terminal is input to one of the differential input signals; 4th transistor that is connected between 1st power-supply terminal and 2nd output terminal, and has a control terminal receiving the other of the differential input signals; 2nd switch that is connected between 2nd power-supply terminal and 3rd transistor. Drive state of 1st and 2nd switches are controlled by a control signal. | 02-03-2011 |
20110024869 | DESIGN METHOD, DESIGN PROGRAM AND DESIGN SUPPORT DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A design method for a semiconductor integrated circuit, includes : a first calculating step; a second calculating step; and a setting step. The first step is a step of calculating a consumption current amount of a layout target circuit based on circuit information. The second calculating step is a step of calculating a suppliable current amount per unit area in a region where a power can be supplied from a power wiring line. The setting step is a step of setting a cell size of the layout target circuit based on the consumption current amount so that a consumption current amount per unit area of the layout target circuit is smaller than the suppliable current amount per unit area. | 02-03-2011 |
20110024865 | SEMICONDUCTOR LIGHT RECEIVING DEVICE - According to an exemplary aspect of the present invention, at least a semiconductor mesa and a semiconductor layer covering at least the side wall of the mesa and a semiconductor mesa are formed on an n-type semiconductor substrate. The semiconductor mesa includes at least a light absorption layer and a p-type contact layer. The principal surface of the semiconductor substrate tilts at an angle θ to the (100) plane. The angle θ is 0.1 degree≦|θ|≦10 degrees. | 02-03-2011 |
20110024863 | Mesa photodiode and method for manufacturing the same - A mesa photodiode which includes a mesa, the side wall of the mesa (a light-receiving region mesa) and at least a shoulder portion of the mesa in an upper face of the mesa are continuously covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type (an undoped InP layer, for example) that is grown on the side wall and the upper face of the mesa. In the semiconductor layer, a layer thickness D | 02-03-2011 |
20110024843 | Semiconductor device including memory having nodes connected with continuous diffusion layer but isolated from each other by transistor - A semiconductor device includes a latch circuit which includes a first node for keeping a first potential corresponding to a data, and a second node for keeping a second potential corresponding to the same data, a diffusion layer continuously formed between the first node and the second node, and a transistor provided on the diffusion layer to isolate the first node from the second node. | 02-03-2011 |
20110024832 | Semiconductor apparatus and manufacturing method thereof - A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions. | 02-03-2011 |
20110024826 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - A nonvolatile semiconductor memory device includes a first columnar protrusion and a second columnar protrusion formed to be spaced out on a surface of a semiconductor substrate, and the first and the second columnar protrusions each include a split gate nonvolatile memory cell in which a first source/drain region and a second source/drain region are formed at a surrounding part and an extremity, and in which a first layered structure, in which a charge accumulating film and a memory gate line are layered, and a second layered structure, in which a gate oxide film and a control gate line are layered, are formed on a surface of a sidewall between the surrounding part and the extremity. The first layered structure is also formed between the first and second columnar protrusions, whereby the memory gate line of the first columnar protrusion and the second columnar protrusion is connected each other. | 02-03-2011 |
20110024041 | Method of manufacturing semiconductor device, and etching apparatus - An etching apparatus includes a process chamber into which an etching gas is introduced, an electrode for generating plasma disposed in the process chamber, a stage disposed in the process chamber, on which a substrate is placed, and a shadow ring disposed in the process chamber and placed above the stage, so as to cover the circumferential portion and an inner region adjacent thereto of the substrate in a non-contact manner. The shadow ring has an irregular pattern on the inner circumferential edge thereof. | 02-03-2011 |
20110019379 | Printed wiring board, semiconductor device, and method for manufacturing printed wiring board - A printed wiring board includes a plurality of lands arranged in a mounting area allowing therein mounting of an electronic component; and an wiring respectively connected to a specific land which is at least one of the outermost lands arranged outermostly out of all lands, wherein a connection portion of the specific land and the wiring connected to the specific land is positioned inside a closed curve which collectively surrounds, by the shortest path, all of the outermost lands formed in the mounting area. | 01-27-2011 |
20110018853 | SIGNAL LINE DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE - A signal line driving circuit according to an exemplary aspect of the present invention includes: a first amplifier; a second amplifier; a first charge share switch connected between an output terminal of the first amplifier and an output terminal of the second amplifier; a first output switch connected between an output node of the first amplifier and the output terminal of the first amplifier; a second charge share switch connected between a node between the first output switch and the output terminal of the first amplifier and an input terminal of the first amplifier; and a first input switch connected to the input terminal of the first amplifier. | 01-27-2011 |
20110018576 | METHOD AND DEVICE FOR TESTING SEMICONDUCTOR - A semiconductor testing device of the prevent invention includes a current detecting circuit, an electric current drawing circuit, and a determining device. The electric current drawing circuit is connected to a semiconductor device under test, and draws a branched electric current branched from a measured electric current output from a second terminal based on predetermined electric voltage. The current detecting circuit is connected to the semiconductor device, and detects a detection current obtained by subtracting the branched electric current from the measured electric current. The determining device determines a quality of the semiconductor device based on the detection current. | 01-27-2011 |
20110018569 | TEST APPARATUS OF SEMICONDUCTOR DEVICE AND METHOD THEREOF - A test apparatus according to the present invention includes a probe card recognition unit that recognizes positions of at least two probe card marks formed to a probe card and assumes a probe card mark connection line connecting the positions of the probe card marks, a backing material recognition unit that recognizes positions of at least two backing material marks formed to a backing material where a semiconductor chip is fixed thereto and assumes a backing material mark connection line connecting the positions of the backing material mark, a positional relationship recognition unit that recognizes a positional relationship between the probe card and the backing material according to the probe card mark connection line and the backing material mark connection line, and a correction unit that corrects the position of at least one of the probe card and the backing material according to the positional relationship. | 01-27-2011 |
20110018137 | Method of manufacturing semiconductor device, semiconductor device thus manufactured, and semiconductor manufacturing apparatus - A plurality of projections, respectively given later as cores of a plurality of external connection terminals, are formed first by selectively forming a curable resin layer over a protective insulating film; flat portions are then formed respectively on the top surfaces of the plurality of projections, by pressing a molding jig having a flat opposing surface onto the top surfaces of the plurality of projections, before the projections are cured; the plurality of projections are cured; and the plurality of external connection terminals, and the plurality of interconnects are formed, by selectively forming an electro-conductive film over the plurality of projections, the protective insulating film, and the plurality of electrode pads. | 01-27-2011 |
20110018090 | SEMICONDUCTOR DEVICE - To suppress stress variation on a channel forming region, a semiconductor device includes an element isolating region on the semiconductor substrate principal surface, and an element forming region on the principal surface to be surrounded by the element isolating region. The principal surface has orthogonal first and second directions. A circumferential shape of the element forming region has a first side extending along the first direction. The element forming region has a first transistor region (TR | 01-27-2011 |
20110016445 | Layout design system and layout design method - In a layout design of a semiconductor circuit, by selecting a frequently-used layout cell based on a layout design, a common location (coordinate) at which dummy metal is arranged is specified. A new layout cell in which dummy metal is arranged in advance at the specified arrangement location is generated. Dummy metal is arranged by replacing the frequently-used layout cell from which the new layout cell is generated by the new layout cell having dummy metal or by overlapping them. Thus, process such as wiring correction in which the amount of data depends on processing speed can be carried out by use of the inexpensive computer having low throughputs and the small amount of memory. | 01-20-2011 |
20110014785 | Method for manufacturing semiconductor device, and semiconductor manufacturing apparatus used in said method - This method includes an electrode pad forming process for forming an electrode pad on a substrate, a solder bump forming process for forming a solder bump on the electrode pad, at least part of the surface of the solder bump being covered with a flux, and an oxygen exposure process for supplying an oxygen gas having reactive properties, such as an ozone (O | 01-20-2011 |
20110013500 | INFORMATION REPRODUCTION APPARATUS AND INFORMATION REPRODUCTION METHOD - A small size circuit reproducing data with low error rate even when a signal includes a non-linear distortion is desired. In such a circuit, the Viterbi method is performed. In the Viterbi method, branch metrics are calculated based on a difference of a sampled reproduction signal and a predetermined expectation values. Path metrics are calculated from the branch metrics. Paths among the plurality of paths having the calculated path metrics and merging at a same state are compared with one another. Based on the magnitude of the compared path metrics, survivor path is selected. In the circuit, for the path metrics of paths merging at a same state, offset corresponding to a determination result until a merging point is added to the paths for the comparison for determining the survivor path from the plurality of merging paths. | 01-20-2011 |
20110012268 | SEMICONDUCTOR DEVICE - After opening a via hole, the bottom portion and the top portion are rounded by etching performed twice. As a result, resistance of the via hole can be reduced and its quality and life can be enhanced. | 01-20-2011 |
20110012265 | Semiconductor device - A semiconductor device includes a wiring board that has a conductive pattern formed on at least one principal surface, and an IC chip that is mounted on the wiring board. The IC chip includes a plurality of electrodes to make conductor connection with the wiring board. The conductive pattern includes a lead line pattern and a heat dissipation pattern. The lead line pattern is connected with at least one of the plurality of electrodes through a conductor. The heat dissipation pattern is physically spaced from the IC chip and the lead line pattern and has a larger surface area than the lead line pattern. Further, the lead line pattern and the heat dissipation pattern are placed opposite to each other with a gap therebetween, and their opposite parts respectively have interdigitated shapes and are arranged with the respective interdigitated shapes engaging with each other with the gap therebetween. | 01-20-2011 |
20110012108 | Semiconductor device having process failure detection circuit and semiconductor device production method - A semiconductor device includes a cell array and a plurality of process failure detection circuits each having a layout pattern substantially identical to that of a cell of the cell array in a dummy region arranged around the cell array. Each of the process failure detection circuits includes a dummy pattern that equalizes a degree of density/sparsity of a peripheral part of the cell array with that of a central part of the cell array. The process failure detection circuits include a process failure detection circuit having a layout pattern formed with a stricter pattern margin in at least one manufacturing process, compared with the layout pattern of the cell of the cell array. | 01-20-2011 |
20110007857 | Communication device - A communication device includes a current information storage unit | 01-13-2011 |
20110007592 | Semiconductor storage device and refresh control method thereof - In a large capacity semiconductor storage device having a multi-bank configuration, it is desired to reduce a peak current of one refresh operation, to avoid an interference between adjacent banks, and to prevent a data breaking of a memory cell caused by a lack of a data hold time. A semiconductor storage device includes: a memory cell array part including a plurality of banks; a refresh control circuit configured to output a refresh timing control signal periodically; and an access control circuit configured to perform a refresh operation on a group of banks which are not adjacent to one another in accordance with a preset combination of banks which are simultaneously activated and a preset activating order when the refresh timing control signal is supplied. | 01-13-2011 |
20110007442 | Rapid discharging circuit upon detection of abnormality - Provided is a protection circuit that is connected between a power supply terminal and an output terminal, and turns off an output transistor when an abnormality occurs in a system, the output transistor outputting a current to a load connected to the output terminal, the protection circuit including: a first discharge unit that is connected between a gate electrode of the output transistor and the power supply terminal, and discharges an electric charge of the gate electrode until a potential of the gate electrode becomes equal to a power supply potential, when an abnormality occurs in the system, and a second discharge unit that is connected between the gate electrode and a source electrode of the output transistor, and discharges the electric charge of the gate electrode until the potential of the gate electrode becomes equal to an output potential, when an abnormality occurs in the system. | 01-13-2011 |
20110006939 | D/A converter - A resistor string type D/A converter in accordance with an exemplary aspect of the present invention includes a resistor string, switches, a higher-order decoder, a lower-order decoder, and a conversion unit. The resistor string generates a plurality of analog voltages by dividing a voltage between a first reference voltage and a second reference voltage. Each of the switches is provided for a respective one of a plurality of voltage drawing points. The higher-order decoder generates a higher-order control signal according to the value of higher bits of an input digital signal. The lower-order decoder generates a lower-order control signal corresponding to the value of lower bits of the input digital signal. The conversion unit outputs a voltage between a pair of the analog voltage values obtained through a pair of switches based on the lower-order control signal. | 01-13-2011 |
20110006813 | Input circuit and semiconductor integrated circuit including the same - An input circuit, includes a first buffer circuit whose output is couple to an output signal terminal of the input circuit, and whose input is coupled to an input signal terminal of the input circuit, a second buffer circuit, a third buffer circuit, a first differential amplification circuit whose first input is coupled to a first external power source terminal, whose second input is coupled to an output of the second buffer circuit, and whose output is coupled to an input of the second buffer circuit, a second differential amplification circuit whose first input is coupled to a second external power source terminal, whose second input is coupled to an output of the third buffer circuit, and whose output is coupled to an input of the third buffer circuit, a first resistance whose one end is coupled to the output of the first differential amplification circuit, and whose another end is coupled between the input signal terminal of the input circuit and the input of the first buffer circuit, a second resistance whose one end is coupled to the output of the second differential amplification circuit, and whose another end is coupled between the input signal terminal of the input circuit and the input of the first buffer circuit. | 01-13-2011 |
20110006797 | PROBE CARD AND TEST EQUIPMENT - Provided are a probe card including a first area group including a plurality of first areas, each including a plurality of probes for input pad and probes for output pad, the first areas being aligned in L rows by M columns (L, M: natural number); and a second area group including a plurality of second areas, each including a plurality of probes for input pad, the second areas being aligned in (L×N) rows by M columns (N: natural number); and the first area group and the second area group are continuously connected in a column direction according to the chip alignment, such that the first areas and the second areas are aligned in {L+(L×N)} rows by M columns. | 01-13-2011 |
20110004777 | DISPLAY CONTROL CIRCUIT AND DISPLAY CONTROL METHOD - A display control circuit in accordance with an exemplary aspect of the present invention is including a display memory that stores display data to be displayed on a display device, the display memory being supplied with electric power through a power-supply terminal, a power-supply unit that connects the power-supply terminal to a power-supply or a ground according to a request, and a control unit that requests the power-supply unit to connect the power-supply terminal to a ground when the display memory enters a standby mode in which no displaying is performed on the display device, and requests the power-supply unit to connect the power-supply terminal to a power supply when a predetermined time has elapsed after the request even if the display memory is in the standby mode. | 01-06-2011 |
20110003472 | WIRING SUBSTRATE FOR MOUNTING SEMICONDUCTORS, METHOD OF MANUFACTURING THE SAME, AND SEMICONDUCTOR PACKAGE - A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates. | 01-06-2011 |
20110002164 | Semiconductor device - A charge pump circuit, whose output is connected to a first node, starts a boosting operation after start of a test period. A load current application circuit supplies a load current to the first node during the test period. A voltage of the first node is a write voltage. A memory circuit stops application of the write voltage to a memory cell during the test period, and applies the write voltage to the memory cell after end of the test period. A high voltage detection unit compares the write voltage and a predetermined voltage to determine whether or not the write voltage is increased to the predetermined voltage. If the write voltage is less than the predetermined voltage at the end of the test period, the high voltage detection unit activates a disable signal. If the disable signal is activated, the charge pump circuit stops the boosting operation. | 01-06-2011 |
20110002076 | SEMICONDUCTOR DEVICE - A semiconductor device including an electrostatic discharge element that protects the semiconductor device from electrostatic destruction is provided. The semiconductor device includes a first circuit, a second circuit, a connection node connecting the first node to the second node, and a first inductor connected between the connection node and a first power supply. The first inductor and the electrostatic discharge element are formed so that they vertically overlap each other. | 01-06-2011 |
20110001739 | DISPLAY APPARATUS AND METHOD OF TESTING THE SAME - A display apparatus includes a delay generation circuit that generates a reference signal and a competing signal, the competing signal being generated based on a delay set signal, an input order judgment circuit that judges an input order of the reference signal and the competing signal, a delay set circuit that generates the delay set signal based on a judgment result in the input order judgment circuit, and an internal synchronous control circuit that controls transfer of display data between a CPU and a display panel. An operation test of the internal synchronous control circuit is performed using the reference signal and the competing signal. Hence, fault coverage can be enhanced. | 01-06-2011 |
20110001649 | Differential chopper comparator and A/D converter including the same - A differential chopper comparator compares an input signal voltage and a first voltage, and includes a first capacitor, a second capacitor, and a differential amplification unit including a differential amplification circuit. Either the input signal voltage or the first voltage is applied to one end of the first capacitor via a first switch unit. A fixed voltage is applied to one end of the second capacitor via a second switch unit. Either a non-inverting input terminal or an inverting input terminal of the differential amplification circuit is connected to the other end of the first capacitor, and the other terminal is connected to the other end of the second capacitor. An impedance of the first switch unit side viewed from one end of the first capacitor and an impedance of the second switch unit side viewed from one end of the second capacitor are substantially same. | 01-06-2011 |
20110001516 | CIRCUIT, APPARATUS, AND METHOD FOR SIGNAL TRANSFER - A signal transfer circuit according to the present invention includes a differential signal generation unit that generates a differential signal according to a voltage difference between two input signals, a voltage difference detection unit that detects a voltage difference between the two input signals input to the differential signal generation unit, and a signal output unit that outputs a signal including a predetermined value if the voltage difference is not detected by the voltage difference detection unit, and outputs the differential signal generated by the differential signal generation unit if the voltage difference is detected by the voltage detection unit. | 01-06-2011 |
20110001509 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor integrated circuit device includes: terminals | 01-06-2011 |
20110001508 | SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - In order to reduce the number of electrodes included in test patterns, the semiconductor integrated circuit includes, a plurality of first and second chains, a first common electrode connected to one end of each first chain, a second common electrode connected to one end of each second chain, and a plurality of selection electrodes. Each selection electrode is connected to the other end of any one of the plurality of first chains and to the other end of any one of the plurality of second chains. When a test target chain is selected from the plurality of first chains, a first reference voltage is applied to the first common electrode, a second reference voltage is applied to a target selection electrode that is connected to the test target chain, and a current flowing in the target selection electrode is measured to obtain a resistance value of the test target chain. | 01-06-2011 |
20110001226 | LEAD FRAME, AND ELECTRONIC PART USING THE SAME - A lead frame includes a die pad on which at least one IC chip is mounted, a plurality of leads that electrically connect the IC chip and at least one external element, and a plurality of projections that are formed in at least one edge of the die pad. The projections are used as at least one bonding point that connect with at least one free terminal of the IC chip or as references of positioning when the IC chip is arranged on the die pad. | 01-06-2011 |
20110001216 | Semiconductor device and manufacturing method thereof - A manufacturing method of a semiconductor device includes: forming a wiring in a first interlayer insulating layer in a first region; etching an surface portion of the first interlayer insulating layer in a second region; | 01-06-2011 |
20100333052 | Method of manufacturing semiconductor device, semiconductor inspection apparatus, and program - A reliability reference storage unit stores reference data for dividing semiconductor devices into equal to or more than three reliability ranks on the basis of the magnitude of an overlay error between a first interconnect layer and a second interconnect layer disposed over the first interconnect layer. An error storage unit stores overlay errors measured at multiple points within the surface of a semiconductor wafer. An error calculation unit calculates the overlay errors for a plurality of semiconductor chips on the basis of the coordinates of the plurality of semiconductor chips within the surface of the semiconductor wafer and the overlay errors stored in the error storage unit. A reliability information providing unit provides reliability information indicating reliability ranks to the plurality of semiconductor chips on the basis of the overlay errors for the plurality of semiconductor chips and reference data. | 12-30-2010 |
20100332932 | TEST METHOD, TEST CONTROL PROGRAM AND SEMICONDUCTOR DEVICE - In a method of performing a test on a logic circuit in accordance with an exemplary aspect of the present invention, the test is performed by supplying a clock signal from a clock supply circuit to a plurality of clock domains operating by a clock signal of a same frequency. The method includes calculating a number of test patterns of each of the plurality of internal clock domains; classifying the plurality of clock domains into a plurality of groups based on the calculated number of test patterns; and assigning a clock supply circuit independently to each of the groups into which the clock domains are classified. | 12-30-2010 |
20100332874 | MICROCOMPUTER AND MICROCOMPUTER SYSTEM - A microcomputer includes a CPU, a standby controller that controls setting of and recovering from a sleep mode of the CPU, an output terminal, a first timer, an output terminal controller, and a second timer. When the first timer performs predetermined time measurement when the CPU is in the sleep mode, the output terminal controller changes the level of the output terminal while maintaining the sleep mode. The second timer starts time measurement when the output terminal controller changes the level of the output terminal in the sleep mode. The standby controller performs recovering from the sleep mode of the CPU when the second timer performs a prescribed time measurement. | 12-30-2010 |
20100330796 | Manufacturing method of semiconductor device - The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm | 12-30-2010 |
20100329584 | Image processing device, image processing method and non-transitory computer readable medium recording image processing program - A first exemplary aspect of the present invention is an image processing device that executes image processing including first image processing and second image processing by using a pipeline mechanism, the image processing device including: a first processing unit that executes the first image processing on an input image data, generates history information recording specifics of processing executed in the first image processing, and outputs the history information to the first processing unit; and a second processing unit that executes the second image processing on the image data obtained in the first image processing according to the output history information. | 12-30-2010 |
20100328358 | Driver circuit - A driver circuit according to the present invention includes a grayscale circuit, an amplifier circuit, a comparison circuit, and a sampling timing adjusting circuit. The grayscale circuit generates a grayscale voltage from grayscale data. The amplifier circuit generates a video output from the grayscale voltage. The comparison circuit compares the grayscale voltage with the video output and outputs a comparison result. The sampling timing adjusting circuit adjusts a sampling timing signal for sampling the video signal based on the comparison result to generate an adjusted sampling timing signal. | 12-30-2010 |
20100327964 | Semiconductor device and method of removing semiconductor device noise - A semiconductor device includes: a noise detecting circuit; an input signal delaying circuit; and a mask circuit. The noise detecting circuit detects noise superimposed on an input signal and outputs a mask signal during a predetermined time period. The input signal delaying circuit delays the input signal and outputs a delay signal thereof. The mask circuit outputs an output signal in which the delay signal is masked based on the mask signal. | 12-30-2010 |
20100327951 | Semiconductor integrated circuit - A semiconductor integrated circuit includes a first circuit, a second circuit and a control circuit. The first circuit is configured by a first MOS transistor, and a threshold voltage of the first MOS transistor is a first threshold voltage. The second circuit has same logic as the first circuit, and is configured by a second MOS transistor. A threshold voltage of the second MOS transistor is a second threshold voltage, and the second threshold voltage is lower than the first threshold voltage. The control circuit makes one of the first circuit and the second circuit operate depending on a temperature of a chip. The first circuit and the second circuit are installed in a chip. | 12-30-2010 |
20100327846 | SEMICONDUCTOR APPARATUS - Provided is a semiconductor apparatus including a divided voltage generation circuit that includes a first resistor element and a first transistor connected in series between a first power supply and a second power supply and generates a divided voltage by dividing a voltage difference between the first power supply and the second power supply with a resistance ratio of the first resistor element and the first transistor specified according to a level of a first current flowing to the first transistor, and a current control circuit that includes a second transistor that is connected in a mirror configuration to the first transistor and determines the level of the first current by a control current flowing from a first terminal to a second terminal, and increases and decreases the control current according to an increase and decrease in a voltage difference between the first power supply and a ground power supply. | 12-30-2010 |
20100327467 | Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device - A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. | 12-30-2010 |
20100327447 | Method of manufacturing semiconductor device and semiconductor device - A method of manufacturing a semiconductor device includes forming a barrier metal film including a high melting point metal in a concave portion formed in an insulating film formed over a substrate; forming a seed alloy film including copper and an impurity metal different from the copper over the barrier metal film so as to fill a portion of the concave portion; forming a plated metal film containing copper as a major ingredient over the seed alloy film so as to fill the concave portion; first heat-treating the seed alloy film and the plated metal film at 200° C. or higher and for ten minutes or less; removing the plated metal film, the seed alloy film, and the barrier metal film which are exposed to the outside of the concave portion, after the first heat-treating; and second heat-treating the seed alloy film and the plated metal film. | 12-30-2010 |
20100327427 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a wiring layer, a semiconductor chip which is arranged on the wiring layer with a gap there between, the semiconductor chip being electrically connected to the wiring layer through a connecting portion, a first sealing member which is filled in a space between the wiring layer and the semiconductor chip, and a second sealing member which coats the semiconductor chip. The first sealing member and the second sealing member include same organic resin, the organic resin including inorganic filler. The second sealing member has larger content of inorganic filler than the first sealing member. | 12-30-2010 |
20100327403 | Semiconductor chip, semiconductor wafer, method of manufacturing semiconductor chip - One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides. | 12-30-2010 |
20100327366 | SEMICONDUCTOR DEVICE - A first adjusting metal, capable of varying the threshold voltage of a first-conductivity-type transistor of a complementary transistor, is added to the first-conductivity-type transistor and a second-conductivity-type transistor at the same time, and a diffusion suppressive element, capable of suppressing diffusion of the first adjusting metal, is added from above a metal gate electrode of the second-conductivity-type transistor. | 12-30-2010 |
20100321084 | Level shift circuit - A level shift circuit includes a level shift voltage generation circuit that receives an input signal having an amplitude between a first voltage system power supply voltage and a ground potential and outputs an output signal voltage having an amplitude between a second voltage system power supply voltage and the ground potential, a replica circuit configured to be a replica of the level shift voltage generation circuit, the replica circuit monitoring a threshold voltage of a first voltage system and a threshold voltage of a second voltage system, and enabling the level shift voltage generation circuit to generate of the output voltage synchronized in such a manner that, when the input voltage crosses the logic threshold of the first voltage system, the output voltage crosses the logic threshold of the second voltage system, and a bias generation circuit that generates a bias for adjusting variations of the output voltages of the level shift voltage generation circuit and the replica circuit, and supplies the bias to the level shift voltage generation circuit and the replica circuit. | 12-23-2010 |
20100321071 | Semiconductor integrated circuit - A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit. | 12-23-2010 |
20100320539 | Semiconductor device with electrostatic protection device - A semiconductor device has an SOI (Silicon On Insulator) structure and comprising a P-channel FET and an N-channel FET which are formed on an insulating film. The semiconductor device includes: at least two of first, second, third and fourth PN-junction elements. The first PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of source/drain regions of the P-channel FET and the N-channel FET, respectively. The second PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the source/drain region and a channel region in the P-channel FET, respectively. The third PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of a channel region and the source/drain region in the N-channel FET, respectively. The fourth PN-junction element is formed from a P-type semiconductor layer and an N-type semiconductor layer having the same impurity concentrations as those of the channel regions of the N-channel FET and the P-channel FET, respectively. At least two PN-junction elements are connected in series in a forward bias between two different terminals to form an electrostatic protection device. | 12-23-2010 |
20100320521 | Semiconductor device - A semiconductor device according to an exemplary embodiment of the present invention includes a memory cell including an information storage portion including a capacitor upper electrode of a DRAM cell and a capacitor lower electrode formed below the upper electrode and an access transistor for controlling access to the information storage portion, a bit-line connected to the access transistor to write or read data to or from the information storage portion, a word line connected to a gate electrode of the access transistor to control the access transistor, and a capacitive element including an upper electrode made from a same layer as a first metal line formed above the capacitor upper electrode and a lower electrode made from a same layer as the capacitor upper electrode, the capacitive element being formed outside an area where the memory cell is formed. | 12-23-2010 |
20100318864 | Fault location estimation device, fault location estimation method, and program - A fault location estimation device includes: a faulty scan chain identification unit that identifies a faulty scan chain and its fault type based on result of operation verification test; a faulty scan FF narrowing unit that compares test result of the faulty scan chain with simulation result for determining a faulty scan FF range beginning at the location of a scan FF where both results differ; and a path trace narrowing unit that references logic circuit configuration information, signal line expected value, a failure-observed scan FF, and test result of a defective circuit to extract a scan FF on the faulty scan chain, which may be reached from a failure-observed scan FF observed on a normal scan chain by tracing back a failure propagation path while performing implication procedure for an input side, and thereby further narrows the faulty scan FF range determined by the faulty scan FF narrowing unit. | 12-16-2010 |
20100318706 | BUS ARBITRATION CIRCUIT AND BUS ARBITRATION METHOD - Provided is a bus arbitration circuit including: a fixed priority determination circuit that grants a bus use right to an access request from a higher priority bus master among access requests from a plurality of bus masters; and a determination adjustment circuit that determines whether or not to assert the access request from the plurality of bus masters to the fixed priority determination circuit. The determination adjustment circuit masks an access request from a bus master which is granted the bus use right, for a given period of time, when the access request from the bus master which is granted the bus use right and an access request from a bus master which is not granted the bus use right compete with each other. | 12-16-2010 |
20100317200 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order. | 12-16-2010 |
20100316338 | OPTICAL COMMUNICATION MODULE AND METHOD OF MANUFACTURING THE SAME - An optical communication module includes a CAN member including a conductive stem member where an optical electronic device is mounted and a conducive lens cap that holds an optical lens optically coupled with the optical electronic device, is connected to the stem member in a conductive state, and covers a surrounding portion of the optical electronic device; a conductive cylindrical holder which is disposed around the lens cap, is fixed to the CAN member in an insulation state through an insulating resin, and is provided with an opening facing the optical lens; and an optical receptacle including an optical member that is optically coupled with the optical lens and the optical electronic device through the opening and a holding frame that holds the optical member inside. | 12-16-2010 |
20100315407 | Display control circuit - A display control circuit for a display includes a plurality of amplifiers connected to data lines of a display panel, the plurality of amplifiers being configured to apply a gray-scale voltage to the data lines when a bias current is supplied, and a control circuit that supplies a bias current to the amplifiers, wherein the control circuit detects an operating state of at least one amplifier among the plurality of amplifiers that operates by the bias current in a first time region, and causes the plurality of amplifiers to operate by supplying the bias current for a predetermined period according to the detection result in a second time region after the first time region. | 12-16-2010 |
20100315406 | Image data transfer to cascade-connected display panel drivers - A display device is provided with a display panel; first to n-th cascade-connected drivers (n being an integer of two or more); a controller transmitting compressed image data to the first driver. The i-th driver of the first to n-th drivers includes a drive circuitry driving the display panel; a first bus adapted to data transfer to the (i+1)-th driver of the first to n-th drivers; a second bus adapted to data transfer to the driver circuitry; and a decompression section receiving the compressed image data from the (i−1)-th driver of the first to n-th drivers or the controller. The decompression section of the i-th driver transfers the received compressed image data to the (i+1)-th driver through the first bus thereof, when the received compressed image data are not associated with the i-th driver. When the received compressed image data are associated with the i-th driver, the decompression section of the i-th driver decompresses the received compressed image data to generate decompressed image data and feeds the decompressed image data to the drive circuitry through the second bus. The drive circuitry drives the display panel in response to the decompressed image data. | 12-16-2010 |
20100315402 | Display panel driving method, gate driver, and display apparatus - A method of driving a display panel in which a voltage polarity reverse cycle of a data signal is three or more scan periods, and multiple scan lines are driven by switching between a first and a second scan orders by a predetermined period. The method includes setting a display pattern as a first maximum current pattern, the display pattern in which the multiple scan lines are driven in the first scan order and a number of charge and discharge of the data signal becomes a maximum number, and specifying that the number of charge and discharge of the data signal when displaying the first maximum current pattern in the second scan order is to be ½ of that of the data signal when displaying the first maximum current pattern in the first scan order. Further, the voltage polarity reverse cycle for specifying the first and the second scan orders is one frame period. | 12-16-2010 |
20100315172 | Spread spectrum clock generator and semiconductor device - A spread spectrum clock generator includes a voltage-controlled oscillator generating an operation clock, a feedback control unit, a modulated pulse generation unit generating a pulse signal obtained by performing a delta-sigma modulation on a component fluctuating a frequency of the operation clock, a level set unit setting an amplitude of the pulse signal, an adder adding a voltage generated by the feedback control unit and the pulse signal whose amplitude is set by the level set unit, and a low pass filter filtering a signal outputted from the adder and generating a control voltage applied to the voltage-controlled oscillator. The feedback control unit compares a phase of the operation clock with a phase of a reference clock, and based on results of the comparison, generates a voltage used as a reference to oscillate the voltage-controlled oscillator. | 12-16-2010 |
20100315130 | DRIVE CIRCUIT - A drive circuit that outputs low-voltage differential signals to an external load circuit, including: first and second nodes to which the external load circuit is connected; a first series circuit including first and second switching elements, connected in series using the first node as a common node; a second series circuit including third and fourth switching elements, connected in series using the second node as a common node; and a first current source that outputs a predetermined current to the first and second series circuits, in which a back gate of a transistor of a first conductivity type included in at least one of the first and third switching elements or the first current source is forward-biased. | 12-16-2010 |
20100315116 | Testing method for a semiconductor integrated circuit device, semiconductor integrated circuit device and testing system - A method that divides semiconductor integrated circuit devices (corresponding to S | 12-16-2010 |
20100314777 | Semiconductor device and method for manufacturing same - A semiconductor device includes: a semiconductor substrate; an interlayer insulating film provided on the semiconductor substrate; an interconnect (second interconnect trench) composed of a metallic film provided in an interconnect trench (second copper interconnect) and a plug composed of a metallic film provided in a connection hole (via hole) coupled to the second interconnect trench, both of which are provided in the interlayer insulating film; a first sidewall provided on a side surface of the via hole; and a second sidewall provided on a side surface of the second interconnect trench, and a thickness of the first sidewall in vicinity of a bottom of the side surface of the via hole is larger than a thickness of the second sidewall in vicinity of a bottom of the second interconnect trench. | 12-16-2010 |
20100314773 | Semiconductor device - A semiconductor device has: a radiator plate that is maintained at a predetermined potential; an SOI (Silicon On Insulator) chip mounted on the radiator plate; and thermal grease applied to an interface between the radiator plate and the SOI chip. The SOI chip has: a first silicon substrate forming a circuit element part; a second silicon substrate facing the radiator plate; and an insulating film formed between the first silicon substrate and the second silicon substrate. The first silicon substrate and the second silicon substrate are electrically connected to each other. The thermal grease is conductive and electrically connects the second silicon substrate and the radiator plate. | 12-16-2010 |
20100314749 | SEMICONDUCTOR DEVICE HAVING A SEALING RESIN AND METHOD OF MANUFACTURING THE SAME - The semiconductor device | 12-16-2010 |
20100314727 | Semiconductor device - A semiconductor device having a digital region and an analog region embedded therein has an annular seal ring which surrounds the outer circumference of the digital region and the analog region in a plan view; a guard ring which is provided in the area surrounded by the seal ring, between the digital region and the analog region, so as to isolate the analog region from the digital region, and so as to be electrically connected to the seal ring; and an electrode pad which is electrically connected to the guard ring in the vicinity of the guard ring. | 12-16-2010 |
20100312978 | COMPUTER SYSTEM, INFORMATION PROTECTION METHOD, AND PROGRAM - A computer system increases the confidentiality of a memory to be protected and prevents invalid access that is made, for example, by replacing the memory. The computer system includes a memory in which state information AA, which indicates whether or not information to be protected is stored in a predetermined memory area, and access permission information BB, which indicates whether or not access to the memory area is permitted, are stored; and an access control unit that rewrites the state information AA when information to be protected is written to, or deleted from, the memory area and at the same time, when the system is started, rewrites the access permission information BB to permit access to the memory area if information to be protected is not written in the memory area but, otherwise, rewrites the access permission information BB to the access inhibition state. | 12-09-2010 |
20100312940 | DMA TRANSFER CONTROL DEVICE - A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed. | 12-09-2010 |
20100312924 | Network processor, reception controller and data reception processing method performing direct memory access transfer - A network processor is connected to an external memory which includes storage areas for storing received data, and stores descriptors specifying locations of the storage areas, respectively. The network processor includes a descriptor storage circuit for storing a plurality of descriptors out of the descriptors; a DMA control circuit configured to transfer the plurality of descriptors from the external memory to the descriptor storage circuit through DMA transfer, transfer the received data to the storage areas in the external memory through DMA transfer on a basis of the plurality of descriptors stored in the descriptor storage circuit upon receipt of the received data, and generate a reception status indicating a condition of the received data each time the received data is transferred to the external memory through DMA transfer, a reception status storage circuit for storing the reception status; and a reception status combination control circuit for combining the reception statuses which are stored in the reception status storage circuit. The DMA control circuit transfers the combined reception statuses to the external memory through DMA transfer. | 12-09-2010 |
20100308893 | Semiconductor device and method of operating the same - A semiconductor device includes: a high VT part including a first transistor with first threshold voltage; a low VT part including a second transistor with second threshold voltage lower than the first voltage; a temperature detector which measures a temperature of the semiconductor device, determines whether the temperature is in a high temperature state where the temperature is higher than a predetermined temperature or a low temperature state where the temperature is lower than the predetermined temperature, and outputs a signal indicating the high temperature state or the low temperature state; and a controller which receives the signal indicating the high temperature state or the signal indicating the low temperature state, and performs control to cause the high VT part to operate based on the signal indicating the high temperature state and to cause the low VT part to operate based on the signal indicating the low temperature state. | 12-09-2010 |
20100308888 | Driver circuit - A driver circuit including a pre-driver B | 12-09-2010 |
20100308874 | CLOCK SWITCH CIRCUIT AND CLOCK SWITCH METHOD OF THE SAME - A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values. | 12-09-2010 |
20100308867 | SEMICONDUCTOR DEVICE AND ABNORMALITY PREDICTION METHOD THEREOF - A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error. | 12-09-2010 |
20100308667 | ARRANGEMENT OF POWER SUPPLY CELLS WITHIN CELL-BASE INTEGRATED CIRCUIT - A semiconductor device is provided with a first power supply cell, first cells and second cells. The first power supply cell and the first cells are continuously arrayed in a row direction in a first row. The second cells are continuously arrayed in the row direction in a second row adjacent to the first row. The first power supply cell is connected to a first power supply line extending perpendicularly to the row direction to feed a power supply voltage corresponding to a voltage fed from the first power supply line to the plurality of first and second cells. One of the second cells is indirectly connected to the first power supply line through the first power supply cell, the one of the second cells being positioned adjacent to the first power supply cell. | 12-09-2010 |
20100308457 | Semiconductor apparatus and manufacturing method of the same - Provided is a semiconductor apparatus that reduces on-resistance in wiring between a first electrode terminal and a second electrode terminal. The semiconductor apparatus includes the first electrode terminal, the second electrode terminal, and at least two wires that connect the first and second electrode terminals. At least two wires are electrically connected with each other by using a conductive adhesive in an extending direction of the wires. The first electrode terminal is a terminal of an external lead electrode, for example. The second electrode terminal is a terminal of a source electrode of a MOSFET, for example. | 12-09-2010 |
20100308392 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A control gate of a nonvolatile semiconductor storage device includes a first side surface on a side near a floating gate, a second side surface opposite to the first side surface, a silicide region formed in an upper portion of the control gate above the first side surface, and a protruding portion formed in an upper portion of the control gate above the second side surface. A side wall insulating film of the nonvolatile semiconductor storage device includes a first portion which covers at least a portion of the protruding portion without covering the silicide region, and a second portion which is provided continuously from the first portion and covers the second side surface with contacting the second side surface. | 12-09-2010 |
20100308387 | Solid state imaging device - A solid state imaging device having a light receiving region on a first surface side of a semiconductor substrate, incident light from an object to be imaged being illuminated on a second surface side of the semiconductor substrate, the solid state imaging device including an impurity diffusion layer formed on the first surface side of the semiconductor substrate, a surface of the impurity diffusion layer being silicided, and a gate electrode formed on the first surface side of the semiconductor substrate. The impurity diffusion layer includes the light receiving region disposed on the first surface side of the semiconductor substrate, a surface of the light receiving region being silicided, and the impurity diffusion layer includes at least a surface adjacent to the gate electrode. | 12-09-2010 |
20100306727 | Method and design system for semiconductor integrated circuit - A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other. | 12-02-2010 |
20100306602 | SEMICONDUCTOR DEVICE AND ABNORMALITY DETECTING METHOD - A semiconductor device comprises: a task state storage configured to store an executing state of a processing task of software executed by a CPU and to output an executing state signal to show the executing state of the processing task; a task validity judging section configured to acquire an interruption signal corresponding to the processing task based on a control of the CPU and the execution state signal, and to output a valid signal when the processing task is executed validly; a clear signal output section configured to output a clear signal in response to the valid signal; and a watchdog timer configured to clear a timer count value when the clear signal is acquired within a prescribed time and to output a reset signal when the clear signal is not acquired within the prescribed time. | 12-02-2010 |
20100304508 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions. | 12-02-2010 |
20100303179 | SYNCHRONIZATION TIMING DETECTING APPARATUS, RECEIVING APPARATUS, AND SYNCHRONIZATION TIMING DETECTING METHOD - A synchronization timing detecting apparatus includes a correlation calculator configured to generate a first correlation value by calculating a cross-correlation between an input signal being sampled and a reference signal or an auto-correlation of the sampled input signal, an interpolation processor configured to generate a second correlation value interpolating a plurality of the first correlation values having a different combination of sampling points of the input signal, and a detector to detect a synchronization timing based on the first and the second correlation values. | 12-02-2010 |
20100303143 | SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD - Provided is a signal processing apparatus including: an equalizer circuit that amplifies a predetermined frequency band of an input signal and outputs an output signal; a sampler circuit that samples the output signal amplified by the equalizer circuit with the output signal being offset in an amplitude direction using a multiphase clock system; an area information calculation circuit that calculates area information of an eye opening in an eye diagram of the output signal based on the output signal sampled by the sampler circuit; and a control circuit that controls amplification of the equalizer circuit based on the area information of the eye opening calculated by the area information calculation circuit. | 12-02-2010 |
20100302699 | ELECTRICAL FUSE CIRCUIT AND METHOD OF OPERATING THE SAME - An electrical fuse circuit is provided with: a protection element having a first terminal connected to a power source and outputting a fusing voltage from a second terminal; an electrical fuse having a third terminal connected to the second terminal of the protection circuit; and a fusing transistor connected between the electrical fuse and ground to switch a current through the electrical fuse. The second terminal of the protection element is connected to a gate of the fusing transistor. | 12-02-2010 |
20100302694 | Electrostatic discharge protection circuit - It is desired to achieve a high ESD protection performance by a small area circuit. An electrostatic discharge protection circuit includes: protection circuits, wherein each protection circuit includes a MOS transistor; and a trigger circuit configured to supply a trigger signal to a gate electrode of the MOS transistor of each protection circuit in response to a surge voltage between a low potential node and a high potential node. Each protection circuit is configured to electrically connect the low potential node and the high potential node to one another when the trigger signal is supplied to the gate electrode. The gate electrode of each protection circuit is connected to a resistive element having larger resistance value than Rmax, supposing that Rmax is a largest parasitic resistance between each of the plurality of protection circuit and an output of the trigger circuit. | 12-02-2010 |
20100302543 | METHOD OF MANUFACTURING OPTICAL RECEIVER MODULE AND APPARATUS FOR MANUFACTURING THE SAME - The core adjusting process includes a procedure of searching for the position in which the photocurrent of the light-receiving element reaches its peak in each of the X-, Y-, and Z-directions. In the searching procedure, the light emitted from a multimode fiber of a MCP is gathered by a lens and is transmitted to the light-receiving element. A check is then made to determine whether, at in both directions of the search direction, there exist a first and second attenuation positions in which the photocurrent shows a predetermined attenuation relative to a peak value in a search range. If there exist the attenuation positions, a peak position is determined to be a position located within a second predetermined range from the middle point between the attenuation positions, and the relative positions of the receptacle and the CAN package are adjusted to the peak position. | 12-02-2010 |
20100301956 | VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator includes a resonator section in which a plurality of types of variable capacitance elements having different structures and capacitance variation characteristics are connected in parallel and capacitance values of the plurality of types of variable capacitance elements are controlled simultaneously by a control voltage; and an amplifier section for maintaining oscillation produced by the resonator section. Varactor diodes and MOS varactors can be used as the variable capacitance elements. | 12-02-2010 |
20100301927 | BOOSTER CIRCUIT - Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage. | 12-02-2010 |
20100301916 | CLOCK DISTRIBUTION CIRCUIT AND LAYOUT DESIGN METHOD USING SAME - A layout design method in accordance with an exemplary aspect of the present invention is a layout design method for a clock tree circuit, including disposing a first clock distribution circuit in a clock tree circuit, wiring the clock tree circuit in which the first clock distribution circuit is disposed, verifying timing of the wired clock tree circuit, and replacing the first distribution element by a second clock distribution circuit based on a result of the timing verification, the second clock distribution circuit having roughly a same input load capacitance as the first clock distribution circuit and a different delay value from the first clock distribution circuit. | 12-02-2010 |
20100301910 | Frequency synthesizer - A frequency synthesizer comprises a VCO group; a phase comparator; and a loop filter. Each VCO includes a varactor and a capacitor bank including a plurality of weighted capacitance elements, and a plurality of switches turned ON and OFF based on a control signal. Also provided a temperature compensation including a varactor correction potential generation circuit, a correction potential generation circuit for parasitic capacitance of the capacitor bank, a variable gain amplifier in which weighting processing, based on a control signal of the capacitor bank, is performed on an output potential of the correction potential generation circuit, and an adder circuit that adds the output voltage of the correction potential generation circuit of the varactor and output voltage of the variable gain amplifier, and the varactor of the VCO is controlled by output (correction potential) of the adder circuit. | 12-02-2010 |
20100301905 | Output circuit having pre-emphasis function - An output circuit includes a first differential pair of transistors driven by a first current source and differentially receiving input signals and a second differential pair of transistors driven by a second current source and differentially receiving first control signals (EMT, EMB). Output pairs of the first and second differential pairs are connected to the differential output terminals. A load resistor element pair is connected between a power supply and the differential output terminals. The output circuit further includes a third differential pair of transistors driven by a third current source and differentially receiving second control signals and a fourth differential pair of transistors driven by a fourth current source and differentially receiving third control signals. An output pair of the third differential pair of transistors is connected between one of the differential output terminals and the power supply. An output pair of the fourth differential pair of transistors is connected between the power supply and the other of the differential output terminals. | 12-02-2010 |
20100301895 | Test system and test method of semiconductor integrated circuit - Provided is a test system of a semiconductor integrated circuit including an output device and an input device for conducting an input/output characteristics test of the output device and the input device inside the semiconductor integrated circuit. In the system, a transmission line provided in a test board where the semiconductor integrated circuit is mounted on establishes a wired connection between an external terminal of one circuit of one of the output device and the input device and external terminals of a plurality of circuits of another one of the output device and the input device. | 12-02-2010 |
20100301495 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided is the method for manufacturing the semiconductor device including: providing a film (organic silicon polymer film) containing a silane compound and a porogen on a substrate; providing a hole (interconnect trench) in the organic silicon polymer film using a selective etching process and providing a metallic film (barrier film and copper interconnect) in the inside of the interconnect trench; and conducting a radiation with ultraviolet over the organic silicon polymer film within an atmosphere of a reducing gas while the film is heated at a temperature of not lower than a boiling point or a decomposition temperature of the porogen to obtain a microporous film. | 12-02-2010 |
20100301488 | Semiconductor device - In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure. | 12-02-2010 |
20100301451 | Semiconductor device, lower layer wiring designing device, method of designing lower layer wiring and computer program - A semiconductor device includes a lower layer wiring layer, an MIM capacitors and an upper layer wiring layer. The lower layer wiring layer includes a plurality of lower layer wirings. The MIM capacitor is formed above the lower layer wiring layer. The MIM capacitor includes a lower electrode, a capacity dielectric film and an upper electrode which are layered from underneath in this order. A planar form of the upper electrode is smaller than that of the lower electrode. The upper layer wiring layer includes a plurality of upper layer wirings which are connected to the lower electrode and the upper electrode through via plugs. A plane of the upper electrode is made rectangular. The lower layer wirings are not arranged right below one or more than one edge of the plane of the upper electrode. | 12-02-2010 |
20100301440 | Mesa photodiode and method for manufacturing the same - A mesa photodiode which includes a mesa, the sidewall of the mesa is a surface that is inclined in the direction in which the bottom of the mesa becomes wider. At least the sidewall of the mesa is covered with a semiconductor layer of a first conductivity type, a second conductivity type, a semi-insulating type, or an undoped type. The semiconductor layer is grown on at least the sidewall of the mesa. The inclined angle of the inclined surface of the mesa at the upper end portion is smaller than the inclined angle of the inclined surface of the mesa at the lower end portion. | 12-02-2010 |
20100299470 | INTERRUPT PROCESSING APPARATUS AND METHOD - An interrupt processing apparatus stores an elapsed detection time and an interrupt occurrence count for each interruption cause. The interrupt processing apparatus stores an interval of trouble determination for each interruption cause, and determines whether the elapsed detection time for each interruption cause reaches the interval of trouble determination. If the interrupt occurrence count exceeds the threshold value when the trouble determination interval is reached, the trouble state is determined. | 11-25-2010 |
20100297811 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing according to an embodiment of the present invention includes forming a seed metal layer | 11-25-2010 |
20100296622 | Counter circuit - A counter circuit adding a first value indicated by a plurality of bits and a second value in response to a clock signal, a first part of the plurality of bits being lower order than a second part of the plurality of bits, the counter circuit including a first counter configured to add the first part of the plurality of bits and the second value in response to the clock signal to output a third value regarding a result of adding the first and the second values, a second counter configured to add the second part of the plurality of bits and a fourth value in response to the clock signal, and a clock transmission control circuit coupled to the first and second counters to receive the clock signal and the third value, and to control whether or not to supply the clock signal to the second counter in accordance with the received third value. | 11-25-2010 |
20100296069 | Pattern division method, pattern division processing apparatus and information storage medium on which is stored a program - There is provided a pattern division method to form crowded patterns accurately on a substrate includes acquiring a mask pattern, dividing a predetermine area into a plurality of areas to prepare a division pattern in which the plurality of the areas are classified into first and second groups, generating a reduced mask pattern by reducing each of two or more patterns laid out in the object mask pattern substantially toward the center of the particular pattern, overlapping the division pattern with the reduced mask pattern and extracting the reduced patterns overlapped with the area classified as the first group of the division pattern to generate a first reduced mask pattern, and restoring the reduced patterns laid out in the first reduced mask pattern to the original size before generation of the reduced mask pattern. | 11-25-2010 |
20100295625 | Variable inductor - A variable inductor includes: a first inductor having two ends connected to a first terminal and a second terminal; a second inductor having two ends connected to the first terminal and the second terminal; a first node provided on the first inductor; a second node provided on the second inductor; and a switch element that switches between a conductive state and a non-conductive state between the first node and the second node. | 11-25-2010 |
20100295596 | LEVEL SHIFT CIRCUIT - A level shift circuit insusceptible to mistaken operations at the time of disengagement of a standby state is disclosed. The level shift circuit includes a level converter circuit | 11-25-2010 |
20100295584 | PLL CIRCUIT AND OPTICAL DISC APPARATUS - A PLL circuit includes a polyphase reference clock output circuit that outputs reference clocks, a polyphase frequency divider circuit that outputs divided clocks, which is obtained by dividing frequencies of the reference clocks, a selection switch circuit that selects one of the reference clocks or one of the divided clocks, and outputs the selected clock as a selected clock, a digital VCO that uses the selected clock as an operating clock, and outputs delay amount data indicating a phase difference between an output clock and an ideal phase, where the output clock has a frequency that fluctuates according to a value of frequency control input data, and the ideal phase is calculated according to the output clock and the value of the frequency control input data, and a selection circuit that selects and outputs the output clock synchronized with the divided clocks according to the delay amount data. | 11-25-2010 |
20100295530 | Power supply voltage control circuit - A power supply voltage control circuit controls power supply voltage supplied to a target circuit that performs certain signal processing. The power supply voltage control circuit includes a control signal generation circuit that selectively generates first and second control signals when the power supply voltage supplied to the target circuit is increased from a first power supply voltage to a second power supply voltage, the second power supply voltage being higher than the first power supply voltage, and a power supply circuit that increases the power supply voltage toward a voltage level of the second power supply voltage based on the first control signal, or increases the power supply voltage to a voltage level higher than the second power supply voltage first and subsequently decreases the power supply voltage to the second power supply voltage based on the second control signal. | 11-25-2010 |
20100295097 | FIELD-EFFECT TRANSISTOR - A field-effect transistor according to the present invention includes a silicon substrate that has a resistivity of not more than 0.02 Ω•cm, a channel layer that is formed on the silicon substrate and has a thickness of at least 5 μm, a barrier layer that is formed on the channel layer and supplies the channel layer with electrons, a two dimensional electron gas layer that is formed by a hetero junction between the channel layer and the barrier layer, a source electrode and a drain electrode that each form an ohmic contact with the barrier layer, and a gate electrode that is formed between the source electrode and the drain electrode, and forms a Schottky barrier junction with the barrier layer. | 11-25-2010 |
20100291732 | Manufacturing method for electronic devices - A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part. | 11-18-2010 |
20100289684 | ANALOG-DIGITAL CONVERTER CIRCUIT AND ANALOG-DIGITAL CONVERSION METHOD - Provided is an analog-digital converter circuit including: a comparison unit that sequentially compares an analog input voltage with reference voltages, which sequentially vary, and outputs a comparison result as a digital value; a standard voltage generation unit that generates a standard voltage for correcting the reference voltages; a storage unit that stores a comparison result of the standard voltage obtained by the comparison unit; and a reference voltage generation unit that generates the reference voltages based on the comparison result of the standard voltage. | 11-18-2010 |
20100289526 | Level shifter - A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level. Each of the first and second level shift circuits includes a first conductivity type transistor having its gate receiving the first and second pulse signals respectively, its source connected to a ground, and its drain outputs a level shifted pulse signal, and a first transistor of a second conductivity type having its gate connected to the gate of the transistor of the first conductivity type, its drain connected to the drain of the transistor of the first conductivity type, and its source connected to the power supply via a connected transistor group, and the connected transistor group includes at least one of the second conductivity type transistors. | 11-18-2010 |
20100289521 | TERMINATION RESISTANCE ADJUSTING CIRCUIT - A termination resistance adjusting circuit includes a first termination resistor circuit, a second termination resistor circuit connected in parallel with the first termination resistor circuit, a resistor circuit for adjustment that adjusts resistances of the first and second termination resistor circuits, a first amplifier circuit that receives a first voltage determined by the resistor circuit for adjustment and a second voltage determined by a reference resistor connected externally, equalizes the first and second voltages, and outputs a resistance adjusting signal to the first and second termination resistor circuits, first and second terminals connected to the first and second termination resistor circuits respectively, and a second amplifier circuit that receives a voltage based on a common voltage of a differential signal supplied to the first and second terminals, and the first or second voltage, and equalizes the voltage based on the common voltage and the first or second voltage. | 11-18-2010 |
20100289150 | Semiconductor device, designing method for semiconductor device, computer-readable medium, and manufacturing method for semiconductor device - A designing method for a semiconductor device includes: determining a placement of metal wirings to be connected to contact holes and a placement of through-holes for preparing the contact holes. The determining step includes: specifying areas in one of the metal wirings to be exposed by the through-holes, specifying a capacitance of the metal wirings, and determining the placement of the metal wirings such that damage to the areas is suppressed in a case where electric charges accumulated in the capacitance are transferred from one of the metal wirings to a polar solvent through the areas. | 11-18-2010 |
20100288915 | Method and apparatus for compensating infrared sensor for temperature - To improve the precision of temperature compensation in an infrared sensor and obtain a sharp image, a correction is applied to a variation in output voltage (referred to as “background infrared radiation absorption intensity distribution” below) due to intensity distribution of background infrared radiation, which is light other than the incident infrared radiation on the infrared sensor, and the temperature characteristic of each individual bolometer constituting the infrared sensor. That is, the temperature of the infrared sensor is measured as a first temperature, a correction value for the output voltage of each bolometer is found by referring to a table, which indicates the background infrared radiation absorption intensity distribution versus the temperature of the infrared sensor, as well as the first temperature, and the variation in output voltage is corrected. | 11-18-2010 |
20100287426 | MEMORY CHECKING SYSTEM AND METHOD - A memory checking system according to the present invention includes a memory that stores a data to be checked, a check circuit that checks the memory by using the data to be checked and a reference check code of the data to be checked, and a transfer circuit that transfers the data to be checked from the memory to the check circuit based on a transfer setting information of the data to be checked. The transfer setting information is registered in advance in the memory. | 11-11-2010 |
20100284116 | INPUT OVERVOLTAGE PROTECTION CIRCUIT WITH SOFT-START FUNCTION - An overvoltage protection circuit includes a PMOS transistor Q | 11-11-2010 |
20100283644 | A/D conversion circute and test method - An A/D conversion circuit includes a plurality of transmission paths that transmit signal voltages and reference voltages, and an A/D conversion unit that A/D converts voltages output from the transmission paths. Each of the plurality of transmission paths includes a first switch that selectively outputs one of the signal voltage and the reference voltage, an S/H circuit that holds output voltage from the first switch, and a second switch that selectively outputs one of the output voltage from the first switch and output voltage from the S/H circuit. | 11-11-2010 |
20100283508 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A semiconductor chip includes a plurality of pads, input circuits or output circuits that are electrically connected to the pads, a main control unit that outputs a read access signal, the read access signal controlling reading of signals from an external circuit or an internal circuit, and activation control units that control activation of the input circuits or the output circuits that are electrically connected to the pads based on the read access signal, the pads receiving the signals from the external circuit or the internal circuit. | 11-11-2010 |
20100281198 | Bus relay device and bus control system - A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus to output a second signal group including at least one of signals onto the first bus, an interconnect section coupled between the first bus and a second bus to receive the first and second signal groups and to output a third signal group including at least one of signals onto the second bus, and a bridge section coupled between the second bus and a third bus to receive the third signal group and to output a fourth signal group including at least one of signals onto the third bus free from performing a selecting operation for the third signal group. | 11-04-2010 |
20100277970 | Static random accee memory device - Additional transistors P | 11-04-2010 |
20100276791 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance. | 11-04-2010 |
20100275035 | Cryptographic processing apparatus and method for storage medium - Provided is a cryptographic processing apparatus for a storage medium, including: a location information conversion unit that stores a conversion result in a buffer, the conversion result obtained by performing a conversion process on location information indicating a location of data to be accessed on the storage medium; and a data cryptographic processing unit that performs cryptography processing on the data using the conversion result stored in the buffer, the cryptography processing being one of encryption and decryption. | 10-28-2010 |
20100274995 | PROCESSOR AND METHOD OF CONTROLLING INSTRUCTION ISSUE IN PROCESSOR - One exemplary embodiment includes a processor including a plurality of execution units and an instruction unit. The instruction unit discriminates whether an instruction is a target instruction for which determination about availability of parallel issue based on dependency among instructions is to be made with respect to each instruction contained in an instruction stream. When a first instruction contained in the instruction stream is the target instruction, the instruction unit adjusts the number of instructions to be issued in parallel to the plurality of execution units based on a detection result of dependency among the first instruction and at least one subsequent instruction. Further, when the first instruction is not the target instruction, the instruction unit issues a group of a predetermined fixed number of instructions including the first instruction in parallel to the plurality of execution units unconditionally regardless of a detection result of dependency among the instruction group. | 10-28-2010 |
20100273401 | Polishing apparatus and polishing method - A polishing apparatus includes a polishing table with a polishing pad at an upper surface, and a conditioning disc carrying out conditioning of the polishing pad, and a moving mechanism (constructed, for example, from a swing arm) capable of moving the conditioning disc to a standby position above the polishing pad, and a spraying mechanism (constructed, for example, from a washing water nozzle) that sprays liquid to the conditioning disc positioned at the standby position so as to wash or wet the conditioning disc. | 10-28-2010 |
20100273312 | Method of manufacturing semiconductor device - In a method of manufacturing a semiconductor device, a first groove and a second groove each having a width less than that of a scribe line are formed along the scribe line in a first protective film provided below a second protective film which protects element forming regions when a wafer is divided into parts by a laser dicing, and the first groove and the second groove are filled with the second protective film. Then, the laser dicing is performed on a region between the first groove and the second groove along the scribe line from the surface where the second protective film is formed to form a cutting groove that reaches at least a predetermined depth of the multi-layer interconnect. | 10-28-2010 |
20100272375 | Image processing apparatus and image processing method - An image processing apparatus that performs filter processing of image data includes a filter processing unit that performs filter processing by reflecting a correction value in a pixel value, an adjustment value generation unit that generates a gain value based on display position of a pixel, and a correction value change unit that changes the correction value based on the gain value generated by the adjustment value generation unit. | 10-28-2010 |
20100272142 | Nitride semiconductor optical element and method of manufacturing the same - Provided is a semiconductor laser element having a first protective film provided at least over the light emitting end face of an active layer (3-period multiple quantum well (MQW) active layer); and a second protective film provided over the first protective film, wherein, the first protective film is provided between a semiconductor which composes the light emitting end face and the second protective film, and a portion of the first protective film, brought into direct contact with the semiconductor, is mainly composed of a rutile-structured TiO | 10-28-2010 |
20100271406 | Display driver and method of testing the same - A display driver includes a gradation data register that stores gradation data having a bit width, and a gradation voltage signal generator that generates a gradation voltage signal that has voltage according to the gradation data stored in the gradation data register and outputs the generated gradation voltage signal, the display driver further including a test circuit that is provided between the gradation data register and the gradation voltage signal generator, the test circuit connecting at least a plurality of bit lines among bit lines provided between both of the circuits through a common node in a test mode, so as to perform failure detection based on a value of current that flows in the common node. | 10-28-2010 |
20100271348 | Semiconductor device and data driver of display apparatus using the same - There is provided a decoder in which a matrix of transistors, a plurality of reference voltage signal lines arranged on a first interconnect layer and extended in a row direction, being separated to one another over the matrix, and a plurality of reference voltage signal lines arranged on a second interconnect layer and extended in the row direction, being separated to one another over the matrix. The reference voltage signal lines on the mutually different layers are respectively connected to impurity diffusion layers of the transistors that are adjacent in the row direction. The reference voltage signal lines on the mutually different layers are respectively connected to the impurity diffusion layers of the transistors that are adjacent in a column direction | 10-28-2010 |
20100271249 | INTERPOLATING A/D CONVERTER - Provided is an interpolating A/D converter including a reference voltage generation circuit, an analog signal input circuit, a preamplifier group including a plurality of preamplifiers, and an interpolation circuit including a plurality of resistors. Reference voltages from the reference voltage generation circuit and an analog signal from the analog signal input circuit are input to the preamplifier group. The interpolation circuit outputs an interpolation signal by interpolating output signals of the preamplifier group. The preamplifiers amplify a differential voltage when a differential voltage between the analog signal and the reference voltages is smaller than a specified value, and the current flow of which is stopped when it is larger than the specified value. The plurality of resistors are connected in series between the adjacent amplifiers. | 10-28-2010 |
20100271132 | Amplifier circuit with resistive current limitter - An amplifier circuit includes first transistor of first conductivity type having source connected to first power supply, while having gate connected to input terminal and drain connected to output terminal; transistor of second conductivity type having source connected to second power supply and drain connected to the output terminal; second transistor of the first conductivity type whose source and gate are connected to the source and gate of the first transistor of the first conductivity type, respectively; resistor whose one end connected to drain of the second transistor of the first conductivity type, and an output control circuit; current input terminal connected to the opposite end of the resistor; and voltage output terminal connected to the gate of the transistor of the second conductivity type. The output control circuit controls the gate voltage of the transistor of the second conductivity type based on the input current of the current input terminal. | 10-28-2010 |
20100271102 | Semiconductor integrated circuit - Provided is a semiconductor integrated circuit including: a differential driver that is, disposed between a first power supply and a second power supply and drives differential input signals to generate differential output signals; and a control signal generation circuit that generates a first control signal for controlling a voltage level of each of the differential output signals. When each of a pair of output signals forming the differential output signals is changed from a voltage level corresponding to the first power supply to a voltage level corresponding to the second power supply, an amount of change in the voltage level of the corresponding output signal is controlled based on the first power supply. | 10-28-2010 |
20100271083 | FLIP-FLOP CIRCUIT AND PRESCALER CIRCUIT INCLUDING THE SAME - A prescaler circuit according to an exemplary aspect of the present invention includes a first flip-flop circuit that detects second output data and outputs the detected data as first output data, and a second flip-flop circuit that detects the first output data and outputs the data as the second output data. The first flip-flop circuit includes a master-side latch circuit that generates intermediate data, a slave-side latch circuit that detects the intermediate data and outputs the data as the first output data, and a control signal switching circuit that selects and outputs the first output data as a control signal in a mode where the frequency is divided by 3, and selects and outputs a predefined fixed signal as a control signal in a mode where the frequency is divided by 4. The master-side latch circuit generates the intermediate data based on the second output data and the control signal. | 10-28-2010 |
20100271077 | LIGHT RECEIVING CIRCUIT - A light receiving circuit in accordance with an exemplary aspect of the present invention includes a photodiode | 10-28-2010 |
20100271065 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MEASURING SYSTEM - A semiconductor device includes: a well of a second conductive type formed on or above a semiconductor substrate of a first conductive type; a first diffusion layer of the second conductive type formed in a surface portion of the well; a second diffusion layer of the first conductive type formed separately from the first diffusion layer in the surface portion of the well; first to third first-layer conductive layers formed above the well; and first to third second-layer conductive layers formed above the first to third first-layer conductive layers. The first second-layer conductive layer, the first first-layer conductive layer, the first diffusion layer and the well are conductively connected as a first conductive path. The second second-layer conductive layer, the second first-layer conductive layer, and the second diffusion layer are conductively connected as a second conductive path. The third second-layer conductive layer, and the third first-layer conductive layer are conductively connected as a third conductive path. | 10-28-2010 |
20100270687 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - One aspect of the present invention is a semiconductor device including: a semiconductor substrate; a first wiring that is formed on the semiconductor substrate; a second wiring that is formed to cross over the first wiring with a space interposed therebetween at a cross portion in which the first wiring and the second wiring cross each other; a protective film that is formed on the semiconductor substrate to cover at least a part of the first wiring, the part being located under the second wiring in the cross portion; and an insulator film that is formed in an island shape on the protective film under the second wiring in the cross portion to be located between edges of the protective film and to cover the first wiring in the cross portion. | 10-28-2010 |
20100270683 | Semiconductor device and method of manufacturing semiconductor device - An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect. | 10-28-2010 |
20100270677 | Semiconductor device and method of manufacturing semiconductor device - An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. A second insulating layer is formed at least over the first insulating layer and the air gap. The second insulating layer does not cover the interconnect. An etching stopper film is formed at least over the second insulating layer. The etching stopper film is formed over the second insulating layer and the interconnect. A third insulating layer is formed over the etching stopper film. A via is provided in the third insulating layer so as to be connected to the interconnect. | 10-28-2010 |
20100270672 | Semiconductor device - A semiconductor device includes a conductive section formed on a semiconductor chip; and a bump electrode formed directly or indirectly on the conductive section. The conductive section includes a slit section having a thickness thinner than another portion of the conductive section. The bump electrode has a recessed section corresponds to the slit section above the slit section. | 10-28-2010 |
20100270643 | Semiconductor device and layout method therefor - Provided is a semiconductor device including: an MIM capacitor that includes a lower electrode, an upper electrode, and a capacitor insulating film formed between the lower electrode and the upper electrode; a first via hole that connects to the lower electrode and extends in a normal upward direction of a principal surface of the lower electrode; a second via hole that connects to the upper electrode and extends in a normal upward direction of a principal surface of the upper electrode; and a plurality of lower wiring lines that are formed under the lower electrode, in which formation areas of the first and second via holes overlap formation areas of the plurality of lower wiring lines when viewed in the normal direction of the principal surface of the upper electrode. | 10-28-2010 |
20100270642 | Semiconductor device - A first inductor is connected to a transmission circuit. A second inductor is connected to a reception circuit, and is inductively coupled to the first inductor. At least part of the first inductor is formed with a first bonding wire. The first bonding wire has two ends connected to a first connecting terminal and a third connecting terminal. At least part of the second inductor is formed with a second bonding wire. The second bonding wire has two ends connected to a second connecting terminal and a fourth connecting terminal. | 10-28-2010 |
20100270621 | Semiconductor device and method of manufacturing the semiconductor device - A semiconductor device includes: a FinFET (Fin Field Effect Transistor); and a PlanarFET (Planar Field Effect Transistor). The FinFET is provided on a chip. The PlanarFET is provided on the chip. A second gate insulating layer of the PlanarFET is thicker than a first gate insulating layer of the FinFET. | 10-28-2010 |
20100270613 | Method for manufacturing semiconductor device, and semiconductor device - In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench. | 10-28-2010 |
20100267211 | Method of manufacturing semiconductor apparatus - A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance. | 10-21-2010 |
20100266292 | LIGHT RECEIVING CIRCUIT AND PHOTOCOUPLER ISOLATION CIRCUIT - A light receiving circuit includes: a light receiving element that receives an optical signal and converts into an electrical signal; a comparator that demodulates the information on the optical signal to a pulsed signal; a band limit circuit disposed between the light receiving element and the comparator, the band limit circuit removing noise components of frequency higher than the pulsed signal; and a comparator threshold circuit disposed between the light receiving element and the comparator, the comparator threshold circuit generating a threshold of the comparator and limiting the threshold of the comparator within a binary range. | 10-21-2010 |
20100266241 | OPTICAL TRANSMITTER AND METHOD OF MANUFACTURING THE SAME - Provided is an optical transmitter including, a substrate (silicon optical bench), a light emitting element, and a temperature sensing element; wherein, two recesses are formed in a surficial portion of the silicon optical bench; the light emitting element is provided inside one recess; and the temperature sensing element is provided inside the other recess. | 10-21-2010 |
20100266221 | DIFFERENCE IMAGE GENERATION DEVICE, DIFFERENCE IMAGE GENERATION METHOD, AND COMPUTER READABLE MEDIA - One exemplary embodiment includes a difference image generation device including a measurement unit and a scaling unit. The measurement unit measures a variation width of pixel values of a difference image signal obtained by performing subtraction processing on first and second input image signals. The scaling unit scales each pixel value of the difference image signal based on a measurement result of the variation width so that the difference image signal can be represented in grayscale using a predetermined bit width, and outputs a difference image signal subjected to scaling. | 10-21-2010 |
20100265376 | SEMICONDUCTOR IMAGE DEVICE - A line sensor includes a second conductive type semiconductor substrate where a first conductive type well region is formed, a pixel line formed in the well region, a plurality of pixels being formed on the well region, the plurality of pixels generating charges corresponding to an incident light, a CCD register unit formed on the well region, a transfer electrode being arranged on the well region, the transfer electrode transferring the charges in response to a transfer clock, an output circuit which outputs a voltage signal corresponding to the charges transferred by the transfer electrode, a wiring part which supplies a reference potential to the well region and the output circuit, and a resistor which is included in a wiring, the wiring connecting a first contact between the well region and the wiring part to a second contact between the output circuit and the wiring part. | 10-21-2010 |
20100265273 | Operational amplifier, driver and display - An operational amplifier includes an input differential stage having one external input receiving an external input voltage and two outputs; and two output stages. A switch section is provided between inputs of the two output stages and the two outputs of the input differential stage, and is configured to alternately connect the two outputs of the input differential stage and inputs of a positive-only output stage of the two output stages; and the two outputs of the input differential stage and inputs of a negative-only output stage of the two output stages. | 10-21-2010 |
20100265241 | Display apparatus using power supply circuit - A power supply circuit for a display apparatus, includes: a voltage boosting circuit configured to boost up an input voltage based on a voltage boosting factor to output a boosted output voltage; a voltage detecting circuit configured to compare a voltage level of a power supply voltage to which the input voltage is related and a predetermined voltage level; and a control circuit configured to output one of a first voltage boosting factor and a second voltage boosting factor as the voltage boosting factor to the voltage boosting circuit based on the comparison result. The control circuit changes the voltage boosting factor during a blanking period in a display panel. | 10-21-2010 |
20100265234 | Driver and display apparatus using the same - A driver includes a gradation voltage supplying section configured to supply a first output gradation voltage to a data line in a first display period; and a charge share performing section configured to supply a second voltage between the first output gradation voltage and a first voltage to the data line in a charge share period after the first display period. The first voltage is a common voltage between the first output gradation voltage and a second output gradation voltage of a polarity opposite to that of the first output gradation voltage. | 10-21-2010 |
20100265024 | SEMICONDUCTOR DEVICE - In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls. | 10-21-2010 |
20100264964 | Pll circuit - There is provided a PLL circuit including a first loop filter and a second loop filter, which includes a current signal generation circuit that includes a first output driver that generates a first current signal to be output to the first loop filter and a second output driver that generates a second current signal to be output to the second loop filter, and a control circuit that selects which of the first output driver and the second output driver is to be activated. | 10-21-2010 |
20100264943 | Resistance variation detection circuit, semiconductor device and resistance variation detection method - A circuit for detecting variation of a resistance value of a resistor with respect to a reference value includes a first resistor; a second resistor; a first current source circuit for supplying current to the first resistor; a second current source circuit for supplying current to the second resistor; a voltage comparator circuit for comparing a voltage across the first resistor and a voltage across the second resistor; and a control circuit for digitally adjusting the supply current of at least one of the first or second current source circuit. A ratio of resistance values of the first and second resistors can be obtained from an adjustment value from the control circuit and result of comparison from the voltage comparator circuit. | 10-21-2010 |
20100264896 | Voltage regulator circuit - It is desired for semiconductor devices to reduce an inrush current and an overshoot. According to the voltage regulator circuit of the present invention, when a power supply is turned on, a switch SW | 10-21-2010 |
20100264892 | Power supply control device and power supply control method - Control accuracy with regard to variation of output voltage is improved. A direct current converter unit ( | 10-21-2010 |
20100264515 | Semiconductor device - An interconnect substrate is placed over a first inductor of a semiconductor chip and a second inductor of another semiconductor chip. The interconnect substrate includes a third inductor and a fourth inductor. The third inductor is located above the first inductor. The distance from the first inductor to the third inductor is longer than the distance from the second inductor to the fourth inductor. | 10-21-2010 |
20100264483 | SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor storage device and method of manufacturing same at a lower cost by without forming a photolithographic resist. Second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together. A select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction. | 10-21-2010 |
20100262302 | Plasma processing apparatus, fault detection apparatus, and fault detection method - Gas introduction piping introduces process gas for plasma generation into a processing chamber. A pressure regulating valve is provided at an exhaust pipe. A mass flow controller is provided at the gas introduction piping and regulates the flow rate of the process gas. A pressure gauge detects the pressure of the processing chamber. A control unit controls pressure within the processing chamber by controlling an extent of opening of the pressure regulating valve based on values detected by the pressure gauge. The control unit receives flow rate data indicating the rate of flow of process gas from the mass flow controller and determines the presence or absence of faults at the mass flow controller based on an extent of fluctuation of the values detected by the pressure gauge when a high-frequency is inputted to the electrode. | 10-14-2010 |
20100259984 | ERASE METHOD OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - An erase method of a nonvolatile semiconductor memory device including a semiconductor substrate with diffusion regions spaced from each other, a first insulating layer formed on the semiconductor substrate, a first gate electrode formed in a first area on the first insulating layer, a charge accumulation layer formed in a second area on the first insulating layer, a second insulating layer formed on the charge accumulation layer and a second gate electrode formed on the second insulating layer includes a step of injecting hot holes into the charge accumulation layer from the diffusion region and a step of injecting channel hot electrons into a part of the charge accumulation layer close to the first gate electrode side. | 10-14-2010 |
20100259860 | Overvoltage protection circuit - An overvoltage protection circuit includes an output transistor coupled between a power supply and an output terminal, the output terminal including a terminal for being coupled to a load and a dynamic clamping circuit and a clamp selection transistor coupled in series between the power supply terminal and a control terminal of the output transistor. The clamp selection transistor is coupled between the dynamic clamping circuit and a control terminal of the output transistor. In addition, the clamp selector transistor includes an N-channel type transistor, a control terminal of the N-channel type transistor being coupled to a ground potential. | 10-14-2010 |
20100259320 | Semiconductor device capable of switching operation modes - A semiconductor device includes a substrate, a first internal terminal, a second internal terminal, a third internal terminal, and a fourth internal terminal which are placed along perimeter of the substrate, a circuit formed above the substrate and coupled to the first internal terminal, a first external terminal coupled to the second internal terminal, a second external terminal coupled to the third internal terminal, and a third external terminal coupled to the fourth internal terminal and placed beside one side of the substrate where the second external terminal is located, wherein the circuit generates a signal indicative of a connection state between the first internal terminal and the first external terminal, and wherein the first internal terminal and the second internal terminal are arranged to form two rows in a direction perpendicular to one side of the substrate beside which the first external terminal is placed. | 10-14-2010 |
20100258955 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a substrate over one surface of which an electroless plating electrode film is formed; a semiconductor chip mounted over the one surface of the substrate; and a bonding wire which connects the semiconductor chip and one surface of the electroless plating electrode film, a recessed depth which is a difference between a lowermost height of a bonding portion of the one surface of the electroless plating electrode film to the bonding wire, and an uppermost height of the one surface other than the bonding portion being equal to or less than 1.5 μm. | 10-14-2010 |
20100258953 | SUBSTRATE AND SEMICONDUCTOR DEVICE - A substrate has a plurality of pads formed over one surface of a base, and an insulating film which is formed thereon and has a plurality of openings formed therein so as to expose each of the pads, wherein the openings of the insulating film are formed so that, in each pad formed at the corner of the base, among the plurality of pads, a first peripheral portion which composes a portion of the pad more closer to the corner and more distant away from the center of the base is covered by the insulating film, and so that a second peripheral portion which composes a portion of the pad more closer to the center as compared with the first peripheral portion is exposed in the opening. | 10-14-2010 |
20100258918 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MODULE EMPLOYING THEREOF - A semiconductor device is provided with a silicon substrate and a structure filled in a through hole that has a rectangular cross section and extends through the silicon substrate. The structure comprises a pipe-shaped through electrode, stripe-shaped through electrodes, silicons, a first insulating film, a second insulating film and a third insulating film. The pipe-shaped through electrode is utilized as a pipe-shaped electric conductor that extends through the silicon substrate. In addition, the stripe-shaped through electrodes are provided in the interior of the pipe-shaped through electrode so that the stripe-shaped through electrodes extend through the silicon substrate and is spaced away from the pipe-shaped through electrode. A plurality of through electrodes are provided in substantially parallel within the inner region of the pipe-shaped through electrode. | 10-14-2010 |