NEC ELECTRONIC CORPORATION Patent applications |
Patent application number | Title | Published |
20100155833 | Semiconductor device having vertical type MOSFET and manufacturing method thereof - A method (and resultant structure) includes forming a semiconductor layer having plural stripe-like trenches, forming a gate electrode buried partially in each of the plural trenches, and introducing an impurity into the semiconductor layer by ion implantation after forming the gate electrode. The gate electrode has a buried portion formed in each of the trenches and a protruding portion situating above the buried portion and having a width larger than that of the buried portion. The introducing the impurity includes introducing an impurity into the semiconductor layer below the protruding portion by oblique ion implantation. | 06-24-2010 |
20100127357 | SEMICONDUCTOR DEVICE - A semiconductor device includes a seal ring formed on an outer circumference of an element forming region when seen from the top in a multilayer interconnect structure formed on a silicon layer, and dummy metal structures formed on a further outer circumference of the seal ring. The more inner circumference side the dummy interconnect is formed on, the more upper layer the dummy interconnect is arranged on. | 05-27-2010 |
20100122072 | Debugging system, debugging method, debugging control method, and debugging control program - A debugging system according to an exemplary embodiment of the present invention includes: a plurality of arithmetic processing units ( | 05-13-2010 |
20100054062 | Static random access memory (SRAM) and test method of the SRAM having precharge circuit to precharge bit line - An SRAM includes a memory cell and a precharge circuit. The precharge circuit precharges a bit line pair with a power supply voltage before writing a data in the memory cell or before reading a data therefrom at a time of a normal mode, and which feeds a power supply voltage to at least a low level data-holding node of a node pair of the memory cell at a time of a read test mode, between time for writing a data in the memory cell and time for reading a data therefrom. | 03-04-2010 |
20100013092 | Semiconductor device and manufacturing method therefor - Provided is a semiconductor device having a bump structure which is capable of resolving inconvenience in mounting. The semiconductor device comprises: an electrode pad; and a columnar bump formed on the electrode pad, the columnar bump comprising: a first high melting point metal layer ( | 01-21-2010 |
20080301420 | Branch prediction control device having return address stack and method of branch prediction - A branch prediction control device, in an information processing unit which performs a pipeline process, generates a branch prediction address used for verification of an instruction being speculatively executed. The branch prediction control device includes a first return address storage unit storing the prediction return address, a second return address storage unit storing a return address to be generated depending on an execution result of the call instruction, and a branch prediction address storage unit sending a stored prediction return address as a branch prediction address and storing the sent branch prediction address. When the branch prediction address differs from a return address, which is generated after executing a branch instruction or a return instruction, contents stored in the second return address storage unit are copied to the first return address storage unit. | 12-04-2008 |