| NEC Computertechno, Ltd. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120063246 | MEMORY CONTROLLER, MEMORY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD OF MEMORY DEVICE - One aspect of the present invention is a memory controller which controls a memory device including two or more memory access units and includes a data control circuit and an adjusting circuit that performs at least one of a first processing and a second processing. In the first processing, a timing of the write strobe signal generated by the data control circuit in a write operation is adjusted for each memory access unit and a write strobe adjusting signal specifying a timing for each memory access unit to load write data is generated, and in the second processing, a timing of the read strobe signal generated by the memory device in a read operation is adjusted for each memory access unit and a read strobe adjusting signal specifying a timing for the data control unit to read data read out from each memory access unit is generated. | 03-15-2012 |
| 20090193232 | Apparatus, processor and method of cache coherency control - An apparatus includes a plurality of processors each of which includes a cache memory, and a controller which suspends a request of at least one of the processors during a predetermined period when a processor fetches a data from a main memory to the cache memory, wherein the controller suspends the request of at least one of the processors except the processor which fetches the data from the main memory to the cache memory. | 07-30-2009 |
| 20080256416 | Apparatus and method for initializing memory - An apparatus includes a memory including a controller for initializing the memory, the controller storing a first data including a first code for correcting a first error of the first data, to the memory when initializing, and a memory controller controlling a data transmission to the memory, the memory controller being connected to the memory. The memory controller includes a code generation circuit storing a second data including a second code, to the memory after the initializing, the second code including an address parity for detecting an address causing a second error of the second data in said memory. | 10-16-2008 |
