| NATIONAL SEMICONDUCTOR CORPORATION Patent applications |
| Patent application number | Title | Published |
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| 20120121113 | Directional control of sound in a vehicle - A system for directing sound in a vehicle includes a passenger selector, a controller, a pattern generator and a speaker array. The passenger selector is configured to generate a direction signal based on a selection of at least one passenger in the vehicle. The controller is configured to generate a pattern signal based on the direction signal. The pattern generator is configured to receive unpatterned audio data and to generate patterned audio data based on the pattern signal. The speaker array is configured to receive the patterned audio data and to generate a directed sound field based on the patterned audio data such that the directed sound field is directed toward the at least one selected passenger. | 05-17-2012 |
| 20120119930 | Background Calibration Method For Fixed Gain Amplifiers - A method for calibrating a fixed gain amplifier configured as a front-end amplification stage of an analog-to-digital converter including sampling a calibration voltage with normal and inversed polarity and with the fixed gain amplifier bypassed and with the fixed gain amplifier connected. An actual gain value of the fixed gain amplifier is computed from offset corrected digital output codes generated from converting the calibration voltage. A gain correction value for the fixed gain amplifier can then be computed based on the ratio of the actual gain to the ideal gain. In another embodiment, a method for calibrating an analog-to-digital converter including a fixed gain amplifier, an input buffer and a modulator generates an offset correction value using normal and polarity inversed input samples. The offset correct value provides correction for at least offset errors in the fixed gain amplifier, the input buffer and the modulator. | 05-17-2012 |
| 20120105032 | SYSTEM AND METHOD FOR PROVIDING AN ACTIVE CURRENT ASSIST WITH ANALOG BYPASS FOR A SWITCHER CIRCUIT - A system and method are disclosed for providing an active current assist with analog bypass for a switcher circuit. An active current assist circuit is coupled to a buck regulator circuit, which includes a switcher circuit, an inductor circuit and a capacitor circuit. The active current assist circuit includes an active current analog bypass control circuit and a current source. The active current analog bypass control circuit receives and uses current limit information, voltage error information, and drop out information to determine a value of assist current that is appropriate for a current operational state of the buck regulator circuit. The active current analog bypass control circuit causes the current source to provide the appropriate value of assist current to the buck regulator circuit. | 05-03-2012 |
| 20120093348 | Generation of 3D sound with adjustable source positioning - A system for generating 3D sound with adjustable source positioning includes a first stage and a second stage, which is coupled to the first stage and to a speaker array that includes a plurality of speakers. The first stage is configured to position a plurality of virtual sound sources through a positioner output. The second stage is configured to generate a 3D signal for the speaker array based on the positioner output. The speaker array is configured to generate a 3D sound stage including the virtual sound sources based on the 3D signal. The first stage may be further configured to reposition the virtual sound sources. | 04-19-2012 |
| 20120086701 | Combined digital modulation and current dimming control for light emitting diodes - A method includes providing an input signal identifying a desired brightness for one or more LEDs to first and second parallel control paths. The method also includes generating a digital modulation control signal using the first control path, generating a current control signal using the second control path, and driving the one or more LEDs using the control signals. The method further includes performing compensation in at least one of the control paths to compensate for an increased efficiency of the one or more LEDs. Generating the control signals could include (i) adjusting the digital modulation control signal while maintaining the current control signal at a substantially constant value for a range of lower LED brightness values and (ii) adjusting the current control signal while maintaining the digital modulation control signal at a maximum value or within a range of maximum values for a range of higher LED brightness values. | 04-12-2012 |
| 20120080781 | DELAMINATION RESISTANT DEVICE PACKAGE HAVING RAISED BOND SURFACE AND MOLD LOCKING APERTURE - A semiconductor package configured to attain a thin profile and low moisture sensitivity. Packages of this invention can include a semiconductor die mounted on a die attachment site of a leadframe and further connected with a plurality of elongate I/O leads arranged about the die attach pad and extending in said first direction. The leadframe having an “up-set” bonding pad arranged with a bonding support for supporting a plurality of wire bonds and a large mold flow aperture in the up-set bonding pad. The package encapsulated in a mold material that surrounds the bonding support and flows through the large mold flow aperture to establish well supported wire bonds such that the package has low moisture sensitivity. | 04-05-2012 |
| 20120074995 | Fractional-N PLL Using Multiple Phase Comparison Frequencies to Improve Spurious Signal Performance - SEARCHES A fractional spur compensation technique is implemented in a fractional-N PLL using multiple phase comparison frequencies F | 03-29-2012 |
| 20120074561 | BACKMETAL REPLACEMENT FOR USE IN THE PACKAGING OF INTEGRATED CIRCUITS - One aspect of the invention pertains to an arrangement for forming exposed die packages. The arrangement includes a semiconductor wafer having multiple integrated circuit dice whose back surfaces cooperate to form the back surface of the wafer. A thermally conductive adhesive layer is deposited on the back surface of the wafer. The metal foil is attached to the wafer with the adhesive layer. Methods of forming exposed die packages using the above arrangement are also described. | 03-29-2012 |
| 20120057313 | PACKAGE FOR SYSTEM LEVEL ELECTRONIC PRODUCTS - Methods and arrangements for packaging system level electronics are described. In one aspect, an external skin of the package is formed from isolation paper. In some embodiments, the isolation paper is formed into a box. A printed circuit board is placed within the isolation paper skin and is substantially completely surrounded by a potting material that substantially completely fills the skin. The potting material is cured to solidify the potting material within the isolation paper box and to adhere the potting material to the isolation paper such that the isolation paper forms a skin for a brick of potting material that encapsulates the printed circuit board. The isolation paper skin includes at least one opening that permits an interconnect to be exposed through the skin. With this arrangement, a packaged electronics device is provided and the isolation paper forms the exposed outer surface of the packaged electronics device. The described package is particularly well suited for use in packaging system level power electronics such as power supplies. | 03-08-2012 |
| 20120056244 | Growth of multi-layer group III-nitride buffers on large-area silicon Substrates and other substrates - A method includes forming a first epitaxial layer over a semiconductor substrate and etching the first epitaxial layer to form multiple separated first epitaxial regions. The method also includes forming a second epitaxial layer over the etched first epitaxial layer. Each epitaxial layer includes at least one Group III-nitride, and the epitaxial layers collectively form a buffer. The method further includes forming a device layer over the buffer and fabricating a semiconductor device using the device layer. The second epitaxial layer could include second epitaxial regions substantially only on the first epitaxial regions. The second epitaxial layer could also cover the first epitaxial regions and the substrate, and the second epitaxial layer may or may not be etched. The device layer could be formed during the same operation used to form the second epitaxial layer. | 03-08-2012 |
| 20120043660 | THIN FOIL SEMICONDUCTOR PACKAGE - One aspect of the present invention involves a foil-based method for packaging integrated circuits. Initially, a metallic foil and a photoresist layer are attached with a carrier. The photoresist layer is exposed and patterned. Afterward, multiple integrated circuit dice are connected to the foil. The dice and portions of the foil are encapsulated in a molding material. The foil is then etched based on the patterned photoresist layer to define multiple device areas in the foil, where each device area supports at least one of the integrated circuit dice. Some aspects of the present invention relate to panel arrangements that are involved in the aforementioned method. | 02-23-2012 |
| 20120032354 | WIREBONDING METHOD AND DEVICE ENABLING HIGH-SPEED REVERSE WEDGE BONDING OF WIRE BONDS - Methods and systems are described for enabling the efficient fabrication of wedge bonding of integrated circuit systems and electronic systems. In particular a reverse bonding approach can be employed. | 02-09-2012 |
| 20120031955 | WIRE BONDING METHOD AND CAPILLARY ENABLING HIGH-SPEED WEDGE BONDING OF WIRE BONDS - Methods and systems are described for enabling the efficient fabrication of wedge-bonding of integrated circuit systems and electronic systems. | 02-09-2012 |
| 20120020441 | FIXED POINT FIR FILTER WITH ADAPTIVE TRUNCATION AND CLIPPING AND WIRELESS MOBILE STATION USING SAME - A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier receiving a selected one of the N sequential input samples from the delay elements and multiplying the selected input sample by a corresponding coefficient to produce an intermediate product; and iii) a summer for receiving and adding N intermediate products from the multipliers to produce an output sum signal comprising a sequence of output sum samples; and 2) an output stage for truncating k least significant bits (LSBs) from each of the output sum samples, wherein k is a variable number. | 01-26-2012 |
| 20120001854 | Analog resistive multi-touch display screen - A method is provided for supporting resistive multi-touch with a touch-sensitive display screen. The display screen includes a resistive network that varies depending on where the display screen is contacted. The display screen has a first plane resistance and a second plane resistance when the display screen is not contacted. The method includes detecting one or more objects contacting the display screen. The method also includes identifying coordinates of multiple contact points on the display screen based on a change in at least one of the plane resistances. The change is caused by one or more parallel resistances created in the display screen by the multiple contact points. | 01-05-2012 |
| 20110316588 | Resistor-programmable device at low voltage - A resistor-programmable device generates pulses counted by a counter. The counter's output controls a drive signal generator, such as an adjustable current source. The drive signal generator generates a drive signal (such as a current), which leads to the creation of a sense signal (such as a voltage) using a resistance. The resistance can have one of a set of specified values or fall within one of a set of specified windows. The resistor-programmable device can convert the resistance value into a digital value, which can be used to set a sensor trip point threshold or some other parameter. The digital or parameter value is independent of changes in the resistance that are within a specified tolerance. For instance, the same parameter value could be selected even when the resistance varies within some tolerance (such as 1%) as the resistor-programmable device can determine the window in which the resistance falls. | 12-29-2011 |
| 20110291729 | Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) systems - An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays. | 12-01-2011 |
| 20110291485 | STACKED POWER SUPPLY MONITOR WITH SENSE-REPLICA LOOP - An apparatus includes a sense module configured to be coupled to at least one power supply, where the sense module has a first leg. The apparatus also includes a replica module having a second leg, where the first and second legs have a common structure. The apparatus further includes a feedback loop configured to cause an output voltage across terminals of the replica module to at least substantially equal an input voltage across terminals of the sense module based on sense currents in the first and second legs. At least one cascode stage coupled to the sense module can be configured to reduce a voltage at which one or more signals from the sense module are referenced. One or more trim units can be used to reduce a gain error and/or an offset error between the input voltage and the output voltage. | 12-01-2011 |
| 20110289248 | Isolated communication bus and related protocol - A system includes a master device and multiple slave devices. The system also includes multiple bus interfaces forming a communication bus that couples the master and slave devices. Each bus interface includes a primary interface unit configured to communicate over first and second buses, where the first and second buses form a portion of the communication bus. Each bus interface also includes a secondary interface unit configured to communicate with the primary interface unit and to communicate with one of the slave devices over a third bus. Each bus interface further includes an isolator configured to electrically isolate the primary interface unit and the secondary interface unit. The primary interface unit is configured to receive multiple commands over the first bus, execute a first subset of commands, transmit a second subset of commands over the second bus, and transmit a third subset of commands over the third bus. | 11-24-2011 |
| 20110289247 | Autonomous positional addressing in stacked multi-board systems - A method includes receiving a first address over an address bus at a first module, modifying the first address to generate a second address, and transmitting the second address over the address bus to a second module. The method also includes determining at the first module if at least one of the first and second addresses has a specified value. Modifying the first address could include incrementing or decrementing the first address to generate the second address. Determining if at least one of the first and second addresses has the specified value could include determining if the first address has a value of zero or a value of 2 | 11-24-2011 |
| 20110287596 | SYSTEM AND METHOD FOR PROVIDING LOW VOLTAGE HIGH DENSITY MULTI-BIT STORAGE FLASH MEMORY - A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates. | 11-24-2011 |
| 20110285318 | Compact and efficient driver for multiple light emitting diodes (LEDs) - A method includes receiving a variable reference voltage at a power converter and generating a regulated output voltage based on the variable reference voltage. The method also includes sequentially driving multiple sets of light emitting diodes (LEDs) using the regulated output voltage, where each set includes at least one LED. The variable reference voltage varies based on the set of LEDs being driven. For example, the method could include receiving a first reference voltage, generating a first output voltage based on the first reference voltage, and driving a first set of LEDs using the first output voltage. The method could then include receiving a second reference voltage, generating a second output voltage based on the second reference voltage, and driving a second set of LEDs using the second output voltage. At least one additional set of LEDs could be driven concurrently with the sequential driving of the multiple sets of LEDs. | 11-24-2011 |
| 20110284859 | Growth of group III nitride- based structures and integration with conventional CMOS processing tools - A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools. | 11-24-2011 |
| 20110280352 | FIXED POINT FIR FILTER WITH ADAPTIVE TRUNCATION AND CLIPPING AND WIRELESS MOBILE STATION USING SAME - A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier receiving a selected one of the N sequential input samples from the delay elements and multiplying the selected input sample by a corresponding coefficient to produce an intermediate product; and iii) a summer for receiving and adding N intermediate products from the multipliers to produce an output sum signal comprising a sequence of output sum samples; and 2) an output stage for truncating k least significant bits (LSBs) from each of the output sum samples, wherein k is a variable number. | 11-17-2011 |
| 20110280350 | FIXED POINT FIR FILTER WITH ADAPTIVE TRUNCATION AND CLIPPING AND WIRELESS MOBILE STATION USING SAME - A fixed point finite impulse response (FIR) filter comprising: 1) an input stage for receiving an input signal as a sequence of input samples comprising: i) delay elements connected in series for receiving and shifting N sequential input samples; ii) multipliers, each multiplier receiving a selected one of the N sequential input samples from the delay elements and multiplying the selected input sample by a corresponding coefficient to produce an intermediate product; and iii) a summer for receiving and adding N intermediate products from the multipliers to produce an output sum signal comprising a sequence of output sum samples; and 2) an output stage for truncating k least significant bits (LSBs) from each of the output sum samples, wherein k is a variable number. | 11-17-2011 |
| 20110269269 | LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS - The present inventions relate generally to methods for packaging integrated circuits using thin foils that form electrical interconnects for the package. The foil includes a base layer (such as copper) with an optional plating layer (such as silver) suitable for improving adhesion of the bonding wires (or other connectors) to the foil. The base layer (or the plated surface if the foil is preplated) of the foil is patterned by laser ablation to define components (e.g. contacts) of a device area. The patterning is arranged to ablate entirely through selected portions of the plating layer and part, but not all, of the way through corresponding underlying portions of the base layer. In some embodiments, the metallic foil is partially etched after the laser ablation in order to deepen the trenches that define the patterning of the foil. Multiple dice may then be attached to die attach pad areas of the plated foil and electrically coupled to electrical contacts. Some embodiments contemplate encapsulating the dice, bonding wires, and portions of the plated foil with a plastic molding material. Portions of the metallic foil may then be removed by etching, laser ablation, or grinding. The resulting structure may then be singulated to form individual integrated circuit packages. | 11-03-2011 |
| 20110266972 | Dynamic current equalization for light emitting diode (LED) and other applications - A system includes multiple dynamic current equalizers (DCEs). Each DCE includes a first control loop configured to regulate a current through a circuit branch associated with the dynamic current equalizer. The first control loop includes a first amplifier having two inputs. Each DCE also includes a second control loop configured to regulate a control signal. The second control loop includes a second amplifier having two inputs coupled to the inputs of the first amplifier. The first amplifier has an input offset compared to the second amplifier. The DCEs are configured such that one DCE regulates the control signal while one or more other DCEs regulate the currents through the associated circuit branches based on the control signal. The DCEs can be configured to achieve one or more ratios between multiple currents flowing through multiple circuit branches, where the one or more ratios are defined by resistances coupled to the DCEs. | 11-03-2011 |
| 20110234318 | LOW VOLTAGE DIFFERENTIAL SIGNAL DRIVER WITH REDUCED POWER CONSUMPTION - A low voltage differential signal (LVDS) driver circuit with reduced power consumption. A pre-driver stage, implemented as a differential current mode amplifier, is driven by the differential input signal and provides a corresponding differential drive signal, which drives the output stage, implemented as a differential voltage mode amplifier, which, in turn, provides the differential output signal for the load. Total current consumption equals the load current, which is provided by the output stage, plus a much smaller current used by the pre-driver stage. | 09-29-2011 |
| 20110233670 | METHOD OF FORMING A REGION OF GRADED DOPING CONCENTRATION IN A SEMICONDUCTOR DEVICE AND RELATED APPARATUS - A method for forming a doped region of a semiconductor device includes masking a portion of a substrate with a mask. The mask is configured to create a graded doping profile within the doped region. The method also includes performing an implant using the mask to create doped areas and undoped areas in the substrate. The method further includes diffusing the doped areas to create the graded doping profile in the doped region. The mask could include a first region having openings distributed throughout a photo-resist material, where the openings vary in size and spacing. The mask could also include a second region having blocks of photo-resist material distributed throughout an open region, where the photo-resist blocks vary in size and spacing. Diffusing the doped areas could include applying a high temperature anneal to smooth the doped and undoped areas to produce a linearly graded doping profile. | 09-29-2011 |
| 20110227547 | Sensing capacitor for constant on-time and constant off-time switching regulators - A method includes generating an output voltage using a constant on-time or constant off-time (COT) switching regulator. The switching regulator includes a switch and an output capacitor. The method also includes sensing a first current flowing through a sensing capacitor, where the first current is proportional to a second current flowing through the output capacitor. The method further includes controlling the switch based on the sensed first current. Controlling the switch could include generating a feedback voltage using the sensed first current, combining the feedback and output voltages to generate a combined voltage, comparing a scaled version of the combined voltage and a reference voltage, and triggering a one-shot timer based on the comparison. A capacitance of the output capacitor may be greater than a capacitance of the sensing capacitor by a factor of N, and a transimpedance amplifier having a gain based on N could generate the feedback voltage. | 09-22-2011 |
| 20110221031 | SYSTEM AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ANTI-FUSE IN CONJUNCTION WITH A TUNGSTEN PLUG PROCESS - A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse. | 09-15-2011 |
| 20110215419 | SYSTEM AND METHOD FOR IMPROVING CMOS COMPATIBLE NON VOLATILE MEMORY RETENTION RELIABILITY - A system and method is disclosed for improving complementary metal oxide semiconductor (CMOS) compatible non volatile memory (NVM) retention reliability in memory cells. A memory cell of the invention comprises a backend layer that reduces charge leakage from a floating gate of the memory cell. A first bottom portion of the backend layer is formed from a first layer of silicon oxynitride having a low value of defect/trap density. A second top portion of the backend layer is formed from a second layer of silicon oxynitride having a high value of defect/trap density. The first layer of silicon oxynitride inhibits electron transport and the second layer of silicon oxynitride protects CMOS devices from plasma induced damage. | 09-08-2011 |
| 20110215373 | SYSTEM AND METHOD FOR MANUFACTURING DOUBLE EPI N-TYPE LATERAL DIFFUSION METAL OXIDE SEMICONDUCTOR TRANSISTORS - A system and a method are disclosed for manufacturing double epitaxial layer N-type lateral diffusion metal oxide semiconductor transistors. In one embodiment two N-type buried layers are used to minimize the operation of a parasitic PNP bipolar transistor. The use of two N-type buried layers increases the base width of the parasitic PNP bipolar transistor without significantly decreasing the peak doping profiles in the two N-type buried layers. In one embodiment two N-type buried layers and one P-type buried layer are used to form a protection NPN bipolar transistor that minimizes the operation of parasitic NPN bipolar transistor. The N-type lateral diffusion metal oxide semiconductor transistors of the invention are useful in inductive full load or half bridge converter circuits that drive very high current. | 09-08-2011 |
| 20110211380 | THREE-QUARTER BRIDGE POWER CONVERTERS FOR WIRELESS POWER TRANSFER APPLICATIONS AND OTHER APPLICATIONS - A three-quarter bridge power converter includes a first switch configured to selectively couple a switch node to a higher voltage. The power converter also includes a second switch configured to selectively couple the switch node to a lower voltage. The power converter further includes a third switch configured to selectively cause a third voltage to be provided to the switch node when the first and second switches are not coupling the switch node to the higher and lower voltages. The third switch may be configured to selectively couple the switch node to an energy storage or energy source, such as a capacitor. The third switch may also be configured to selectively couple an energy storage or energy source to ground, where the energy storage or energy source is coupled to the switch node. | 09-01-2011 |
| 20110180854 | Normally-off gallium nitride-based semiconductor devices - A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride. | 07-28-2011 |
| 20110180848 | HIGH PERFORMANCE SiGe:C HBT WITH PHOSPHOROUS ATOMIC LAYER DOPING - A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles. | 07-28-2011 |
| 20110167892 | SYSTEM AND METHOD FOR CALIBRATING A WAFER HANDLING ROBOT AND A WAFER CASSETTE - A system and method is disclosed for calibrating a semiconductor wafer handling robot and a semiconductor wafer cassette. A robot blade boot is attached to a robot blade of the semiconductor handling robot. The robot blade boot decreases a value of tolerance for the robot blade to move between two semiconductor wafers in the semiconductor wafer cassette. In one embodiment the vertical tolerance is decreased to approximately twenty thousandths of an inch (0.020″) on a top and a bottom of the robot blade boot. The use of the robot blade boot makes the calibration steps more critical and precise. The robot blade boot is removed from the robot blade after the calibration process has been completed. | 07-14-2011 |
| 20110163457 | INTEGRATED CIRCUIT MICRO-MODULE - One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna. | 07-07-2011 |
| 20110152703 | Heart monitoring system or other system for measuring magnetic fields - A system includes at least one first magnetic field sensor configured to measure first and second magnetic fields. The system also includes at least one second magnetic field sensor configured to measure the second magnetic field substantially without measuring the first magnetic field. The system further includes processing circuitry configured to perform signal cancellation to generate measurements of the first magnetic field and to generate an output based on the measurements of the first magnetic field. The sensors could represent magneto-electric sensors. The magneto-electric sensors could be configured to up-convert electrical signals associated with the first and/or second magnetic fields to a higher frequency. The processing circuitry could be configured to identify one or more problems associated with a patient's heart. | 06-23-2011 |
| 20110148403 | Magneto-electric sensor with injected up-conversion or down-conversion - A method includes generating an electrical signal representing a magnetic field using a magnetic field sensor having alternating layers of magneto-strictive material and piezo-electric material. The method also includes performing up-conversion or down-conversion so that the electrical signal representing the magnetic field has a higher or lower frequency than a frequency of the magnetic field. The up-conversion or down-conversion is performed before the magnetic field is converted into the electrical signal. The up-conversion or down-conversion could be performed by repeatedly sensitizing and desensitizing the magnetic field sensor. This could be done using a permanent magnet and an electromagnet, an electromagnet without a permanent magnet, or a movable permanent magnet. The up-conversion or down-conversion could also be performed by chopping the magnetic field. The chopping could involve intermittently shielding the magnetic field sensor from the magnetic field or moving the magnetic field sensor with respect to the magnetic field. | 06-23-2011 |
| 20110140262 | MODULE PACKAGE WITH EMBEDDED SUBSTRATE AND LEADFRAME - An integrated circuit package is described that includes a substrate, a leadframe and one or more integrated circuits that are positioned between the substrate and the leadframe. Multiple electrical components may be attached to one or both sides of the substrate. The active face of the integrated circuit is electrically and physically connected to the substrate. The back side of the integrated circuit is mounted on a die attach pad of the leadframe. The leadframe includes multiple leads that are physically attached to and electrically coupled with the substrate. A molding material encapsulates portions of the substrate, the leadframe and the integrated circuit. Methods for forming such packages are also described. | 06-16-2011 |
| 20110140253 | DAP GROUND BOND ENHANCEMENT - A variety of semiconductor package arrangements and packaging methods are described that improve the reliability of bonding wires that down bond a die to a die attach pad. In one aspect, selected portions of the top surface of a lead frame (which may be in panel form) are plated (e.g., silver plated) to facilitate wire bonding. The plating covers some, but not all of a die attach surface of the die attach pad. In some preferred embodiments, the plating on the die attach pad is arranged as a peripheral ring that surrounds an unplated central region of the die support surface. In other embodiments, the plating on the die attach pad takes the form of bars or other geometric patterns that do not fully cover the die support surface. Unplated portions of the die support surface are roughened to improve the adherence of the die to the die attach pad, thereby reducing the probability of die attach pad delamination and the associated risks to down bonded bonding wires. The described lead frames may be used in a variety of packages. Most commonly, a die is attached to the die support surface of the die attach pad and electrically connected to the lead frame leads by wire bonding as appropriate. At least one of the die's bond pads (typically the ground bond pad(s)) is down bonded to the die attach pad. The die, the bonding wires and at least portions of the lead frame are then typically encapsulated with a plastic encapsulant material while leaving a contact surface of the die attach pad exposed to facilitate electrically coupling the die attach pad to an external device. | 06-16-2011 |
| 20110140249 | TIE BAR AND MOLD CAVITY BAR ARRANGEMENTS FOR MULTIPLE LEADFRAME STACK PACKAGE - A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes. | 06-16-2011 |
| 20110140242 | Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates - A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation. | 06-16-2011 |
| 20110140173 | Low OHMIC contacts containing germanium for gallium nitride or other nitride-based power devices - An apparatus includes a substrate, a Group III-nitride layer over the substrate, and an electrical contact over the Group III-nitride layer. The electrical contact includes a stack having multiple layers of conductive material, and at least one of the layers in the stack includes germanium. The layers in the stack may include a contact layer, where the contact layer includes aluminum copper. The stack could include a titanium or titanium alloy layer, an aluminum or aluminum alloy layer, and a germanium or germanium alloy layer. At least one of the layers in the stack could include an aluminum or titanium alloy having a germanium content between about 1% and about 5%. | 06-16-2011 |
| 20110140118 | Backside stress compensation for gallium nitride or other nitride-based semiconductor devices - A method includes forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process. The amorphous or microcrystalline material could create no or a smaller amount of stress on the substrate, and the crystallized material could create a larger amount of stress on the substrate. | 06-16-2011 |
| 20110115436 | ACTIVE CELL AND MODULE BALANCING FOR BATTERIES OR OTHER POWER SUPPLIES - A system includes multiple power modules, each having multiple power cells coupled in series. Each power module has a charge that is based on charges of the power cells in that power module. The system also includes multiple active cell balancing circuits, each configured to substantially balance the charges of the power cells in an associated one of the power modules. The system further includes an active module balancing system configured to substantially balance the charges of the power modules by charging a first subset of the power modules and/or discharging a second subset of the power modules. The active module balancing system could include multiple module balancing circuits, each associated with one of the power modules and configured to charge or discharge its associated power module. A direct current (DC) bus can be configured to transport DC power between the module balancing circuits. | 05-19-2011 |
| 20110115395 | DIMMER DECODER WITH IMPROVED EFFICIENCY FOR USE WITH LED DRIVERS - A method includes receiving a sense signal having multiple pulses, where the sense signal is based on an output of a dimmer. The method also includes, for each of multiple sampling periods, sampling a subset of the pulses in the sense signal during that sampling period. The method further includes generating a holding current for the dimmer during the sampling of the subset of pulses in at least one of the sampling periods. In addition, the method includes, for each of the sampling periods, generating an output value identifying a duty cycle for driving one or more light emitting diodes (LEDs). The subset of pulses in each of the sampling periods includes multiple pulses during that sampling period but not one or more initial pulses at a beginning of that sampling period. | 05-19-2011 |
| 20110115071 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit. | 05-19-2011 |
| 20110104854 | METHOD AND LEADFRAME FOR PACKAGING INTEGRATED CIRCUITS - A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads. | 05-05-2011 |
| 20110095365 | Power transistor with improved high-side operating characteristics and reduced resistance and related apparatus and method - A method includes forming a transistor device on a first side of a semiconductor-on-insulator structure. The semiconductor-on-insulator structure includes a substrate, a dielectric layer, and a buried layer between the substrate and the dielectric layer. The method also includes forming a conductive plug through the semiconductor-on-insulator structure. The conductive plug is in electrical connection with the transistor device. The method further includes forming a field plate on a second side of the semiconductor-on-insulator structure, where the field plate is in electrical connection with the conductive plug. The transistor device could have a breakdown voltage of at least 600V, and the field plate could extend along at least 40% of a length of the transistor device. | 04-28-2011 |
| 20110089914 | Apparatus and method for isolating an adaptive voltage scaling (AVS) loop in a powered system - A method includes generating a regulated voltage for a powered component and modifying the regulated voltage with an adaptive voltage scaling (AVS) control loop. The method also includes further modifying the regulated voltage using at least one additional control loop. The AVS control loop is isolated from the at least one additional control loop. Modifying the regulated voltage with the AVS control loop could include storing an AVS digital value and converting the AVS digital value into an analog signal. Modifying the regulated voltage with the AVS control loop could also include modifying a control signal for a voltage regulator using the analog signal, where the voltage regulator generates the regulated voltage. Modifying the regulated voltage with the AVS control loop could further include buffering the analog signal and outputting the buffered analog signal as an isolated AVS signal over the AVS control loop. | 04-21-2011 |
| 20110089556 | LEADFRAME PACKAGES HAVING ENHANCED GROUND-BOND RELIABILITY - Various semiconductor package arrangements and methods that improve the reliability of wire bonding a die to ground or other outside contacts are described. In one aspect, selected ground pads on the die are wire bonded to a bonding region located on the tie bar portion of the lead frame. The tie bar is connected to an exposed die attach pad that is downset from the bonding region of the tie bar. In some embodiments, the bonding region and the leads are at substantially the same elevation above the die and die attach pad. The die, bonding wires, and at least a portion of the lead frame can be encapsulated with a plastic encapsulant material while leaving a contact surface of the die attach pad exposed to facilitate electrically coupling the die attach pad to an external device. | 04-21-2011 |
| 20110089546 | MULTIPLE LEADFRAME PACKAGE - Apparatuses and methods directed to a semiconductor chip package having multiple leadframes are disclosed. Packages can include a first leadframe having a die attach pad and a first plurality of electrical leads, a second leadframe that is generally parallel to the first leadframe and having a second plurality of electrical leads, and a plurality of direct electrical connectors between the first and second leadframes, where such direct electrical connectors control the distance between the leadframes. Additional device components can include a primary die, an encapsulant, a secondary die, an inductor and/or a capacitor. The plurality of direct electrical connectors can comprise polymer balls having solder disposed thereabout. Alternatively, the direct electrical connectors can comprise metal tabs that extend from one leadframe to the other. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes. | 04-21-2011 |
| 20110089473 | Method for improved mobility using hybrid orientation technology (HOT) in conjunction with selective epitaxy and related apparatus - A semiconductor apparatus includes a first substrate and a second substrate located over a first portion of the first substrate and separated from the first substrate by a buried layer. The semiconductor apparatus also includes an epitaxial layer located over a second portion of the first substrate and isolated from the second substrate. The semiconductor apparatus further includes a first transistor formed at least partially in the second substrate and a second transistor formed at least partially in or over the epitaxial layer. The second substrate and the epitaxial layer have bulk properties with different electron and hole mobilities. At least one of the transistors is configured to receive one or more signals of at least about 5V. The first substrate could have a first crystalline orientation, and the second substrate could have a second crystalline orientation. | 04-21-2011 |
| 20110084646 | Off-grid led street lighting system with multiple panel-storage matching - A system includes multiple photovoltaic panels having a combined output profile that defines energy or power generated by the photovoltaic panels over time. Each photovoltaic panel is configured to generate a peak amount of energy or power at a different time. The system also includes a storage device having a charging profile and configured to be charged by the photovoltaic panels. The charging profile defines a maximum amount of energy or power sinkable by the storage device at a given time. The output profile and the charging profile are substantially matched such that a maximum level of the output profile is approximately equal to the maximum amount of energy or power sinkable by the storage device. The maximum level of the output profile could be substantially constant over time between first and second peak amounts of energy or power generated by different photovoltaic panels. | 04-14-2011 |
| 20110084623 | Dimmer decoder with adjustable filter for use with led drivers - A method includes receiving a sense signal having multiple pulses, where the sense signal is based on an output of a dimmer. The method also includes, for each of multiple sampling periods, (i) identifying at least one pulse duty cycle for at least one pulse in the sense signal during that sampling period and (ii) generating an output value identifying a duty cycle for driving one or more light emitting diodes (LEDs). The output value is based on the at least one pulse duty cycle. The method further includes filtering the output values using a filter and adjusting the filter based on a rate at which the output of the dimmer changes. The filter could be adjusted by controlling whether an additional resistor forms part of an RC filter based on a sampling state. | 04-14-2011 |
| 20110084622 | DIMMER DECODER WITH LOW DUTY CYCLE HANDLING FOR USE WITH LED DRIVERS - A method includes receiving a sense signal having multiple pulses, where the sense signal is based on an output of a dimmer. The method also includes, for each of multiple sampling periods, (i) identifying a pulse duty cycle by sampling at least one pulse in the sense signal and calculating a duty cycle of the at least one pulse and (ii) generating an output value identifying a duty cycle for driving one or more LEDs. The output value is based on the pulse duty cycle. The method further includes generating a holding current for the dimmer (i) during the sampling of the at least one pulse in at least one of the sampling periods and (ii) when the pulse duty cycle is less than a specified threshold. The holding current can be applied continuously when the pulse duty cycle is less than the specified threshold (such as 15%). | 04-14-2011 |
| 20110084607 | Integrated driver system architecture for light emitting diodes (LEDS) - A method includes forming one or more capacitors over a substrate. The method also includes forming a transformer at least partially over the substrate. The transformer is adjacent to at least one of the one or more capacitors. At least a portion of the transformer is formed at a same level over the substrate as the one or more capacitors. The method further includes coupling the one or more capacitors and the transformer to at least one embedded integrated circuit die. The one or more capacitors, the transformer, and the at least one embedded integrated circuit die form at least part of a light emitting diode (LED) driver. | 04-14-2011 |
| 20110084407 | SYSTEM AND METHOD FOR PREVENTING METAL CORROSION ON BOND PADS - A system and method are disclosed for preventing metal corrosion on bond pads. During manufacture of an integrated circuit device an anti-reflective coating (ARC) layer is applied to a metal stack of a bond pad. A mask and etch process is applied to etch an aperture through the ARC layer down to the metal stack. Then a passivation layer is applied to cover the ARC layer and the aperture through the ARC layer. Then another mask and etch process is applied to etch a bond pad opening through the passivation layer inside the ARC layer aperture down to the metal stack. Interior edge portions of the passivation layer seal the interior edge portions of the ARC layer aperture to prevent corrosion of the ARC layer due to high temperatures, high humidity and corrosive materials encountered in subsequent assembly operations of the integrated circuit device. | 04-14-2011 |
| 20110074003 | FOIL BASED SEMICONDUCTOR PACKAGE - The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One embodiment of the present invention involves attaching multiple dice to a foil carrier structure. The foil carrier structure is made of a thin foil that is bonded to a carrier. The dice and at least a portion of the metallic foil is then encapsulated with a molding material. The carrier is removed, leaving behind a molded foil structure. The exposed foil is patterned and etched using photolithographic techniques to define multiple device areas in the foil. Each device area includes multiple conductive lines. Afterwards, portions of the conductive lines are covered with a dielectric material and other portions are left exposed to define multiple bond pads in the device area. The molded foil structure can be singulated to form multiple integrated circuit packages. | 03-31-2011 |
| 20110073481 | FOIL PLATING FOR SEMICONDUCTOR PACKAGING - Arrangements for plating a single surface of a thin foil are described. In one aspect, a metal foil is wrapped tightly at least partially around a plating solution drum. The drum is partially immersed in a plating solution such that the waterline of the metal plating solution is below a break point where the metallic foil strip begins to unwind from the plating solution drum. With this arrangement, one side of the metallic foil strip is exposed to the metal plating solution, while the opposing back side of the metallic foil strip does not come in substantial contact with the metal plating solution. In this manner, the exposed side of the foil is plated while the back surface of the foil is not plated. The drum may be rotated to convey the foil through the plating solution. | 03-31-2011 |
| 20110065256 | SYSTEM AND METHOD FOR INCREASING BREAKDOWN VOLTAGE OF LOCOS ISOLATED DEVICES - An efficient method is disclosed for increasing the breakdown voltage of an integrated circuit device that is isolated by a local oxidation of silicon (LOCOS) process. The method comprises forming a portion of a field oxide in an integrated circuit so that the field oxide has a gradual profile. The gradual profile of the field oxide reduces impact ionization in the field oxide by creating a reduced value of electric field for a given value of applied voltage. The reduction in impact ionization increases the breakdown voltage of the integrated circuit. The gradual profile is formed by using an increased thickness of pad oxide and a reduced thickness of silicon nitride during a field oxide oxidation process. | 03-17-2011 |
| 20110064254 | CASE FOR PROVIDING IMPROVED AUDIO PERFORMANCE IN PORTABLE GAME CONSOLES AND OTHER DEVICES - A system includes a portable electronic device and a case configured to be placed in association with the portable electronic device. The case includes an interface configured to receive audio signals from the portable electronic device and a speaker array configured to generate audible sounds having one or more specified audio effects based on the audio signals. The case could also include an audio amplifier configured to amplify the audio signals and to provide the amplified audio signals to the speaker array. The audio amplifier could include a filter configured to filter the audio signals in order to produce the one or more specified audio effects. The case could further include a processor configured to (i) process the audio signals in order to produce the one or more specified audio effects and (ii) output the processed audio signals to the audio amplifier. | 03-17-2011 |
| 20110057824 | Analog-to-digital converter having output data with reduced bit-width and related system and method - A circuit includes an analog-to-digital converter configured to receive an analog input signal and generate first digital values at a first sampling rate. The first digital values have a first bit-width. The circuit also includes an interpolator configured to receive the first digital values and generate second digital values at a second sampling rate higher than the first sampling rate. The second digital values have a second bit-width equal to or greater than the first bit-width. The circuit further includes a digital filter configured to receive the second digital values and perform bit-width reduction in a recoverable manner to generate third digital values. The third digital values have a third bit-width less than the first and second bit-widths. The circuit could optionally include a recovery circuit configured to process the third digital values to generate recovered digital values at the first sampling rate. The recovered digital values have the first bit-width. | 03-10-2011 |
| 20110051937 | BEAM FORMING IN SPATIALIZED AUDIO SOUND SYSTEMS USING DISTRIBUTED ARRAY FILTERS - A system includes multiple speakers arranged in a speaker array configuration. The system also includes one or more filters configured to filter audio signals and generate filtered audio signals. The one or more filters are configured to operate using filter coefficients associated with a desired beam pattern to be produced by the multiple speakers. The system further includes at least one amplifier configured to amplify the filtered audio signals and provide the amplified filtered audio signals to the speakers. The one or more filters reside within or are coupled to the at least one amplifier. The system may further include a controller configured to modify at least one of the filter coefficients based on a change in the speaker configuration. The filters may operate independently of a centralized processor, and a centralized processor may not even be required to provide electronic beam forming. | 03-03-2011 |
| 20110042778 | SEMICONDUCTOR DEVICE HAVING LOCALIZED INSULATED BLOCK IN BULK SUBSTRATE AND RELATED METHOD - One or more trenches can be formed around a first portion of a semiconductor substrate, and an insulating layer can be formed under the first portion of the semiconductor substrate. The one or more trenches and the insulating layer electrically isolate the first portion of the substrate from a second portion of the substrate. The insulating layer can be formed by forming a buried layer in the substrate, such as a silicon germanium layer in a silicon substrate. One or more first trenches through the substrate to the buried layer can be formed, and open spaces can be formed in the buried layer (such as by using an etch selective to silicon germanium over silicon). The one or more first trenches and the open spaces can optionally be filled with insulative material(s). One or more second trenches can be formed and filled to isolate the first portion of the substrate. | 02-24-2011 |
| 20110025443 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - An apparatus and method for wafer level fabrication of high value inductors directly on top of semiconductor integrated circuits. The apparatus and method includes fabricating a semiconductor wafer including a plurality of dice, each of the dice including power circuitry and a switching node. Once the wafer is fabricated, then a plurality of inductors are fabricated directly onto the plurality of dice on the wafer respectively. Each inductor is fabricated by forming a plurality of magnetic core inductor members on an interconnect dielectric layer formed on the wafer. An insulating layer, and then inductor coils, are then formed over the plurality of magnetic core inductor members over each die. A plated magnetic layer is formed over the plurality of inductors respectively to raise the permeability and inductance of the structure. | 02-03-2011 |
| 20110025362 | APPARATUS AND METHOD FOR MEASURING PHASE NOISE/JITTER IN DEVICES UNDER TEST - A system for testing integrated circuit products and other devices under test (DUT) includes a DUT tester, which stimulates the devices under test and analyzes signals from the devices under test. A device interface board transports signals between the DUT tester and the devices under test. A test board is coupled to the device interface board and used to generate measurements associated with the devices under test, such as phase noise or phase jitter measurements. The test board could, for example, include a phase detector for detecting a phase difference between two signals and a control loop for adjusting at least one of the two signals to maintain an average of zero DC volts at an output of the phase detector. A customization module could also be used to customize the test board. The customization module could include a phase shifter, a phase-locked loop synthesizer, and/or an oscillator. | 02-03-2011 |
| 20110024910 | METALLURGY FOR COPPER PLATED WAFERS - Improved protective metallization arrangements are described that are particularly useful in bumped copper-top type semiconductor chips. In one aspect of the invention, the semiconductor device includes integrated circuits and has a top wafer fabrication passivation layer. A plurality of I/O pads are exposed through contact pad openings formed in the top wafer fabrication passivation layer. A patterned copper layer is formed over the top wafer fabrication passivation layer. The patterned copper layer is electrically coupled to the contact pads through the contact pad openings. A metallic barrier layer is provided between the contact pads and the patterned copper layer. A titanium metallization layer overlies at least portions of the patterned copper layer and preferably cooperates with the barrier layer to envelop the copper layer in the regions of the contact pads. A first aluminum metallization layer overlies at least portions of the titanium metallization layer. An electrically insulating protective layer overlies the first aluminum metallization layer and the top wafer fabrication passivation layer. The protective layer is preferably formed from an organic material and includes a plurality of contact openings. Underbump metallization stacks are formed in the contact openings. Each underbump metallization stack is electrically connected to the first aluminum metallization layer through its associated contact opening in the protective layer. Solder bumps are preferably then adhered to the underbump metallization stacks. | 02-03-2011 |
| 20110013425 | High step-up ratio soft-switched flyback converter - A converter circuit includes a transformer having a first side and a second side. The converter circuit also includes a switch coupled to the first side of the transformer. The converter circuit further includes a rectifying diode coupled to the second side of the transformer and to a first output terminal of the converter circuit. In addition, the converter circuit includes a clamping diode coupled to the second side of the transformer, to the rectifying diode, and to a second output terminal of the converter circuit. The converter circuit may include a boost section and a flyback section. The converter circuit may also include an active clamp and an isolated flyback section. | 01-20-2011 |
| 20110007574 | METHOD OF ERASING AN NVM CELL THAT UTILIZES A GATED DIODE - A method of erasing an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain regions defining an n-type channel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and rain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and separated therefrom by intervening dielectric material, the erasing method comprising: biasing the deep N-type well at a selected erase voltage; holding the source and drain regions of the PMOS transistor at the erase voltage or floating; and holding the control gate at ground for a preselected erase time. | 01-13-2011 |
| 20110007570 | METHOD OF READING AN NVM CELL THAT UTILIZES A GATED DIODE - A method of reading an NVM cell structure formed on a deep well of N-type semiconductor material, wherein the NVM cell structure includes a PMOS transistor formed in an N-type well, the PMOS transistor including spaced-apart p-type source and drain region defining an n-type cannel region therebetween, an NMOS transistor formed in a P-type well that is adjacent to the N-type well, the NMOS transistor including spaced-apart n-type source and drain regions defining a p-type channel region therebetween, a conductive floating gate that includes a first section that extends over the n-type channel region of the PMOS transistor and is separated therefrom by intervening dielectric material and a second section that extends over the p-type channel region and is separated therefrom by intervening dielectric material, and a conductive control gate formed over at least a portion of the second section of the floating gate and is separated therefrom by intervening dielectric material, the method comprising: biasing the deep N-type well at a preselected read voltage; holding the source region of the PMOS transistor at the read voltage; holding the drain of the PMOS transistor at ground; and holding the control gate at ground for a preselected read time. | 01-13-2011 |
| 20100327659 | SYSTEM AND METHOD FOR OVER-VOLTAGE PROTECTION OF A PHOTOVOLTAIC SYSTEM WITH DISTRIBUTED MAXIMUM POWER POINT TRACKING - A solar panel array for use in a solar cell power system is provided. The solar panel array includes a string of solar panels and multiple voltage converters. Each voltage converter is coupled to a corresponding solar panel in the string of solar panels. The solar panel array also includes multiple maximum power point tracking (MPPT) controllers. Each MPPT controller is coupled to a corresponding solar panel in the string of solar panels. Each MPPT controller is configured to sense an instantaneous power unbalance between the corresponding solar panel and an inverter. | 12-30-2010 |
| 20100321750 | METHOD AND SYSTEM FOR PROVIDING RESONANT FREQUENCY CHANGE COMPENSATION IN A DRIVE SIGNAL FOR A MEMS SCANNER - A method for providing feed forward compensation in a drive signal for a rapid resonant frequency change due to a rapid LASER intensity change upon a micro-electro-mechanical system (MEMS) mirror and/or a surrounding MEMS structure in a MEMS scanner causing a mirror temperature change is provided. The method includes determining an intensity factor for at least one laser beam projected onto the MEMS scanner and adjusting a drive frequency of the drive signal based on the intensity factor. The intensity could represent a single intensity factor for multiple laser beams projected onto the MEMS scanner. The method could also include delaying the adjustment of the drive frequency to allow the resonant frequency change to take affect in the MEMS scanner. Delaying the adjustment could include delaying delivery of the intensity factor such that the intensity factor is provided coincident with the resonant frequency change of the MEMS scanner. | 12-23-2010 |
| 20100301901 | UNIVERSAL TWO-INPUT LOGIC GATE THAT IS CONFIGURABLE AND CONNECTABLE IN AN INTEGRATED CIRCUIT BY A SINGLE MASK LAYER ADJUSTMENT - A spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs, and whose output is utilized as a logic gate output. Each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function. By modifying a single photolithographic mask, the spare logic gate can be: configured to perform the desired logic function; connected into a target logic circuit; or both configured and connected into a target logic circuit. | 12-02-2010 |
| 20100295638 | METHOD OF SWITCHING A MAGNETIC MEMS SWITCH - A MEMS magnetic flux switch is fabricated as a ferromagnetic core. The core includes a center cantilever that is fabricated as a free beam that can oscillate at a resonant frequency that is determined by its mechanical and material properties. The center cantilever is moved by impulses applied by an associated motion oscillator, which can be magnetic or electric actuators. | 11-25-2010 |
| 20100295550 | ADAPTIVE ENERGY MANAGEMENT TERMINAL FOR A BATTERY - A battery includes multiple conductive plates and a permeable electrolytic material and an ion membrane located between the conductive plates. The battery also includes at least one wire located within one or more of the permeable electrolytic material and the ion membrane. The at least one wire can be configured to regulate a flow of ions through the ion membrane based on an electrical signal flowing through the at least one wire. The at least one wire could also be configured to generate a magnetic field within the permeable electrolytic material based on another electrical signal flowing through the at least one wire. The battery could further include a temperature sensor wire within the permeable electrolytic material. | 11-25-2010 |
| 20100288327 | System and method for over-Voltage protection of a photovoltaic string with distributed maximum power point tracking - A string over-voltage protection system and method for arrays of photovoltaic panels. The system and method includes a device for use in a photovoltaic array power system. The device includes a voltage converter. The voltage converter is adapted to be coupled to a photovoltaic panel in a string of photovoltaic panels. The device also includes a string over-voltage protection circuit. The string over-voltage protection circuit is coupled to the voltage converter. The string over-voltage protection circuit senses a string voltage and determines if a string over-voltage condition exists. Additionally, the string over-voltage protection circuit is configured to disable the voltage converter in the event of a string over-voltage condition. | 11-18-2010 |
| 20100269883 | SYSTEM AND METHOD FOR OVER-VOLTAGE PROTECTION IN A PHOTOVOLTAIC SYSTEM - A photovoltaic array for use in an electrical power system includes multiple photovoltaic modules and a voltage converter coupled to at least one of the photovoltaic modules. The photovoltaic array also includes an over-voltage protection circuit. The over-voltage protection circuit includes an interface adapted to couple to an output of the voltage converter. The over-voltage protection circuit also includes a spike detector configured to detect a voltage spike in an output voltage of the voltage converter. The over-voltage protection circuit further includes a voltage control module configured to regulate an output voltage slew rate of the voltage converter in response to an over-voltage signal received from the spike detector. | 10-28-2010 |
| 20100259996 | System and method for providing low cost high endurance low voltage electrically erasable programmable read only memory - A system and method are disclosed for increasing the reliability of a channel erase procedure in an electrically erasable programmable read only memory (EEPROM) memory cell. A memory cell of the present invention comprises a program gate, a control gate, and a floating gate that erase data using a channel erase procedure. An erase capacitor is coupled to the floating gate to provide a low voltage bias that decreases the voltage that is required to perform a Fowler-Nordheim erase process in the memory cell. The erase capacitor of the present invention is formed without adding a step in the manufacturing process of the memory cell. Memory cells of the present invention are low cost, high endurance, low voltage memory cells. | 10-14-2010 |
| 20100238848 | Class-B transmitter and replica transmitter for gigabit ethernet applications - A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature. | 09-23-2010 |
| 20100237487 | METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS - Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable. | 09-23-2010 |
| 20100225386 | QUADRATURE SIGNAL DEMODULATOR CIRCUITRY SUITABLE FOR DOPPLER ULTRASOUND - Quadrature signal demodulator circuitry for demodulating multiple related input signals into respective pairs of quadrature signals for selective combining to provide a composite pair of quadrature signals with a maximized signal-to-noise ratio (SNR). | 09-09-2010 |
| 20100225352 | Integrated circuit with pin-selectable mode of operation and level-shift functionality and related apparatus, system, and method - An apparatus includes a digital interface circuit configured to provide a digital interface. The digital interface is configurable based on a mode of operation of the digital interface circuit. The apparatus also includes input and output level-shift circuits. The input level-shift circuit is configured to shift a voltage level of an input signal for the digital interface circuit. The output level-shift circuit is configured to shift a voltage level of an output signal from the digital interface circuit. The input level-shifting and the output level-shifting are based on first and second level-shift input voltages. The apparatus further includes a mode detector configured to identify at least two modes of operation for the digital interface circuit based on the first and second level-shift input voltages. For example, the digital interface circuit could be configured to function as a serial or parallel interface depending on which level-shift input voltage is greater. | 09-09-2010 |
| 20100216280 | INTEGRATED CIRCUIT MICRO-MODULE - Various methods for forming an integrated circuit micro-module are described. In one aspect of the invention, layers of an epoxy are sequentially deposited over a substrate to form planarized layers of epoxy over the substrate. The epoxy layers are deposited using spin coating. At least some of the layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. Openings are formed in at least some of the patterned epoxy layers after they are patterned and before the next epoxy layer is deposited. An integrated circuit is placed within one of the openings. At least one of the epoxy layers is deposited after the placement of the integrated circuit to cover the integrated circuit. At least one conductive interconnect layer is formed over an associated epoxy layer. Multiple external package contacts are formed. The integrated circuit is electrically connected with the external package contacts at least in part through one or more of the conductive interconnect layers. | 08-26-2010 |
| 20100215995 | MAGNETIC STATE OF CHARGE SENSOR FOR A BATTERY - A battery includes multiple conductive battery plates and a complex electrolytic material located between the conductive battery plates. The battery also includes a conductive sensor wire located within the complex electrolytic material. The conductive sensor wire may be configured to generate a magnetic field within the complex electrolytic material based on an electrical signal flowing through the conductive sensor wire. The battery may further include a temperature sensor wire within the complex electrolytic material. | 08-26-2010 |
| 20100213607 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a wafer level method for packaging micro-systems. A substrate prefabricated with metal vias can be provided. The substrate can also be made by forming holes in a substrate and electroplating an electrically conductive material into the holes to form the vias. Multiple Microsystems are formed on a top surface of the substrate. Each microsystem is formed to include multiple layers of planarizing, photo-imageable epoxy, one or more interconnect layers and an integrated circuit. Each interconnect layer is embedded in an associated epoxy layer. The integrated circuit is positioned within at least an associated epoxy layer. The interconnect layers of the Microsystems are formed such that at least some of the interconnect layers are electrically coupled with one or more of the metal vias in the substrate. Molding material is applied over the top surface of the substrate and the Microsystems to form a molded structure. Portions of the substrate can be removed. The molded structure can be singulated to form individual integrated circuit packages. Each of the integrated circuit packages contains at least one microsystem. Various embodiments involve forming conductive pads on the top surface of the substrate instead of the metal vias. | 08-26-2010 |
| 20100213604 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described. | 08-26-2010 |
| 20100213603 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to an integrated circuit package in which one or more integrated circuits are embedded in a substrate and covered with a layer of photo-imageable epoxy. The substrate can be made of various materials, including silicon, quartz and glass. An integrated circuit is positioned within a cavity in the top surface of the substrate. The epoxy layer is formed over the top surface of the substrate and the active face of the integrated circuit. An interconnect layer is formed over the epoxy layer and is electrically coupled with the integrated circuit. | 08-26-2010 |
| 20100213602 | INTEGRATED CIRCUIT MICRO-MODULE - Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. Various embodiments pertain to apparatuses that are formed by performing some or all of the aforementioned operations. | 08-26-2010 |
| 20100213601 | INTEGRATED CIRCUIT MICRO-MODULE - In one aspect, an integrated circuit package composed of a plurality of immediately adjacent stacked layers of cured, planarizing, photo-imageable dielectric is described. At least one interconnect layer is provided between a pair of adjacent dielectric layers. An integrated circuit is positioned within one or more of the dielectric layers such that at least one of the dielectric layers extends over the active surface of the integrated circuit. The integrated circuit is electrically coupled with I/O pads on a surface of the package at least in part through the interconnect layer or electrically conductive vias. In particular embodiments, the package can include thermal pipes, a heat sink, multiple integrated circuits, interconnect layers, conductive vias that electrically connect different components of the package and/or passive devices. In some specific embodiments, the dielectric layers are formed from a suitable epoxy such as SU-8 type. In a method aspect of the invention, the dielectric layers may be formed using a spin-on coating approach and patterned using conventional photolithographic techniques. | 08-26-2010 |
| 20100190316 | METHOD OF SELECTIVE OXYGEN IMPLANTATION TO DIELECTRICALLLY ISOLATE SEMICONDUCTOR DEVICES USING NO EXTRA MASKS - A method of fabricating integrated circuit structures utilizes selective oxygen implantation to dielectrically isolate semiconductor structures using no extra masks. Existing masks are utilized to introduce oxygen into bulk silicon with subsequent thermal oxide growth. Since the method uses bulk silicon, it is cheaper than silicon-on-insulator (SOI) techniques. It also results in bulk silicon that is latch-up immune. | 07-29-2010 |
| 20100164656 | INTEGRATED DIGITALLY CONTROLLED LINEAR-IN-DECIBELS ATTENUATOR - An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively. | 07-01-2010 |
| 20100157682 | METHOD OF ENHANCING CHARGE STORAGE IN AN E2PROM CELL - A method is provided for enhancing charge storage in an E | 06-24-2010 |
| 20100151614 | WAFER LEVEL METHOD OF FORMING SIDE FIBER INSERTION OPTOELECTRONIC PACKAGES - Optoelectronic packages and wafer level techniques for forming optoelectronic packages are described. In accordance with one apparatus aspect of the invention, a pair of substrates are bonded together to form an optical coupler. A first one of the substrates has a recess that faces the second substrate to at least in part define a channel suitable for receiving an optical transmission medium. A photonic device is mounted on a mounting surface of the second substrate that is opposite its bonded surface. The photonic device faces the reflective surface and an optical path is formed between the channel and the photonic element that both reflects off of the reflective surface and passes through the second substrate. In some embodiments an integrated circuit device and/or solder bumps are also attached to the mounting surface and the second substrate has conductive traces thereon that electrically couple the various electrical components as appropriate (e.g., the photonic device, the integrated circuit device, the solder bumps and/or other components). The substrates may be formed from a wide variety of materials including, glass, plastic and silicon. In some embodiments, at least the second substrate is formed from an optically transparent material and the optical path passes directly though the optically transparent material. In a method aspect of the invention, a variety of wafer level methods for forming such devices are described. | 06-17-2010 |
| 20100136749 | MICROARRAY PACKAGE WITH PLATED CONTACT PEDESTALS - A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 μm to about 35 μm. | 06-03-2010 |
| 20100127352 | SELF-ALIGNED BIPOLAR TRANSISTOR STRUCTURE - A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region. | 05-27-2010 |
| 20100117206 | MICROARRAY PACKAGE WITH PLATED CONTACT PEDESTALS - A microarray package includes a leadframe having an array of contact posts, a die carried by the lead frame, and a plurality of bonding wires that electrically connect the die to the lead frame. An encapsulant is included that encapsulates the die, the bonding wire and the leadframe while leaving the distal ends of the contact posts exposed and substantially co-planar with a bottom surface of the microarray package. A plurality of pedestal members is plated to the distal end of a respective contact pad. A distal surface of each pedestal member protrudes outwardly beyond the bottom surface of the microarray package in the range of about 15 μm to about 35 μm. | 05-13-2010 |
| 20100109167 | CONDUCTIVE PATHS FOR TRANSMITTING AN ELECTRICAL SIGNAL THROUGH AN ELECTRICAL CONNECTOR - The claimed invention relates to structures suitable for improving the performance and reliability of electrical connectors. One embodiment of the claimed invention includes an integrated circuit die having an electrical contact coupled with electrically conductive paths that share a common electrical source. The conductive paths are configured to transmit the same electrical signal to the electrical contact, which supports an electrical connector, such as a solder bump. The electrical connector couples the die with an outside component, such as a circuit board. Each of the conductive paths connect to the electrical contact at different interface locations. When the electrical signal passes through the interface locations, the paths are configured to have non-zero current densities at those locations. The electrical resistance of the conductive paths may be substantially similar. Thus, instead of being concentrated at a single point, current is more evenly distributed along the junction between the die and solder bump, which may reduce voiding and localized heating. | 05-06-2010 |
| 20100105325 | Plurality of Mobile Communication Devices for Performing Locally Collaborative Operations - A plurality of mobile communication devices for performing one or more locally collaborative operations. In one embodiment, one of the mobile communication devices provides a first local energy emission and, related thereto, a local wireless transmission signal, while another of the mobile communication devices responds to the local wireless transmission signal by providing a second local energy emission related to the first local energy emission. In another embodiment, one of the mobile communication devices receives a local stimulus, exclusive of vocal energy emitted by a user, and in response thereto provides a local wireless transmission signal, while another of the mobile communication devices responds to the local wireless transmission signal by providing a local energy emission related to the local stimulus. In another embodiment, each of the mobile communication devices receives a respective portion of a local stimulus in response to which at least one of the mobile communication devices transmits a local wireless transmission signal in response to which a second one of the mobile communication devices provides a local energy emission related to responses to the local stimulus in addition to its own. In additional embodiments, each of the mobile communication devices receives a respective portion of a local stimulus and in response thereto transmits a wireless transmission signal for collaboratively providing, to a remotely located system, information about the various responses to the local stimulus. | 04-29-2010 |
| 20100090876 | CONTINUOUS SYNCHRONIZATION FOR MULTIPLE ADCS - A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit. | 04-15-2010 |
| 20100084748 | THIN FOIL FOR USE IN PACKAGING INTEGRATED CIRCUITS - Methods for minimizing warpage of a welded foil carrier structure used in the packaging of integrated circuits are described. Portions of a metallic foil are ultrasonically welded to a carrier to form a foil carrier structure. The ultrasonic welding helps define a panel in the metallic foil that is suitable for packaging integrated circuits. Warpage of the thin foil can be limited in various ways. By way of example, an intermittent welding pattern that extends along the edges of the panel may be formed. Slots may be cut to define sections in the foil carrier structure. Materials for the metallic foil and the carrier may be selected to have similar coefficients of thermal expansion. An appropriate thickness for the metallic foil and the carrier may be selected, such that the warpage of the welded foil carrier structure is limited when the foil carrier structure is subjected to large increases in temperature. Foil carrier structures for use in the above methods are also described. | 04-08-2010 |
| 20100073215 | UNIFIED ARCHITECTURE FOR FOLDING ADC - A system, apparatus and method for a folding analog-to-digital converter (ADC) are described. The general architecture of the folding ADC includes an array ( | 03-25-2010 |
| 20100072613 | INKJET PRINTED LEADFRAME - Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays. | 03-25-2010 |
| 20100068864 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils. | 03-18-2010 |
| 20100068466 | METHODS AND ARRANGEMENTS FOR FORMING SOLDER JOINT CONNECTIONS - The present invention relates to methods and arrangements for forming a solder joint connection. One embodiment involves an improved solder ball. The solder ball includes a perforated, metallic shell with an internal opening. Solder material encases the shell and fills its internal opening. The solder ball may be applied to an electrical device, such as an integrated circuit die, to form a solder bump on the device. The solder bump in turn can be used to form an improved solder joint connection between the device and a suitable substrate, such as a printed circuit board. In some applications, a solder joint connection is formed without requiring the application of additional solder material to the surface of the substrate. The present invention also includes different solder bump arrangements and methods for using such arrangements to form solder joint connections between devices and substrates. | 03-18-2010 |
| 20100052725 | ADAPTIVE TEST TIME REDUCTION FOR WAFER-LEVEL TESTING - In a method for testing a plurality of consecutively indexed sites, a default test sequence is applied to the consecutively indexed sites until a first defective site is identified. If a first defective site is identified, then a more stringent test sequence is applied to a predefined number of sites subsequent to the first defective site. If the more stringent test sequence does not identify a second defective site in the predefined number of sites subsequent to the first defective site, then the default test sequence is resumed. | 03-04-2010 |
| 20100052123 | LOW STRESS CAVITY PACKAGE - The present invention relates to methods and arrangements for forming a low stress cavity package. Particular methods may be performed with existing packaging equipment. In one such method, a leadframe laminated with adhesive film is provided. Integrated circuit dice are connected to the leadframe by reflowing solder between bond pads on the active surface of each die and the leadframe. A viscous thermosetting material is dispensed around the periphery of the active surface of each die. The thermosetting material fills gaps between the solder joint connections and the adhesive film. As a result, the thermosetting material, solder joint connections, each integrated circuit die and the adhesive film define and seal a protective cavity between the active surface of the die and the adhesive film. Portions of each die, leads, solder joint connections and adhesive film are encapsulated with a molding material that is prevented from entering the sealed cavity. | 03-04-2010 |
| 20100046188 | THIN FOIL SEMICONDUCTOR PACKAGE - The present invention relates to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure, which includes a foil adhered to a carrier having cavities. Some methods of the present invention involve attaching dice to the foil and encapsulating the foil carrier structure in a molding material. In one embodiment, the molding material presses against the foil, which causes portions of the foil to distend into the cavities of the carrier. As a result, recessed and raised areas are formed in the foil. Afterwards, the carrier is removed and portions of the raised areas in the foil are removed through one of a variety of techniques, such as grinding. This process helps define and electrical isolate contact pads in the foil. The resulting molded foil structure may then be singulated into multiple semiconductor packages. | 02-25-2010 |
| 20100039840 | AC-TO-DC VOLTAGE CONVERSION AND CHARGING CIRCUITRY - Voltage conversion and charging circuitry and method for converting an alternating current (AC) voltage to a direct current (DC) voltage for charging an energy storage element (e.g., battery or supercapacitor). An output capacitance, which is initially charged quickly for use in the slower charging of a battery, also maintains the charge on an input capacitance which provides power for the charging control circuitry during such charging process. In accordance with a preferred embodiment, the DC charging current is substantially constant during a first time interval following which the DC charging power is substantially constant during a second time interval. | 02-18-2010 |
| 20100025818 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package is described that includes an integrated circuit die, a plurality of lower contact leads, and an insulating substrate positioned over the die and lower contact leads. The insulating substrate includes a plurality of electrically conducting upper routing traces formed on the bottom surface of the substrate. The traces on the bottom surface of the substrate electrically couple each lower contact lead with an associated I/O pad. | 02-04-2010 |
| 20100019339 | MOLDED OPTICAL PACKAGE WITH FIBER COUPLING FEATURE - Apparatuses and methods directed to an integrated circuit package having an optical component are disclosed. The package may include an integrated circuit die having at least one light sensitive region disposed on a first surface thereof. By way of example, the die may be a laser diode that emits light through the light sensitive region, or a photodetector that receives and detects light through the light sensitive region. An optical concentrator may be positioned adjacent the first surface of the first die. The optical concentrator includes a lens portion positioned adjacent the light sensitive region and adapted to focus light. | 01-28-2010 |
| 20100015329 | METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS WITH THIN METAL CONTACTS - Methods and arrangements are described for forming an array of contacts for use in packaging one or more integrated circuit devices. In particular, various methods are described for forming contacts having thicknesses less than approximately 10 μm, and in particular embodiments, between 0.5 to 2 μm. | 01-21-2010 |
| 20100006991 | PACKAGING INTEGRATED CIRCUITS FOR HIGH STRESS ENVIRONMENTS - One aspect of the invention pertains to a semiconductor package suitable for use in high stress environments, such as ones involving high pressures, temperatures and/or corrosive substances. In this aspect, a die and leadframe are fully encapsulated in a first plastic casing. The first plastic casing is fully encapsulated in turn with a second plastic casing. The two casings have different compositions. The first plastic casing, for example, may be made of a thermoset plastic material and the second plastic casing may be made of a thermoplastic material. The first plastic casing may have recesses, indentations and/or slots suitable for securing it to the second plastic casing. In some embodiments, a corrosion resistant coating is added to the second plastic casing. Methods for forming semiconductor packages suitable for use in high stress environments are also described. | 01-14-2010 |
| 20100001383 | INTEGRATED CIRCUIT PACKAGE WITH MOLDED INSULATION - A variety of improved arrangements and processes for packaging integrated circuits are described. More particularly, methods of encapsulating dice in lead frame based IC packages are described that facilitate covering some portions of the bottom surface of the lead frame while leaving other portions of the bottom surface of the lead frame exposed. In some embodiments, a method of encapsulating integrated circuits mounted on a lead frame panel is described. The lead frame panel includes a plurality of leads having associated contacts and supports. A shim having a plurality of cavities is positioned under the lead frame such that the cavities are adjacent to the supports and not adjacent to the contacts. During the encapsulation process, encapsulant material flows under the supports such that the bottom surfaces of the supports are electrically insulated by the encapsulant while the bottom surfaces of the contacts remain exposed. | 01-07-2010 |
| 20090315161 | DIE ATTACH METHOD AND LEADFRAME STRUCTURE - In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure). The width of at least some of these tailed lead traces in a region that overlies their associated contact post is narrower than their associated contact post. Thus, these narrowed lead traces have extensions that extend beyond their associated contact posts. The extensions provide additional surface area that gives an adhesive applied to the narrowed lead trace (as for example by stamping) room to bleed (flow) along the top surface of the lead trace on both sides of the associated contact pad. | 12-24-2009 |
| 20090309611 | CABLE DETECTOR - A cable detector includes one or more peak detectors that detect when a termination impedance is missing from the output of a line driver. A peak detection signal is asserted when signals on a transmission line exceed a threshold level. A fault condition is asserted when the peak detection signal is asserted for a sufficient length of time to indicate that an actual fault is detected. The time period required for detecting a lost or missing line termination is longer than the time periods for any one of the pathological conditions to avoid a false positive detection. After the peak detection signal is de-asserted, the fault condition will be maintained until another sufficient length of time has expired without a peak detection. | 12-17-2009 |
| 20090305076 | FOIL BASED SEMICONDUCTOR PACKAGE - The present inventions relate to methods and arrangements for using a thin foil to form electrical interconnects in an integrated circuit package. In one embodiment, a foil carrier structure is formed by ultrasonically bonding portions of a conductive foil to a metallic carrier. The bonded portions define panels in the foil carrier structure. In some embodiments, the foil carrier structure is cut to form multiple isolated panels that are sealed along their peripheries. Each isolated panel may be approximately the size of a conventional leadframe strip or panel. As a result, existing packaging equipment may be used to add dice, bonding wires and molding material to the panel. The ultrasonic welding helps prevent unwanted substances from penetrating the foil carrier structure during such processing steps. After the carrier portion of the molded foil carrier structure is removed, the structure is singulated into integrated circuit packages. Some embodiments relate to methods that utilize some or all of the aforementioned operations. Other embodiments relate to arrangements used in the above processes. | 12-10-2009 |
| 20090300558 | USE OF STATE NODES FOR EFFICIENT SIMULATION OF LARGE DIGITAL CIRCUITS AT THE TRANSISTOR LEVEL - A method is provided for simulating a sequential digital circuit module given a set of input conditions and a current state for the circuit. The method comprises initiating all state nodes of the circuit module to logic values stored in the current state, initializing all sequential submodules of the circuit module to the states stored in the current state, simulating the circuit module after initialization, and after completion of the simulation step, reporting the output logic values and associated delays and storing the logic values of the state nodes and the states of the sequential modules in the next state in the circuit module, multiple value changes in the state nodes of the circuit module being recorded on the next state. | 12-03-2009 |
| 20090296493 | MID-SIZE NVM CELL AND ARRAY UTILIZING GATED DIODE FOR LOW CURRENT PROGRAMMING - A method of operating a non-volatile memory (NVM) cell structure that utilizes gated diode is provided. The cell architecture, utilizing about 4-10 um2 per bit, includes gated diodes that are used to program the cells while consuming low programming current. The cell architecture also allows a large number of cells to be programmed at the same time, thereby reducing the effective programming time per bit. Erase and read mode bias conditions are also provided. | 12-03-2009 |
| 20090284998 | Method and system for providing maximum power point tracking in an energy generating system - A method for providing a maximum power point tracking (MPPT) process for an energy generating device is provided. The method includes coupling a local converter to the energy generating device. A determination is made regarding whether the local converter is operating at or below a maximum acceptable temperature. A determination is made regarding whether at least one current associated with the local converter is acceptable. When the local converter is determined to be operating at or below the maximum acceptable temperature and when the at least one current associated with the local converter is determined to be acceptable, the MPPT process is enabled within the local converter. | 11-19-2009 |
| 20090284240 | Method and system for providing local converters to provide maximum power point tracking in an energy generating system - A method for providing maximum power point tracking for an energy generating device using a local buck-boost converter coupled to the device is provided. The method includes operating in a tracking mode, which includes initializing a conversion ratio for the buck-boost converter based on a previous optimum conversion ratio. A device power associated with the initialized conversion ratio is calculated. The conversion ratio is repeatedly modified and a device power associated with each of the modified conversion ratios is calculated. A current optimum conversion ratio for the buck-boost converter is identified based on the calculated device powers. The current optimum conversion ratio corresponds to one of a buck mode, a boost mode and a buck-boost mode for the buck-boost converter. | 11-19-2009 |
| 20090284232 | Method and system for selecting between centralized and distributed maximum power point tracking in an energy generating system - A method for selecting between centralized and distributed maximum power point tracking in energy generating system is provided. The energy generating system includes a plurality of energy generating devices, each of which is coupled to a corresponding local converter. Each local converter includes a local controller for the corresponding energy generating device. The method includes determining whether the energy generating devices are operating under quasi-ideal conditions. The energy generating system is placed in a centralized maximum power point tracking (CMPPT) mode when the energy generating devices are operating under quasi-ideal conditions and is placed in a distributed maximum power point tracking (DMPPT) mode when the energy generating devices are not operating under quasi-ideal conditions. | 11-19-2009 |
| 20090284078 | System and method for integrating local maximum power point tracking into an energy generating system having centralized maximum power point tracking - A system for integrating local maximum power point tracking (MPPT) into an energy generating system having centralized MPPT is provided. The system includes a system control loop and a plurality of local control loops. The system control loop comprises a system operating frequency, and each local control loop comprises a corresponding local operating frequency. Each of the local operating frequencies is spaced apart from the system operating frequency by at least a predefined distance. For a particular embodiment, a settling time corresponding to the local operating frequency of each local control loop is at least five times faster than a time constant corresponding to the system operating frequency. | 11-19-2009 |
| 20090283129 | System and method for an array of intelligent inverters - A system and method for DC to AC conversion in a power generating array. The system and method includes a number of inverters coupled to a group of solar panels. A group controller coordinates operation of the inverters for interleaved switching of the inverters. The group controller communicates via a local area network, a wireless network, or both, to coordinate operation with additional groups of inverters coupled in parallel with additional solar panels. | 11-19-2009 |
| 20090283128 | Method and system for activating and deactivating an energy generating system - A method for activating a local converter for one of a plurality of energy generating devices in an energy generating array is provided. The local converter includes a power stage and a local controller. The method includes comparing a device voltage for the energy generating device to a voltage activation level. The local converter is automatically activated when the device voltage exceeds the voltage activation level. | 11-19-2009 |
| 20090267692 | DIGITALLY VARIABLE GAIN AMPLIFIER USING MULTIPLEXED GAIN BLOCKS - A digitally variable gain amplifier comprising a front-end stage, a level shifter stage, and an output amplifier stage. The front-end stage comprises a high gain pre-amplifier and a low gain pre-amplifier driven in parallel by a differential input signal. A coarse gain control is realized by enabling only one pre-amplifiers at a time, while the differential input signal remains connected to the inputs of the disabled pre-amplifier. An attenuator following each pre-amplifier provides fine gain control. The enabled pre-amplifier amplifies the differential input signal and outputs a first dc voltage level. The disabled pre-amplifier is placed into a standby ready mode and outputs a second dc voltage level that is greater in magnitude than the first dc voltage level. The level shifter stage performs a minimum voltage selection operation to automatically select and level shift the amplified differential input signal, and further pass the signal to the output amplifier stage. | 10-29-2009 |
| 20090267216 | INKJET PRINTED LEADFRAMES - Apparatuses and methods for inkjet printing electrical interconnect patterns such as leadframes for integrated circuit devices are disclosed. An apparatus for packaging includes a thin substrate adapted for high temperature processing, and an attach pad and contact regions that are inkjet printed to the thin substrate using a metallic nanoink. The nanoink is then cured to remove liquid content. The residual metallic leadframe or electrical interconnect pattern has a substantially consistent thickness of about 10 to 50 microns or less. An associated panel assembly includes a conductive substrate panel having multiple separate device arrays comprising numerous electrical interconnect patterns each, a plurality of integrated circuit devices mounted on the conductive substrate panel, and a molded cap that encapsulates the integrated circuit devices and associated electrical interconnect patterns. The molded cap is of substantially uniform thickness over each separate device array, and extends into the space between separate device arrays. | 10-29-2009 |
| 20090256960 | VIDEO TOP-OF-FRAME SIGNAL GENERATOR FOR MULTIPLE VIDEO FORMATS - A signal generator for use in producing a video top-of-frame signal based upon an input video signal with an input video frame including one or more input video fields and having an input video frame rate for an output video signal with an output video frame having a plurality of output video frame lines, each with a plurality of output video pixels, and an output video frame rate. | 10-15-2009 |
| 20090254872 | Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in - A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention. | 10-08-2009 |
| 20090251215 | AMPLIFIER OUTPUT STAGE WITH EXTENDED OPERATING RANGE AND REDUCED QUIESCENT CURRENT - An output stage of an amplifier circuit includes one or more output transistors that are selectively driven by a boosted drive circuit, where the boosted drive circuit is arranged such that the output range of the amplifier circuit is increased while maintaining reduced quiescent current. The drive signal to each output transistor is selectively increased only when demanded by the output load conditions. The threshold for boosting the drive signal can be adjusted for optimized performance. In one example, a class AB output stage includes a separate drive boost circuit for each output transistor. For this example, each drive boost circuit has a separate threshold for boosting each of the drive signals to the output transistors. The boosting can also be adjusted to optimize the differential input stage and current mirror maximum current requirement while maintaining minimum required bias currents. | 10-08-2009 |
| 20090212382 | OPTICAL LEADLESS LEADFRAME PACKAGE - Apparatuses and methods directed to a semiconductor chip package having an optical component are disclosed. Packages include a die having a light sensing region and a stress buffer on a first surface, a first opaque encapsulant having an opening therethrough disposed atop the first surface, and a second transparent or translucent encapsulant formed within the first encapsulant opening and directly atop and contacting the light sensing region. A leadless leadframe or other conductive component can be coupled to a second surface of the die. The die may also have light sensitive regions that are shielded by the first encapsulant and/or stress buffer. The stress buffer can be a layer formed at the wafer stage or a dam formed at the panel stage. A customized mold is used while dispensing the first encapsulant such that the opening therethrough is properly formed. | 08-27-2009 |
| 20090201086 | Current sense amplifier with extended common mode voltage range - A circuit includes an input stage configured to receive and amplify an input signal to produce an amplified signal, where the input signal is referenced to a higher voltage and is associated with a common mode voltage. The circuit also includes level shifter resistors configured to level shift the amplified signal to produce a shifted signal. The level shifter resistors are configured to provide a voltage drop so that the shifted signal is referenced to a lower voltage. The input stage may include multiple transistors floating in one or more isolated portions of a substrate, where the transistors perform amplification in the input stage. The circuit may also include circuitry configured to control current through the level shifter resistors so that the voltage drop depends on the common mode voltage of the input signal. In addition, the lower voltage may be between supply rails of the circuit. | 08-13-2009 |
| 20090195700 | LASER DIODE / LED DRIVE CIRCUIT - The invention relates to an apparatus for controlling the output of an LD or LED. The apparatus includes a substantially static bias source and a variable source. The substantially static bias source provides a bias current to the LD/LED. The variable source is capacitively coupled to the LD/LED. The bias current may be provided such that it is higher than a threshold current at which, when provided to an LD, lasing occurs. | 08-06-2009 |
| 20090194868 | PANEL LEVEL METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS WITH INTEGRATED HEAT SINKS - Panel level methods and arrangements are described for attaching heat sinks in panel form with dice attached to a leadframe panel. Various methods produce integrated circuit packages each having an exposed heat sink on one outer surface of the package and an exposed die attach pad on a second opposite surface of the package. | 08-06-2009 |
| 20090189279 | METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS - Methods of packaging integrated circuits are described. One method relates to attaching a singulated device wafer to a substrate. The singulated device wafer includes a multiplicity of integrated circuit dice arranged in a first configuration. The method also involves a substrate, which includes a sacrificial semiconductor wafer having device areas with metalized contacts. The device areas on the substrate may be arranged in a configuration matching that of the dice on the device wafer. The method also entails aligning the singulated device wafer as a whole with the substrate so that the dice of the device wafer are positioned substantially simultaneously over associated device areas on the substrate. The method also involves attaching the dice from the singulated wafer as a whole substantially simultaneously to the substrate such that each die of the device wafer is attached to an associated device area of the substrate. | 07-30-2009 |
| 20090174069 | I/O PAD STRUCTURE FOR ENHANCING SOLDER JOINT RELIABILITY IN INTEGRATED CIRCUIT DEVICES - A semiconductor device is described. The device includes an integrated circuit die having an active surface that includes a plurality of input/output (I/O) pads. The device further includes a plurality of crack resistant structures. Each crack resistant structure is formed over an associated I/O pad and includes an associated raised portion. Each I/O pad may be bumped with solder such that a solder bump is formed over the associated crack resistant structure on the I/O pad. | 07-09-2009 |
| 20090160067 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package is described that includes two dice. The active surface of each die includes a plurality of I/O pads. The active surface of the first die is positioned adjacent first surfaces of the leads of a leadframe such that I/O pads from the first die are arranged adjacent corresponding solder pad surfaces on the first surfaces. Similarly, the active surface of the second die is positioned adjacent second surfaces of the leads opposite the first surfaces such that I/O pads from the second die are arranged adjacent corresponding solder pad surfaces on the second surfaces. A plurality of solder joints are arranged to physically and electrically connect I/O pads from the first or second die to associated adjacent solder pad surfaces on the leads. In this way, a single leadframe can be utilized to package two dice, one on either side of the leads of the leadframe. | 06-25-2009 |
| 20090160039 | METHOD AND LEADFRAME FOR PACKAGING INTEGRATED CIRCUITS - A leadframe suitable for use in the packaging of at least two integrated circuit dice into a single integrated circuit package is described. The leadframe includes a plurality of leads. Each of a first set of the plurality of leads has a first side and a second side substantially opposite the first side of the lead. Additionally, each of the first and second sides of the first set of leads each include at least two solder pads. Each solder pad on a lead of the first set of leads is isolated from other solder pads on the same side of the lead with at least one recessed region adjacent the solder pad. In various embodiments, I/O pads from at least two dice are physically and electrically connected to the opposing sides of the leads. | 06-25-2009 |
| 20090160037 | METHOD OF PACKAGING INTEGRATED CIRCUITS - A method of packaging an integrated circuit die having a plurality of I/O pads is described. The method includes positioning the die within a die attach area of a first leadframe that includes a plurality of first leads. The method also includes positioning a second leadframe that includes a plurality of second leads over the first leadframe. The method further includes electrically connecting each of the second leads to both an associated I/O pad and a first lead. | 06-25-2009 |
| 20090152707 | METHODS AND SYSTEMS FOR PACKAGING INTEGRATED CIRCUITS - Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts. Dice are mounted onto each device area and electrically connected to the array of contacts. The surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including saw street structures, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable. | 06-18-2009 |
| 20090152691 | LEADFRAME HAVING DIE ATTACH PAD WITH DELAMINATION AND CRACK-ARRESTING FEATURES - One aspect of the invention pertains to a semiconductor package having a die and a die attach pad with a plurality of spaced apart pedestals supported by a web. A die is mounted on the die attach pad such that the die is supported by at least a plurality of the pedestals. Selected edge regions of the die are arranged to overlie recessed regions of the die attach pad between adjacent pedestals. The die is electrically connected to at least some of the contact leads. An adhesive is arranged to secure the die to the die attach pad, with the thickness of the adhesive between the web of the die attach pad and the die being greater than the thickness of the adhesive between the die and the top surfaces of the pedestals that support the die. The die attach pad may have rounded peripheral corners between adjacent edge surfaces of the die attach pad. In another aspect of the invention, a method of packaging integrated circuits is described, wherein the resulting packages include at least some of the aforementioned leadframe structures. | 06-18-2009 |
| 20090152683 | ROUNDED DIE CONFIGURATION FOR STRESS MINIMIZATION AND ENHANCED THERMO-MECHANICAL RELIABILITY - One aspect of the invention pertains to a semiconductor die with rounded sidewall junction edge corners. Such rounding reduces stress accumulations at those corners. In other embodiments of the invention, the sharpness of other corners and edges in the die are reduced. For example, reducing the sharpness of the bottom edge corners formed by the intersection of a sidewall and the back surface of a die can further diminish stress accumulations. One embodiment pertains to a wafer carried on a wafer support, where the wafer includes a multiplicity of such dice. Another embodiment involves a semiconductor package containing such dice. Methods of fabricating the dice are also described. | 06-18-2009 |
| 20090147708 | TIME SHARED BI-DIRECTIONAL SERIAL SIGNALING SYSTEM - A time shared bi-directional serial signaling system providing a differential signal with apparent duplex signal operation for higher and lower bandwidth data signals in a forward direction and another lower bandwidth data signal in a return direction. | 06-11-2009 |
| 20090141413 | INTEGRATED ELECTROSTATIC DISCHARGE (ESD) PROTECTION CIRCUITRY FOR SIGNAL ELECTRODE - An integrated electrostatic discharge (ESD) protection circuitry for a signal electrode. Coupled in shunt between the signal electrode and the positive and negative power supply electrodes are opposing sets of multiple diodes coupled in series. Each set includes a diode across which is applied a nominal reverse bias voltage These opposing reverse bias voltages are maintained at substantially constant predetermined nominal magnitudes in relation to the voltage at the signal electrode, thereby ensuring minimal leakage current via the signal electrode over the full dynamic range of the signal. | 06-04-2009 |
| 20090129786 | COUPLING OF OPTICAL INTERCONNECT WITH ELECTRICAL DEVICE - One embodiment of the present invention includes a flexible interconnect assembly that can convert between optical and electrical signals and that is configured to be easily secured to an electrical device, such as a printed circuit board or integrated circuit chip. The flexible interconnect assembly includes a flexible substrate and one or more optical waveguides that are mounted on the flexible interconnect and suitable for transmitting optical signals. One or more conversion devices for converting between electrical and optical signals are arranged on the flexible substrate. The flexible interconnect assembly optionally includes an attachment fixture that enables the flexible substrate to be reversibly coupled to an attachment apparatus. Particular embodiments of the present invention involve methods, devices and systems for using a flexible interconnect assembly with one or more electronic substrates configured with an attachment apparatus. | 05-21-2009 |
| 20090123257 | WAFFLE PACK - An arrangement is described that includes a compartmentalized structure having a multiplicity of compartments defined by associated links and each having a bottom surface. The arrangement also includes a multiplicity of fiducials. The fiducials are positioned at top surfaces of the links that surround each compartment such that each compartment includes at least one associated fiducial at the top surface of an adjacent link that defines the compartment. The arrangement further includes an adhesive layer positioned on the bottom surface of each compartment. The at least one fiducial that surrounds each compartment is suitable for use by a vision system to identify the location of the associated compartment. | 05-14-2009 |
| 20090115517 | APPARATUS AND METHOD FOR LOW POWER RAIL-TO-RAIL OPERATIONAL AMPLIFIER - A rail-to-rail amplifier is provided. The rail-to-rail amplifier includes a p-type differential pair, an n-type differential pair, switches, and an output stage. The switches are arranged to selectively couple either the p-type differential pair or the n-type differential pair to the output stage so that only one of the differential pairs is coupled to the output stage at a time. | 05-07-2009 |
| 20090115037 | INTEGRATED CIRCUIT PACKAGE WITH INTEGRATED HEAT SINK - An IC package and methods for making the same are described. The IC package includes a die and a heat sink that is attached to the back surface of the die with a thermal interface material layer. The heat sink includes a base and a partition. The partition extends around the periphery of the base and is offset from the outer edge of the base such that a ledge region is formed that surrounds the periphery of the base. The inner surfaces of the partition define an inner region that includes heat dissipation structures. A molding material encapsulates at least portions of the die and the ledge region around the periphery of the heat sink while leaving the inner region of the heat sink unencapsulated by molding material and exposed. The molding material covering the ledge region provides a locking feature that secures the heat sink in the package. | 05-07-2009 |
| 20090115035 | INTEGRATED CIRCUIT PACKAGE - Integrated circuit (IC) packages are described. Each IC package includes a die having an exposed metallic layer deposited on its back surface. Solder joints are arranged to physically and electrically connect I/O pads on the active surface of the die with associated leads. A molding material encapsulates portions of the die, leadframe and solder joint connections while leaving the metallic layer exposed and uncovered by molding material. | 05-07-2009 |
| 20090108907 | SIGNAL DETECTOR OUTPUT FOR CABLE DRIVER APPLICATIONS - The present disclosure relates to a system, apparatus and method for a line driver circuit to generate a signal detect (SD) signal when an invalid data signal is detected at its input. An invalid signal may be present either when no signal is available or when the line driver circuit or another component in the system (e.g., a crosspoint switch, a multiplexer, etc.) fails. The SD signal is coupled to an external controller that can either power down the line driver circuit to save power when no signal is available, or change over to a different line driver circuit or other component of the system when a failure is identified. When the input signal is determined to be a valid data signal via the SD signal, the line driver circuit can be enabled for operation. The described systems, apparatus and methods can save the user from having to directly control the line driver power state, especially in systems with large router configurations that may include hundreds of line drivers. | 04-30-2009 |
| 20090108906 | CABLE DRIVER USING SIGNAL DETECT TO CONTROL INPUT STAGE OFFSET - A system, apparatus and method are arranged for monitoring an input signal for a line driver and determining if a valid data signal is present. When the input signal is determined to be an invalid data signal, an offset is introduced into the input stage of the line driver to prevent noise induced toggling of the output of the line driver. When the input signal is determined to be a valid data signal, the offset is removed from the input stage since inclusion of the offset can introduce undesirable duty cycle distortion in the output of the line driver. By dynamically adding or removing the offset from the input stage of the line driver, invalid signals are prevented from toggling the output of the line driver while preserving a clean data transmission for valid signals. | 04-30-2009 |
| 20090091016 | I/O PAD STRUCTURES FOR INTEGRATED CIRCUIT DEVICES - A semiconductor device, including methods and arrangements for making the same, are described. The device includes an integrated circuit die having a plurality of bond pads. At least one bond pad on the active surface of the die is an extended I/O pad. Each extended I/O pad extends to at least one peripheral side edge of the die. | 04-09-2009 |
| 20090072931 | Integrated Digitally Controlled Linear-in-Decibels Attenuator - An integrated digitally controlled linear-in-decibels attenuator circuit in which one or more sets of selection switches establish a desired attenuation by selectively connecting the input signal electrode to one or more corresponding resistive ladder networks connected in series, thereby providing a substantially more constant signal attenuation value over a wider frequency bandwidth. With a single resistive ladder network, attenuation control is achieved using a thermometer switching code. With multiple resistive ladder networks, coarse and fine attenuation control can be achieved using thermometer and bubble switching codes, respectively. | 03-19-2009 |
| 20090072367 | LEADFRAME - Particular embodiments of the present invention provide a leadframe suitable for use in packaging IC dice that enables stress reduction in and around the die, die attach material, die attach pad and mold interfaces. More particularly, various leadframes are described that include recesses in selected regions of the top surface of the die attach pad. | 03-19-2009 |
| 20090045860 | Apparatus and method for two tier output stage for switching devices - A circuit for reducing EMI is provided. The circuit includes driver circuitry that drives a power switch, such as a power MOSFET. The power switch provides an output voltage. The circuit decreases the drive strength by which the power switch is driven during each output edge (i.e. when the output goes from low to high (rising edge) or high to low (falling edge)), and returns the drive strength to its normal level when the output edge is complete or approximately complete. Reducing the drive strength of the driver circuitry causes the output edge to occur over a longer period of time. This results in reduction of the EMI of the device. | 02-19-2009 |
| 20090045848 | PHASE-FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE - A phase-frequency detection system and method for enhancing performance of the frequency detector in a phase-frequency detection system. Filtering of the frequency detector inputs makes operation of the frequency detector more robust in the presence of intersymbol interference within the incoming data signal and other non-ideal characteristics such as noise and crosstalk. | 02-19-2009 |
| 20090044034 | Power Control and Status Circuitry for Communicating Power on Reset Control and Status Via a Single Electrode - A system and method providing, via a single output electrode of an integrated circuit having internal circuitry, a status signal having time multiplexed states indicative of a power on reset condition for external circuitry following enablement of operations of portions of the internal circuitry, and further indicative of subsequent operation statuses of the internal circuitry portions. | 02-12-2009 |
| 20090040000 | INTEGRATED CIRCUITS WITH INDUCTORS - The claimed invention relates to arrangements of inductors and integrated circuit dice. One embodiment pertains to an integrated circuit die that has an inductor formed thereon. The inductor includes an inductor winding having a winding input and a winding output. The inductor also comprises an inductor core array having at least first and second sets of inductor core elements that are magnetically coupled with the inductor winding. Each inductor core element in the first set of inductor core elements is formed from a first metallic material. Each inductor core element in the second set of inductor core elements is formed from a second metallic material that has a different magnetic coercivity than the first magnetic material. The inductor further comprises a set of spacers that electrically isolate the inductor core elements. Some embodiments involve multiple inductor windings and/or multiple inductor core elements that magnetically interact in various ways. Particular embodiments involve core elements having different compositions and/or sizes. | 02-12-2009 |
| 20090038142 | METHODS OF FORMING INDUCTORS ON INTEGRATED CIRCUITS - The claimed invention pertains to methods of forming one or more inductors on a semiconductor substrate. In one embodiment, a method of forming an array of inductor core elements on a semiconductor substrate that includes integrated circuits is disclosed. A first set of spaced apart metallic core elements are formed over the substrate. Isolation sidewalls are then formed on side surfaces of the core elements. Afterward, a second set of metallic core elements are formed over the substrate. In some embodiments, at least one core element of the second set of core elements is positioned in a space between an associated adjacent pair of core elements from the first set of core elements. The first and second sets of core elements are substantially co-planar and interleaved such that only the isolation sidewalls separate adjacent core elements. Particular embodiments involve other processing operations, such as the forming of a metal seed layer, the deposition and patterning of photoresist, the selective electroplating of different types of metal to form core elements and/or the deposition and etching away of an isolation layer to form isolation sidewalls on the core elements. | 02-12-2009 |
| 20090033421 | DIFFERENTIAL INPUT DRIVER USING CURRENT FEEDBACK AND CROSS-COUPLED COMMON BASE DEVICES - A differential input driver circuit ( | 02-05-2009 |
| 20090026590 | LEADFRAME PANEL - An improved leadframe panel suitable for use in packaging IC dice is described. The described leadframe panel is configured such that the amount of leadframe material that is removed during singulation of the leadframe panel is reduced. | 01-29-2009 |
| 20090016090 | Synchronous Rectifier and Controller for Inductive Coupling - A synchronous rectifier is arranged to rectify inductively coupled power using FETs (field effect transistors) to minimize the voltage drop of the rectifier, which minimizes power loss. Power loss is an important consideration in applications where fairly significant power is coupled to a device (such as a battery charger or other energy storage device) for a fairly short time (such as less than one hour) at a fairly low voltage (such as around 2.5 to 4.5 volts). Body diodes of the FETs can be used to supply power for bootstrapping and control logic for controlling the FETs. | 01-15-2009 |
| 20080303836 | VIDEO DISPLAY DRIVER WITH PARTIAL MEMORY CONTROL - Partial memory control for a video display driver in which data storage is provided for storing and providing a plurality of video pixel data having selectable ones of a plurality of pixel color depths to be displayed by a plurality of video displays having a plurality of mutually distinct dimensions. | 12-11-2008 |
| 20080303767 | VIDEO DISPLAY DRIVER WITH GAMMA CONTROL - Voltage generator circuitry for providing a plurality of voltages for use in gamma compensation of a video signal. | 12-11-2008 |
| 20080303750 | VIDEO DISPLAY DRIVER WITH DATA ENABLE LEARNING - Data enable learning is provided for a video display driver in which a data enable signal and pixel clock exclusive of their associated horizontal and vertical synchronization signals for a digital video signal are used to facilitate generating of signals corresponding to the associated horizontal and vertical synchronization signals. | 12-11-2008 |
| 20080297386 | SIGMA-DELTA MODULATOR WITH DAC RESOLUTION LESS THAN ADC RESOLUTION - A sigma-delta modulator is provided with a feedback digital-to-analog converter having less resolution than the quantizer, while providing a reduced length output word, requiring minimal additional internal processing, and shaping of the truncation error by an effective noise transfer function greater than the order of the host sigma-delta modulator. | 12-04-2008 |
| 20080290949 | APPARATUS AND METHOD FOR ASYMMETRIC CHARGE PUMP FOR AN AUDIO AMPLIFIER - An audio amplifier with an integrated asymmetric charge pump is provided. The audio amplifier receives VDD and VSS as power supply signals. The integrated charge pump is arranged to provide VSS from VDD, such that VSS is a negative voltage that is lower in magnitude than VDD. | 11-27-2008 |
| 20080290907 | THRESHOLD CONTROL CIRCUITRY FOR MULTIPLE CURRENT SIGNAL RECEIVERS - Calibration circuitry and method for maintaining constant signal detection thresholds for multiple signal receivers that receive data signals in the form of current signals. A value of one of the incoming current signals having a predetermined signal pattern is detected and used to generate threshold control signals for each of the signal receivers to control the data signal detection thresholds. | 11-27-2008 |
| 20080290482 | METHOD OF PACKAGING INTEGRATED CIRCUITS - A method of packaging integrated circuit dice into exposed die packages is described. The method includes depositing a metallic layer onto the back surface of an integrated circuit wafer such that it covers the back surface. The method additionally includes applying a protective layer over the metallic layer such that the protective layer covers the metallic layer. The method further includes singulating the wafer to produce individual dice. Each die may then be electrically connected to a lead frame. The die and portions of the lead frame may then be encapsulated with a molding compound. The protective layer inhibits the molding compound from contacting the metallic layer on the back surface of the die. The protective layer is then removed from the metallic layer. As a result, an individual IC package is produced that includes a die having a metallic layer exposed on the back surface of the die. | 11-27-2008 |
| 20080284514 | DIFFERENTIAL AMPLIFIER WITH MULTIPLE SIGNAL GAINS AND WIDE DYNAMIC RANGE - A circuit and method for amplifying a differential input signal over a wide dynamic range using multiple signal gains such that, over a predetermined range of values of the differential input signal, a ratio of the differential output signal to the differential input signal varies in relation to a continuous combination of the multiple signal gains. | 11-20-2008 |
| 20080284405 | Enhanced Cascode Performance By Reduced Impact Ionization - The conventional cascode circuit can be improved by adding another transistor in series. The added transistor may use the body effect to reduce supply voltage variations across the cascode transistor as the supply voltage varies. The added transistor reduces impact ionization in the cascode transistor. | 11-20-2008 |
| 20080279397 | MICROPHONE MADE FROM A POLYMER WAVEGUIDE - An apparatus and method for making a microphone that is not susceptible to RF noise and that can be fabricated to be very thin. The microphone includes a light transmitter configured to generate light, a waveguide having optically aligned transmit, vibrating and receive sections, and a receiver. Light from the transmitter is configured to be transmitted through the transmit section, vibrating section and the receive section of the waveguide, and to the receiver. The vibrating section of the waveguide is configured to vibrate in response to received acoustic energy, so that the light received by the receive section is modulated in proportion to the acoustic energy. In response, the receiver converts the modulated light to an electrical signal that is indicative of the received acoustic energy. Since the microphone of the present invention uses a thin waveguide to modulate the acoustic energy, it is not susceptible to RF noise, and it can be made to have a very thin profile. | 11-13-2008 |
| 20080278357 | Data Conversion Diagnostic Bit In A Data Converter - A data converter ( | 11-13-2008 |
| 20080278280 | Termination Compensation for Differential Signals on Glass - A system for calibrating operation of integrated differential signal receiver circuitry mounted on a substrate and coupled via surface conductors to edge mounted interface electrodes in which compensation is provided for variances among the resistances of the surface conductors. | 11-13-2008 |
| 20080273019 | SHADOW DETECTION IN OPTICAL TOUCH SENSOR THROUGH THE LINEAR COMBINATION OF OPTICAL BEAMS AND GREY-SCALE DETERMINATION OF DETECTED SHADOW EDGES - An optical based input touch display device with high resolution shadow detection using the linear splitting of waveguides among transmit and receive lenses and grey-scale calculations for shadow edge and center detection is disclosed. The apparatus includes a light source and a transmit waveguide optically coupled to the light source. The transmit waveguide includes a plurality of transmit waveguide grooves coupled to a plurality of groups of shared transmit lenses respectively. The plurality of groups of transit lenses, which are configured to generate a plurality of collimated light beams from the light source. A receive waveguide is also provided having a plurality of receive waveguide grooves coupled to a plurality of groups of shared receive lenses. The plurality of groups of receive lenses are configured to receive the plurality of collimated light beams. A photodiode array including a plurality of photodiodes are optically coupled to the plurality of receive waveguide grooves respectively. Each of the photodiodes is configured to receive light from the plurality of light beams received by the plurality of groups of receive lenses respectively. A processor is configured to detect shadow edge and/or shadow center of an interrupt in the plurality of collimated light beams. | 11-06-2008 |
| 20080266463 | STACKED DIFFERENTIAL SIGNAL TRANSMISSION CIRCUITRY - Differential signal transmission circuitry in which multiple differential signal transmission circuits are coupled in a stacked relationship between the power supply electrodes to minimize power dissipation by reusing the signal currents among the channels. | 10-30-2008 |
| 20080252378 | Gain Adjustment for Programmable Gain Amplifiers - A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit. | 10-16-2008 |
| 20080242003 | INTEGRATED CIRCUIT DEVICES WITH INTEGRAL HEAT SINKS - A method for forming integral heat sinks on back surfaces of integrated circuit devices at wafer level is described. A first metallic layer is deposited over the back surface of a wafer. A second metallic layer is deposited over the first metallic layer. Optionally, a third metallic layer is deposited over the second metallic layer. The first metallic layer, the second metallic layer, and optionally the third metallic layer form the integral heat sink for the wafer. When the wafer is diced into multiple semiconductor devices, each semiconductor device has an integral heat sink formed on its back surface that includes the first metallic layer, the second metallic layer, and optionally the third metallic layer. Optionally, each semiconductor device is connected to a lead frame via solder bumps or bonding wires to form an integrated circuit (IC) package. | 10-02-2008 |
| 20080232606 | SYNCHRONOUS DETECTION AND CALIBRATION SYSTEM AND METHOD FOR DIFFERENTIAL ACOUSTIC SENSORS - A synchronous detection and calibration system is provided for expedient calibration of differential acoustic sensors in a manufacturing and testing environment. By processing a series of sequentially received tones, respective portions of a system using differential acoustic sensors are tuned for optimum individual operation, following which corresponding control data are generated and stored for use in selecting among predetermined calibration vectors which establish and maintain optimum system operation. | 09-25-2008 |
