| National Chip Implementation Center National Applied Research Laboratories Patent applications |
| Patent application number | Title | Published |
|---|
| 20120102254 | Virtualized Peripheral Hardware Platform System - The present invention discloses a virtualized peripheral hardware platform system. The virtualized peripheral hardware platform system includes a first hardware platform and a software platform, which is executed in a second hardware platform. The first hardware platform is in signal communication with the second hardware platform. The software platform not only simulates the operation of the peripheral device of the first hardware platform but also simulates input signals of virtual peripheral devices and then transmits the input signals to the first hardware platform to conduct further calculations. Furthermore, the input/output (I/O) interface of the second hardware platform can be simulated as the I/O interface of the first hardware platform, so as to decrease the number of the I/O interface which the first hardware platform needed and downsize the first hardware platform. | 04-26-2012 |
| 20110282831 | DEVICE INCLUDING A VIRTUAL DRIVE SYSTEM - A device including a virtual drive system is provided. An image file can be identified as an ordinary physical disk drive via the device. The device includes a storage unit, an image management unit, and an operating-system interface. The storage unit is configured to store at least one image file. The image management unit includes an image management program which can manage the image files to be selected. The operating-system interface is connected by electrical signals with an operating-system apparatus and is controlled by the image management program to send a controlling signal to the operating-system apparatus. Therefore, the operating-system apparatus can identify as many physical disk drives as the corresponding selected image files. | 11-17-2011 |
| 20110188210 | THREE-DIMENSIONAL SOC STRUCTURE FORMED BY STACKING MULTIPLE CHIP MODULES - A three-dimensional SoC structure formed by stacking multiple chip modules is provided. The three-dimensional SoC structure includes at least two vertical SoC modules and at least one connector module, wherein each connector module electrically connects two vertical SoC modules. Each vertical SoC module is constructed by stacking at least two chip modules vertically. Each chip module includes a module circuit board and at least one preset element. A recess is formed in each module circuit board and provided with a first connecting interface for electrically connecting with the corresponding at least one preset element. The at least two vertical SoC modules are connected by the connector module to form a three-dimensional SoC structure with multiple functions. Besides, the recesses formed in the module circuit boards provide effective heat dissipation paths for the preset elements. | 08-04-2011 |
| 20110181245 | UNITIZED CHARGING AND DISCHARGING BATTERY MANAGEMENT SYSTEM AND PROGRAMMABLE BATTERY MANAGEMENT MODULE THEREOF - The present invention discloses a unitized charging and discharging battery management system and a programmable battery management module thereof The unitized charging and discharging battery management system includes a smart battery module and a programmable battery management module, which has a universal loop and a control unit. The smart battery module has at least two smart batteries which are electrically connected by a plurality of switches and circuits of the universal loop to form a charging/discharging loop in series/parallel. The control unit monitors the charging and discharging status of the smart batteries to turn on or off the switches accordingly, so as to manage the smart batteries, thereby enhancing the overall power efficacy of the smart battery module. Besides, the service life of the smart battery module is also prolonged due to the simultaneous charging and discharging capability. | 07-28-2011 |
| 20110169056 | HYDROGEN ION-SENSITIVE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A hydrogen ion-sensitive field effect transistor and a manufacturing method thereof are provided. The hydrogen ion-sensitive field effect transistor includes a semiconductor substrate, an insulating layer, a transistor gate, and a sensing film. A gate area is defined on the semiconductor substrate having a source area and a drain area. The insulating layer is formed within the gate area on the semiconductor substrate. The transistor gate is deposited within the gate area and includes a first gate layer. Further, the first gate layer is an aluminum layer, and a sensing window is defined thereon. The sensing film is an alumina film formed within the sensing window by oxidizing the first gate layer. Thus, the sensing film is formed without any film deposition process, and consequently the manufacturing method is simplified. | 07-14-2011 |
| 20110138248 | METHOD FOR ARRANGING MEMORIES OF LOW-COMPLEXITY LDPC DECODER AND LOW-COMPLEXITY LDPC DECODER USING THE SAME - A method for arranging memories of a low-complexity low-density parity-check (LDPC) decoder and a low-complexity LDPC decoder using the same method are provided. The main idea of the method for arranging memories of a low-complexity LDPC decoder is to merge at least one or two small-capacity memory blocks into one memory group, so that the memory area can be reduced and the power consumption in reading or writing data is lowered. Besides, as the merged memory group shares the same address line in reading or writing data, at least one delay unit is used to adjust the reading or writing order and thereby ensure data validity. A low-complexity LDPC decoder using the disclosed method can meet the demands of high processing rate and low power consumption. | 06-09-2011 |
| 20110133256 | CMOS-MEMS Cantilever Structure - The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity. | 06-09-2011 |
| 20110117747 | METHOD OF FABRICATING SINGLE CHIP FOR INTEGRATING FIELD-EFFECT TRANSISTOR INTO MEMS STRUCTURE - A method of fabricating a single chip for integrating a field-effect transistor into a microelectromechanical systems (MEMS) structure is provided. The method includes the steps of: providing a substrate having thereon at least one transistor structure, a MEMS structure and a blocking structure, wherein the blocking structure encircles the MEMS structure to separate the MEMS structure from the transistor structure; forming a masking layer for covering the transistor structure, the MEMS structure and the blocking structure; forming a patterned photoresist layer on the masking layer; performing a first etching process by using the patterned photoresist layer to remove the masking layer on the MEMS structure; and performing a second etching process by removing a portion of the MEMS structure to form a plurality of microstructures such that a relative motion among the microstructures takes place in a direction perpendicular to the substrate. | 05-19-2011 |
| 20110096506 | MULTI-LAYER SOC MODULE STRUCTURE - A multi-layer system-on-chip (SoC) module structure is provided. The multi-layer SoC module structure includes at least two circuit board module layers and at least one connector module layer. Each connector module layer is sandwiched between and thus electrically connects two circuit board module layers such that the SoC module structure is formed by stacking. Each circuit board module layer is composed of at least one circuit board module while each connector module layer is composed of at least one connector module. Hence, the SoC module structure can be manufactured as a three-dimensional structure, thus allowing highly flexible connections within the SoC module structure. | 04-28-2011 |
| 20100330741 | FABRICATION METHOD FOR SYSTEM-ON-CHIP (SOC) MODULE - A fabrication method for a system-on-chip (SoC) module is provided. The fabrication method includes the steps of providing at least two SoC sub-modules and connecting the SoC sub-modules. The SoC sub-modules are electrically connected with each other by connection interfaces of the SoC sub-modules so as to form the SoC module. As the SoC sub-modules have been verified in advance, the time required for verifying the resulting SoC module can be significantly reduced. As for application-specific SoC modules, they are fabricated by connecting with application-specific SoC sub-modules via the appropriate connection interfaces. Thus, the time and costs for developing SoC modules can both be minimized. | 12-30-2010 |
| 20100277203 | Edge-Missing Detector Structure - An edge-missing detector structure includes a first detector, a first delay unit, a first logic gate, a second detector, a second delay unit, and a second logic gate. After being input separately into the edge-missing detector structure, a first reference signal and a first clock signal are detected by the first and second detectors and then subjected to cycle suppression by the first and second logic gates, respectively, so as to generate a second reference signal and a second clock signal which present a phase difference less than 2π. Moreover, the edge-missing detector structure generates a compensative current corresponding to the number of occurrences of cycle suppression. Thus, a phase-locked loop (PLL) using the edge-missing detector structure can avoid cycle slip problems and achieve fast acquisition of phase lock. | 11-04-2010 |
| 20100099582 | Biochip Package Structure - A biochip package structure is provided. The biochip package structure includes a substrate, a biochip, at least one wire, and a molding compound. The substrate has a circuit unit electrically connected, by wiring, to the biochip defined with a sensing region. The molding compound covers the wire but leaves the sensing region of the biochip exposed, allowing a cavity to be formed in the sensing region. The cavity delivers a biomedical sample. The biomedical sample reacts in the sensing region. Thus, the biochip package structure is applicable to various medical and biochemical assays. | 04-22-2010 |
