NANYA TECHNOLOGY CORPORATION Patent applications |
Patent application number | Title | Published |
20150270830 | THREE DIMENSIONAL INTEGRATED CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A three dimensional integrated circuit includes a master circuit, a slave circuit, and a through-silicon via (TSV). The master circuit is configured to receive and process an input data, a data strobe signal (DQS) and an input command to output a writing data signal to a master die. The through-silicon via (TSV) is electrically coupled between the master circuit and the slave circuit. The master circuit is configured to transfer the writing data signal to a slave die through the TSV. Furthermore, a method for controlling a three dimensional integrated circuit is disclosed herein. | 09-24-2015 |
20150262634 | POWER GENERATOR FOR DATA LINE OF MEMORY APPARATUS - The invention provides the power generator includes a bias voltage generator and a voltage clamping circuit. The bias voltage generator receives a reference voltage and generates a bias voltage according to the reference voltage. The voltage clamping circuit is coupled to the bias voltage generator. The voltage clamping circuit receives a supply voltage and the bias voltage and respectively outputs a plurality of data line power to the data transporting buffers by clamping the supply voltage according to the bias voltage. Wherein, the supply voltage is varied between a voltage range, and voltage levels of the data line powers are all constant. | 09-17-2015 |
20150206836 | METHOD OF FORMING AN INTERCONNECT STRUCTURE WITH HIGH PROCESS MARGINS - A method of forming an interconnect structure with high process margin. The present invention provides higher aligning margin for the connection of via parts and line parts. The method for forming the interconnect structure includes the steps of: forming a first mask layer with a plurality of first openings over the first insulating layer; forming a second insulating layer over the mask layer; forming a second mask layer with a plurality of second openings over the second insulating layer; performing an etching process by using the second mask layer to form a plurality of cavities penetrating through the second insulating layer, the first mask layer, and the first insulating layer; and filling the plurality of cavities with at least one conductive material. | 07-23-2015 |
20150206789 | METHOD OF MODIFYING POLYSILICON LAYER THROUGH NITROGEN INCORPORATION FOR ISOLATION STRUCTURE - The present disclosure relates to a method of modifying a polysilicon layer, which includes the following steps. A polysilicon layer is provided. Nitrogen is incorporated into the polysilicon layer toward a predetermined depth. The polysilicon layer incorporated with nitrogen is etched, wherein after the nitrogenized polysilicon is removed, the formation of the remaining polysilicon layer is nearly indistinguishable from the formation of the polysilicon layer. | 07-23-2015 |
20150205340 | MEMORY DEVICE AND CONTROL METHOD - A memory device and a control method are disclosed herein. The memory device includes a delay locked loop module, a memory bank module and a control module. The delay locked loop module is configured to generate a system clock signal when enabled by a control signal. The memory bank module is configured to read or write data signals in accordance with the system clock signal and a read command or a write command. The control module configured to receive at least one control command to generate the control signal, wherein the control module disables the delay locked loop, when the memory bank module goes to a precharge mode or a powerdown mode. | 07-23-2015 |
20150203753 | LIQUID ETCHANT COMPOSITION, AND ETCHING PROCESS IN CAPACITOR PROCESS OF DRAM USING THE SAME - An etching process in a capacitor process for DRAM is described. A substrate is provided, which has thereon a silicon layer and metal electrodes in the silicon layer. The silicon layer is removed using a liquid etchant composition. The liquid etchant composition contains tetramethylammonium hydroxide (TMAH), an additive including hydroxylamine or a metal corrosion inhibitor, and water as a solvent. | 07-23-2015 |
20150200163 | CHIP PACKAGE - A chip of a chip package comprises a substrate having a chip circuit, a chip selection terminal connecting to the chip circuit, multiple first conductors separated at different levels by multiple insulation layers, multiple first vertical connections respectively connecting to the first conductors and extending to a substrate surface, multiple second vertical connections respectively connecting to the first conductors and extending to a surface of the insulation layers, a third vertical connection electrically connecting to the chip selection terminal and extending to the substrate surface, a fourth vertical connection formed through the insulation layers and the substrate, a second conductor formed on the surface of the insulation layers and connecting to the fourth vertical connection, multiple first pads respectively connecting to the first vertical connections and the third vertical connection, and multiple second pads respectively connecting to the second vertical connections. | 07-16-2015 |
20150187703 | BOX-IN-BOX OVERLAY MARK - A box-in-box overlay mark is described, including an inner box region and an outer box region surrounding the same, dense narrow trenches in the previous layer in the inner box region and the outer box region, x- and y-directional linear photoresist patterns defining a rectangle over the narrow trenches in the inner box region, and x- and y-directional linear patterns defining another rectangle in the outer box region. At least the narrow trenches in the inner box region are orientated in a direction different from the x-direction and the y-direction. The linear photoresist patterns are defined in or from a photoresist layer for defining a current layer, each of which is wider than each of the narrow trenches. The linear patterns are defined in or from the previously layer, each of which is wider than each of the narrow trenches. | 07-02-2015 |
20150115462 | INTEGRATED CIRCUIT DEVICE - An integrated circuit device includes a substrate, at least one transistor, at least one metal layer, a conductive pillar, and a connecting structure. The substrate has at least one via passing therethrough. The transistor is at least partially disposed in the substrate. The metal layer is disposed on or above the substrate. The conductive pillar is disposed in the via. The connecting structure is at least partially disposed in the via and connecting the conductive pillar and the metal layer. At least a first portion of the connecting structure is made of a stress releasing material having a coefficient of thermal expansion less than a coefficient of thermal expansion of the conductive pillar. A projection of the transistor in the via overlaps with the connecting structure. | 04-30-2015 |
20150097296 | MULTI-DIE STACK STRUCTURE - A multi-die stack structure including N dies stacked vertically is described. N is an integer larger than or equal to 2. Each die includes N die-specific input pads, wherein a specific pad among the N pads is for the input of the die. The specific pad of each die above the bottom die is electrically connected with a different pad of the bottom die other than the specific pad of the bottom die, via at least one TSV and, when not being in the die neighboring to the bottom die, also via a different pad of each underlying die above the bottom die. The specific pad of the bottom die is electrically connected with at least one pad of the overlying die(s) that is not the specific pad of any overlying die and not any pad electrically connected with the specific pad of any overlying die. | 04-09-2015 |
20150097228 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, which includes the following steps. First, a substrate having at least one transistor is provided. A first insulation layer is formed to cover the transistor. The first insulation layer is patterned to form at least one opening, wherein a part of the transistor is exposed by the opening. At last, an epitaxy is formed in the opening to cover the part of the transistor. | 04-09-2015 |
20150084205 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - A semiconductor device comprises a plurality of conductors for connecting another semiconductor device. Each conductor connects to a chip select pad within the semiconductor device through an upper vertical connection formed through an insulation layer formed on a substrate or connected to a straight vertical connection formed through the substrate and the insulation layer. The semiconductor device further comprises a plurality of lower vertical connections formed through the substrate and correspondingly connecting to the chip select pads and a chip select terminal. The chip select terminal electrically connects to the die circuit of the semiconductor device while the chip select pads are electrically isolated from the die circuit. The lower vertical connections and the straight vertical connection can be arranged in two dimensions. | 03-26-2015 |
20150076698 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. | 03-19-2015 |
20150063051 | LOW POWER PROTECTION CIRCUIT - The present invention provides the low power protection circuit including a first voltage detector, a pulse generating circuit, a SR latch, and an output logic operation circuit. The low power protection circuit is adapted for a dynamic random access memory (DRAM) with dual operating voltages. The first voltage detector generates a high-voltage pump enable signal by detecting a voltage level of the power-up signal. The pulse generating circuit generates a power-up pulse according to the power-up signal. The SR latch receives the power-up pulse, the high-voltage pump enable signal and an inverted power-up signal, and generates an output signal. The second voltage detector generates a low-voltage pump enable signal by detecting a voltage level of the output signal. The output logic operation circuit generates a pump enable signal according to the low-voltage pump enable signal and the high-voltage pump enable signal. | 03-05-2015 |
20150048894 | DELAY LINE RING OSCILLATION APPARATUS - The delay line degradation protection architecture as build-in ring oscillation apparatus includes a two gates logical circuit, a buffer, a clock input buffer and a delay lock loop circuit. The two gates logical circuit receives a clock enable signal, specific mode signal, and delayed clock output signal. The two gates logical circuit performs a logical operating on the clock enable signal, the specific mode signal and the delayed clock output signal for generating a mode selecting signal. The buffer generates a feedback signal according to the mode selecting signal and a control signal. The clock input buffer decides whether to transport the input clock signal to an output end of the clock input buffer or not according to the feedback signal. The delay lock loop circuit generates the delayed clock output signal. A frequency of the feedback signal is adjusted according to the control signal. | 02-19-2015 |
20150048886 | TEMPERATURE DETECTING APPARATUS, SWITCH CAPACITOR APPARATUS AND VOLTAGE INTEGRATING CIRCUIT THEREOF - The invention provides a temperature detecting apparatus, a switch capacitor apparatus and a voltage integrating circuit. The voltage integrating circuit includes an operating amplifier, a capacitor and a current source. The operating amplifier has a positive input end, a negative input end and an output end. The output end of the operating amplifier generates an output voltage, and the positive input end receives a reference voltage. The capacitor is coupled between the output end and the negative input end of the operating amplifier. The current source is coupled to the output end of the operating amplifier. The current source draws a replica current from the capacitor, and a current level of the replica current is determined according to a current level of a current flowing to the negative input end of the operating amplifier. | 02-19-2015 |
20150048880 | GLITCH FILTER AND FILTERING METHOD - A glitch filter is disclosed herein. The glitch filter includes a high glitch filter circuit, a low glitch filter and a control circuit. The high glitch filter circuit is configured for generating a pull-up control signal in accordance with the input signal. The low glitch filter circuit is configured for generating a pull-down control signal in accordance with the input signal. The control circuit is configured for determining the logic level of the output of the glitch filter in accordance with the pull-up control signal and the pull-down control signal. A filtering method for filtering glitches is disclosed herein as well. | 02-19-2015 |
20150046738 | DATA BUFFER SYSTEM AND POWER CONTROL METHOD - A data buffer system includes a plurality of data buffer modules and a plurality of switching units. The data buffer module is configured for buffering a corresponding data signal. The data buffer module includes a plurality of buffers. The buffers are electrically coupled in series. The switching unit is configured for supplying power to the corresponding buffer in accordance with a regulated voltage. Each of the switching units is electrically coupled between the corresponding one of the buffers and the supply voltage. A power control method for a data buffer system is also provided. | 02-12-2015 |
20150028459 | METHOD FOR SEMICONDUCTOR SELF-ALIGNED PATTERNING - A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; | 01-29-2015 |
20140355361 | CIRCUIT IN DYNAMIC RANDOM ACCESS MEMORY DEVICES - A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry. | 12-04-2014 |
20140327307 | VOLTAGE TRACKING CIRCUIT - A voltage tracking circuit, which comprises a voltage generating device, a first operational amplifier, a first voltage generator, and a diode-connected device. The voltage generating device provides a fixed voltage. The first operational amplifier has a first input terminal that can receive the fixed voltage, a second input terminal that is coupled with a protected device model, and an output terminal. The first voltage generator connects to the output terminal of the first operational amplifier and to a voltage limiter that is coupled with devices under protection. The diode-connected device is in a feedback loop that connects the second input terminal of the first operational amplifier to the first voltage generator. | 11-06-2014 |
20140266360 | DUTY CYCLE CORRECTOR - The duty cycle corrector for correcting a system clock signal comprises a duty cycle detector and a duty cycle adjuster. The duty cycle detector is configured for detecting a system duty cycle of the system clock signal and generating the first control signal and the second control signal, wherein the first control signal and the second control signal are complementary to each other. The duty cycle adjuster comprises an inverter and the duty cycle adjuster is configured for delaying a change in an input status of the inverter and adjusting of the inverter in accordance with the first control signal and the second control signal. | 09-18-2014 |
20140266359 | CLOCK CYCLE COMPENSATOR AND THE METHOD THEREOF - One aspect of the present invention is to provide a method for compensating a system duty cycle of a system clock signal. The method in one embodiment comprises the following steps: locking a duty cycle center of the system duty cycle by a delay lock loop; detecting a current system duty cycle of the system clock signal; determining a duty cycle correction amount, wherein the duty cycle correction amount is a gap of the current system duty cycle from a target duty cycle; and changing a polarity of an input reference clock signal according to whether the duty cycle correction amount exceed a threshold amount or not. | 09-18-2014 |
20140264893 | PITCH-HALVING INTEGRATED CIRCUIT PROCESS AND INTEGRATED CIRCUIT STRUCTURE MADE THEREBY - A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns. | 09-18-2014 |
20140252532 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening. | 09-11-2014 |
20140252459 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, which includes the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar, and a doped region is disposed at a bottom of each pillar. An insulation layer is formed below each doped region. | 09-11-2014 |
20140213035 | METHOD OF FORMING BURIED WORD LINE STRUCTURE - A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer. | 07-31-2014 |
20140206172 | ALIGNMENT MARK AND METHOD OF MANUFACTURING THE SAME - An alignment mark includes a plurality of mark units. Each mark unit includes a first element and a plurality of second elements. Each second element includes opposite first and second end portions. The plurality of second elements are arranged along a direction. The first element extends adjacent to the first end portions of the plurality of second elements and parallel to the direction of the plurality of second elements. | 07-24-2014 |
20140082572 | METHOD OF GENERATING ASSISTANT FEATURE - A method of generating an assistant feature is provided. A plurality of main features is provided. A first main feature is selected from the main features. A plurality of rule-based features is disposed around the first main feature. A model-based feature is generated around the first main feature. An overlap Boolean feature is extracted from the rule-based features, wherein the overlap Boolean feature overlaps with the model-based feature in an overlap ratio up to a target value. The overlap Boolean feature serves as an assistant feature, and the assistant feature and the first main feature constitute a transfer feature. | 03-20-2014 |
20140080305 | DOUBLE PATTERNING PROCESS - A double patterning process is described. A substrate having a first area and a second area is provided. A target layer is formed over the substrate. A patterned first photoresist layer is formed over the target layer, wherein the patterned first photoresist layer has openings and has a first thickness in the first area, and at least a portion of the patterned first photoresist layer in the second area has a second thickness less than the first thickness. A second photoresist layer is then formed covering the patterned first photoresist layer and filling in the openings. | 03-20-2014 |
20140065380 | OVERLAY MARK AND METHOD OF FORMING THE SAME - A method of forming an overlay mark is provided. A plurality of photoresist patterns are formed on a substrate. Each of the photoresist patterns includes a first strip and a plurality of second strips arranged in parallel. The first strip crosses the second strips to form a fence shape. Further, there is a space between two adjacent photoresist patterns, and the space is fence-shaped. A plurality of islands are formed in each of the spaces to form dot type strip patterns. The photoresist patterns are removed, and the dot type strip patterns serve as the overlay mark. | 03-06-2014 |
20140062597 | EXTERNAL PROGRAMMABLE DFE STRENGTH - A decision feedback equalizer is disclosed. The decision feedback equalizer comprises an amplifier circuit and a latch. The amplifier circuit is configured to receive an input signal, a decision feedback signal and a control signal, and is configured to adjust its driving capability according to the decision feedback signal and the control signal to provide an amplified signal of the input signal. The latch is configured to latch the amplified signal as an output signal. | 03-06-2014 |
20140054794 | MEMORY PROCESS AND MEMORY STRUCTURE MADE THEREBY - A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer. | 02-27-2014 |
20140054720 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEROF - A method for fabricating a semiconductor device is provided. A first polysilicon layer of a first conductivity type is provided on a substrate having first and second active regions. An ion implantation process is performed in the polysilicon layer corresponding to the second active region by using a dopant of a second conductivity type opposite to the first conductivity type, and silane plasma is introduced during the ion implantation process to form a second polysilicon layer thereon and convert the first conductivity type of the first polysilicon layer corresponding to the second active region to the second conductivity type. The first and second polysilicon layers are patterned to form a first gate layer corresponding to the first active region and a second gate layer corresponding to the second active region. A semiconductor device is also provided. | 02-27-2014 |
20140049302 | PHASE-LOCKED LOOP AND METHOD FOR CLOCK DELAY ADJUSTMENT - A phase-locked loop (PLL) for clock delay adjustment and a method thereof are disclosed. The method includes the following steps. A reference clock signal and a clock signal are generated. The reference clock signal is fed through an N-divider to generate an output clock signal having a frequency 1/N of the reference clock signal. | 02-20-2014 |
20140046616 | CIRCUIT TEST SYSTEM AND CIRCUIT TEST METHOD THEREOF - A circuit test system including a circuit test apparatus and a circuit to be tested is provided. The circuit test apparatus provides a first clock signal. The circuit to be tested includes a plurality of input/output pads and at least one clock pad. At least two input/output pads of the input/output pads are connected to each other to form a test loop during a test mode. The clock pad receives the first clock signal. The circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the test loop of the circuit to be tested is tested based on the second clock signal during the test mode. The frequency of the second clock signal is higher than that of the first clock signal. Furthermore, a circuit test method of the foregoing circuit test system is also provided. | 02-13-2014 |
20140042548 | DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF - A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines. | 02-13-2014 |
20140036611 | VOLTAGE GENERATING SYSTEM AND MEMORY DEVICE USING THE SAME - A voltage generating system and a memory device using the same are disclosed. The voltage generating system includes an internal voltage regulator, configured to supply a current to pull an internal supply voltage to a regulated level and maintain at the regulated level; and a substrate-bias controlled selector, configured to receive a regulator power-up mode signal, a regulating mode signal and a substrate-bias voltage of a substrate, and control the internal voltage regulator such that when the substrate-bias voltage is smaller than a predetermined voltage, the internal voltage regulator powers up and operates normally by respectively taking the regulator power-up mode signal and the regulating mode signal into consideration, and when the substrate-bias voltage is larger than or equal to the predetermined voltage, the internal voltage regulator is disabled. The predetermined voltage is smaller than or equal to a forward voltage of a p-n junction formed with the substrate. | 02-06-2014 |
20140036565 | MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY STRUCTURE - An exemplary memory device includes a substrate and two word lines extending on the substrate. The substrate includes an active area. The two word lines are formed on the active area. Each word line includes a recessed portion corresponding to the active area. The recessed portion is defined by a planar top surface. | 02-06-2014 |
20140034585 | CASSETTE TRAY AND CARRIER MODULE - A cassette tray is provided, which includes a bottom plate and two holding members. The bottom plate includes a plurality of positioning holes, wherein the positioning holes are arranged in rows along a first direction, and the rows are spaced apart from each other in a second direction perpendicular to the first direction. Each of the holding members is selectively connected to the positioning holes in one of the rows and mounted on the bottom plate in a detachable manner, and a circuit board is received between the two holding members. | 02-06-2014 |
20140021599 | THREE-DIMENSIONAL INTEGRATED CIRCUITS AND FABRICATION THEREOF - A three-dimensional integrated circuit is disclosed, including a first interposer including through substrate vias (TSV) therein and circuits thereon; a plurality of first active dies disposed on a first side of the first interposer, a plurality of first intermediate interposers, each including through substrate vias (TSV), disposed on the first side of the first interposer, and a second interposer including through substrate vias (TSV) therein and circuits thereon supported by the first intermediate interposers. | 01-23-2014 |
20140021535 | SEMICONDUCTOR DEVICE HAVING VERTICAL GATES AND FABRICATION THEREOF - A method for forming a semiconductor device with a vertical gate is disclosed, including providing a substrate, forming a recess in the substrate, forming a gate dielectric layer on a sidewall and a bottom of the recess, forming an adhesion layer in the recess and on the gate dielectric layer, wherein the adhesion layer is a metal silicide nitride layer, and forming a gate layer in the recess and on the adhesion layer. | 01-23-2014 |
20140008117 | CONNECTING STRUCTURE OF CIRCUIT BOARD - A connecting structure of a circuit board is provided. The connecting structure includes at least one connecting trace and at least one connecting pad. The connecting trace and the connecting pad are disposed on a surface, or inside of the circuit board. The connecting pad has a first end surface and a second end surface at two opposite end surfaces thereof. The first end surface is a convex curved surface and connected to the connecting trace, and a cross section area of the connecting pad is gradually increased from the first end surface. | 01-09-2014 |
20140001633 | COPPER INTERCONNECT STRUCTURE AND METHOD FOR FABRICATING THEREOF | 01-02-2014 |
20130337629 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches. | 12-19-2013 |
20130336571 | MASK PATTERN ANALYSIS APPARATUS AND METHOD FOR ANALYZING MASK PATTERN - A pattern analysis method includes the steps of: grouping a plurality of polygons in a circuit layout into a plurality of polygon groups; locating a potential defect area of each polygon group according to an aerial image of the circuit layout; determining a representing point of the potential defect area of each polygon group; determining representing points of the plurality of polygons in each polygon group; and comparing a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in one of the polygon groups with a distribution pattern of the representing points of the plurality of polygons relative to the representing point of the potential defect area in another of the polygon groups. The steps aforesaid are executed by a processor in a computer system. | 12-19-2013 |
20130323626 | REFLECTIVE MASK - A reflective mask includes a substrate, a first reflective multi-layer, a second reflective multi-layer, a first patterned absorber layer and a second patterned absorber layer. The substrate includes a first surface and a second surface opposite to the first surface. The first reflective multi-layer is formed on the first surface of the substrate. The second reflective multi-layer is formed on the second surface of the substrate. The first patterned absorber layer is formed on the first reflective multi-layer. The second patterned absorber layer is formed on the second reflective multi-layer. | 12-05-2013 |
20130320540 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a conductive material, and a material layer. The substrate includes a through hole. The conductive material fills the through hole. The material layer is formed in the conductive material, wherein an electrical resistance of the conductive material is lower than an electrical resistance of the material layer. | 12-05-2013 |
20130320442 | TRANSISTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively. | 12-05-2013 |
20130307612 | VOLTAGE DOUBLER AND OSCILLATING CONTROL SIGNAL GENERATOR THEREOF - A voltage doubler and an oscillating control signal generator controlling a charge pump (powered by a first voltage to provide a second voltage) of the voltage doubler are disclosed. The oscillating control signal generator includes a first input terminal receiving a fundamental oscillation signal, a second input terminal receiving a comparison result showing whether the second voltage is greater than a target value, a third input terminal operative to obtain an electric current consumption status at an output terminal of the charge pump, and an output terminal outputting an oscillating control signal for the control of the charge pump. Further, the oscillating control signal generator includes a logic circuit. The logic circuit generates the oscillating control signal by selectively blocking status changes of the fundamental oscillation signal according to the comparison result and the electric current consumption status. | 11-21-2013 |
20130307166 | METHOD FOR FORMING PATTERNS OF DENSE CONDUCTOR LINES AND THEIR CONTACT PADS, AND MEMORY ARRAY HAVING DENSE CONDUCTOR LINES AND CONTACT PADS - A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern. | 11-21-2013 |
20130307017 | ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - The invention discloses an ESD protection circuit, comprising a P-type substrate; an N-well formed on the P-type substrate; a P-doped region formed on the N-well, wherein the P-doped region is electrically connected to an input/output terminal of a circuit under protection; a first N-doped region formed on the P-type substrate, the first N-doped region is electrically connected to a first node, and the P-doped region, the N-well, the P-type substrate, and the first N-doped region constitute a silicon controlled rectifier; and a second N-doped region formed on the N-well and electrically connected to a second node, wherein a part of the P-doped region and the second N-doped region constitute a discharging path, and when an ESD event occurs at the input/output terminal, the silicon controlled rectifier and the discharging path bypass electrostatic charges to the first and second nodes respectively. | 11-21-2013 |
20130301371 | DYNAMIC RANDOM ACCESS MEMORY WITH MULTIPLE THERMAL SENSORS DISPOSED THEREIN AND CONTROL METHOD THEREOF - A dynamic random access memory (DRAM) with multiple thermal sensors disposed therein and a control method for the DRAM. A DRAM in accordance with an exemplary embodiment of the invention provides multi-zone temperature detection. The DRAM comprises a plurality of banks, a plurality of thermal sensors and a control unit. The thermal sensors are disposed between the banks. The control unit controls the thermal sensors to obtain sensed temperatures, and sets a self-refresh cycle for all of the banks based on the highest one of the sensed temperatures. | 11-14-2013 |
20130299884 | MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY DEVICE - A memory device includes a substrate, first and second trench isolations, a plurality of line-type isolations, a first word line, and a second word line. The substrate comprises an active area having source and drain regions. The first and second trench isolations extend parallel to each other. The line-type isolations define the active area together with the first and second trench isolations. The first word line extends across the active area and is formed in the substrate adjacent to the first trench isolation defining a first segment of the active area with the first trench isolation. The second word line extends across the active area and is formed in the substrate adjacent to the second trench isolation defining a second segment of the active area with the second trench isolation. The size of the first segment is substantially equal to the size of the second segment. | 11-14-2013 |
20130270708 | METHOD FOR FORMING BURIED CONDUCTIVE LINE AND STRUCTURE OF BURIED CONDUCTIVE LINE - A method for forming a buried conductive line is described. A substrate having a trench therein and a contact area thereon is provided, wherein the trench has an end portion in the contact area and a conductive layer is filled in the trench. A mask layer is formed covering the conductive layer in the contact area. The conductive layer is etched back using the mask layer as a mask. | 10-17-2013 |
20130249047 | THROUGH SILICON VIA STRUCTURE AND METHOD FOR FABRICATING THE SAME - A through silicon via structure is provided, including a substrate, an isolation layer, a conductive layer and a dielectric layer. The substrate has a through-hole therein. The isolation layer is disposed on two sidewalls of the through-hole. The conductive layer is disposed in the through-hole and covers the isolation layer, and the conductive layer includes a first portion and a second portion, wherein the first portion fills a portion of the through-hole, and the second portion is located on the sidewalls in the other portion of the through-hole, such that the conductive layer has a concave part. The dielectric layer is disposed in the concave part and fills the concave part. | 09-26-2013 |
20130183809 | METHOD OF FABRICATING MEMORY DEVICE - A method of fabricating a memory device comprises forming a plurality of first insulative blocks and a plurality of second insulative blocks arranged in an alternating manner in a substrate, forming a plurality of wide trenches in the substrate to form a plurality of protruding blocks, forming a word line on each sidewall of the protruding blocks, isolating the word line on each sidewall of the protruding block, and forming an trench filler in the protruding block to form two mesa structures, wherein the first insulative block and the second insulative block have different depths, and the wide trenches are transverse to the first insulative blocks. | 07-18-2013 |
20130183808 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections. | 07-18-2013 |
20130182255 | OVERLAY MARK AND APPLICATION THEREOF - An overlay mark for checking alignment accuracy between a former layer and a later layer on a wafer is described, including a former pattern as a part of the former layer, and a later pattern as a part of a patterned photoresist layer defining the later layer. The former pattern has two parallel opposite edges each forming a sharp angle α with the x-axis of the wafer. The later pattern also has two parallel opposite edges each forming the sharp angle α with the x-axis of the wafer. | 07-18-2013 |
20130181277 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THEREOF - A semiconductor device includes a semiconductor substrate having a first opening and a second opening adjacent thereto. A first dielectric layer is disposed in a lower portion of the first opening. A charge-trapping dielectric layer is disposed in an upper portion of the first opening to cover the first dielectric layer. A doping region of a predetermined conductivity type is formed in the semiconductor substrate adjacent to the first opening and the second opening, wherein the doping region of the predetermined conductivity type has a polarity which is different from that of the charges trapped in the charge-trapping dielectric layer. A gate electrode is disposed in a lower portion of the second opening. A method for fabricating the semiconductor device is also disclosed. | 07-18-2013 |
20130168877 | MASK OVERLAY METHOD, MASK, AND SEMICONDUCTOR DEVICE USING THE SAME - A mask overlay method, and a mask and a semiconductor device using the same are disclosed. According to the disclosed mask overlay technique, test marks and front layer overlay marks corresponding to a plurality of overlay mark designs are generated in a first layer of a semiconductor device. The test patterns generating the test marks each include a first sub pattern and a second sub pattern. Note that the first sub pattern has the same design as a front layer overlay pattern (which generates the front layer overlay mark corresponding thereto). Based on the test marks, performances of the plurality of overlay mark designs are graded. The front layer overlay mark corresponding to the overlay mark design having the best performance is regarded as an overlay reference for a mask of a second layer of the semiconductor device. | 07-04-2013 |
20130164689 | PHOTOMASK AND METHOD FOR FORMING OVERLAY MARK USING THE SAME - The present invention relates to a photomask and a method for forming an overlay mark in a substrate using the same. The photomask comprises a plurality of patterns. At least one of the patterns comprises a plurality of ring areas and a plurality of inner areas enclosed by the ring areas, wherein the light transmittancy of the ring areas is different from that of the inner areas. When the photomask is applied in a photolithography process, the formed overlay mark has a large thickness. Therefore, the contrast is high when a metrology process is performed, and it is easy to find the overlay mark. | 06-27-2013 |
20130161735 | TRANSISTOR STRUCTURE AND METHOD FOR PREPARING THE SAME - A transistor structure includes a semiconductor substrate; a conductor having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate; a metal layer positioned on the upper block; a cap layer positioned on the metal layer; an upper insulation layer positioned at least on sidewalls of the metal layer and the cap layer; and a lower insulation layer positioned on sidewalls of the upper block of the conductor. | 06-27-2013 |
20130157176 | PHOTOMASK - A photomask is provided. The photomask is applied to a photolithography apparatus and includes a substrate with a mask pattern disposed thereon. The mask pattern includes at least one main pattern and a plurality of sub-resolution assistant features (SRAFs). The SRAFs are disposed around the main pattern and separated from each other, wherein a distance between each of the SRAFs and the main pattern is about 3 to 10 times a linewidth of the main pattern. The photomask would result in an improved imaging quality on the wafer. | 06-20-2013 |
20130141124 | TEST METHOD OF DRIVING APPARATUS AND CIRCUIT TESTING INTERFACE THEREOF - A circuit testing interface and test method are disclosed. The circuit testing interface may include a test current transmitting pad, a test voltage measuring pad, and at least one driving circuit comprising an output terminal. The output terminal of the at least one driving circuit may be coupled to a through-silicon via (TSV). The circuit testing interface may further include at least one switch module, coupled to (1) the output terminal of the driving circuit, (2) the test current transmitting pad, and (3) the test voltage measuring pad. | 06-06-2013 |
20130102123 | METHOD FOR FABRICATING SINGLE-SIDED BURIED STRAP IN A SEMICONDUCTOR DEVICE - A method for manufacturing a buried-strap includes: forming a trench capacitor structure in a semiconductor substrate, wherein the trench capacitor structure has a doped polysilicon layer and an isolation collar covered by the doped polysilicon layer, and a top surface of the doped polysilicon layer is lower than a top surface of the semiconductor substrate such that a first recess is formed; sequentially forming a first resist layer, a second resist layer and a third resist layer over the semiconductor substrate; sequentially patterning the third resist layer, the second resist layer and the first resist layer, forming a patterned tri-layer resist layer over the semiconductor substrate; partially removing a portion of the doped polysilicon layer exposed by the patterned tri-layer resist layer to form a second recess; removing the patterned tri-layer resist layer; and forming an insulating layer in the second recess and a portion of the first recess. | 04-25-2013 |
20130099309 | VERTICAL MOSFET ELECTROSTATIC DISCHARGE DEVICE - A vertical MOSFET electrostatic discharge device is disclosed, including a substrate comprising a plurality of trenches, a recessed gate disposed in each trench, a drain region disposed between each of the two neighboring recessed gates, an electrostatic discharge implant region disposed under each drain region, and a source region surrounding and disposed under the recessed gates and the electrostatic discharge implant regions. | 04-25-2013 |
20130082718 | CIRCUIT TEST INTERFACE AND TEST METHOD THEREOF - A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad. | 04-04-2013 |
20130078815 | METHOD FOR FORMING SEMICONDUCTOR STRUCTURE WITH REDUCED LINE EDGE ROUGHNESS - A method for forming a semiconductor structure with reduced line edge roughness is provided, including: providing a device layer with a patterned photoresist layer formed thereon; and performing a plasma etching process to pattern the device layer with the patterned photoresist layer formed thereon, forming a patterned device layer, wherein the plasma etching process is operated under a continuous on-stage voltage provided with a relative higher frequency and an on-off stage voltage with pulsing modulation provided with a relative lower frequency. | 03-28-2013 |
20130078804 | METHOD FOR FABRICATING INTEGRATED DEVICES WITH REDUCTED PLASMA DAMAGE - A method for fabricating an integrated device with reduced plasma damage is disclosed, including providing a substrate, forming a structural layer on the substrate, forming a photoresist layer on the structural layer, and performing an etching process to the structural layer, wherein the photoresist layer is conductive to reduce plasma damage during the etching process. | 03-28-2013 |
20130078774 | METHOD FOR FORMING DOPE REGIONS WITH RAPID THERMAL PROCESS - The invention provides a method for forming a semiconductor device, including providing a substrate, forming a gate dielectric layer, forming a gate electrode on the gate dielectric layer, forming a spacer on sidewalls of the gate dielectric layer and the gate electrode, and using a rapid thermal process (RTP) apparatus comprising a plurality of lamps and a bias applying system to dope the substrate to form a source/drain region, wherein in the RTP apparatus, gaseous dopant species are illuminated by the lamps to be excited for transference gaseous dopant species to dopant ions and the dopant ions are moved by a bias from the bias applying system to be doped into the substrate. | 03-28-2013 |
20130077414 | MEMORY APPARATUS - A memory apparatus includes a mimic redundant device comparator, a reference delay signal generator, and a signal comparison controller. The mimic redundant device comparator is configured to receive an input signal and to delay the input signal according to a mimic delay, so as to generate a comparison signal. The reference delay signal generator is configured to receive the input signal and to delay the input signal according to a plurality of reference delays, so as to generate a plurality of reference delay signals. The signal comparison controller is configured to receive the reference delay signals and the comparison signal. According to a time difference between the comparison signal and the reference delay signals, the signal comparison controller is configured to generate a selected signal and to generate a delay control signal according to the selected signal. | 03-28-2013 |
20130074878 | WAFER SCRUBBER - A wafer scrubber is disclosed, including a chamber, and a holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and the wafer spins to remove water on the wafer, and a mashed inner cup comprising a plurality of through holes disposed between the holder and a wall of the chamber, wherein the mashed inner cup receives water from a surface of the wafer and rotates around the spindle to release the water through the through holes. | 03-28-2013 |
20130071992 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. An insulating layer is formed on a semiconductor substrate. A portion of the insulating layer is removed, so as to form a plurality of isolation structures and a mesh opening disposed between the isolation structures and exposing the semiconductor substrate. By performing a selective growth process, a semiconductor layer is formed from a surface of the semiconductor substrate exposed by the mesh opening, so that the isolation structures are disposed in the semiconductor layer. | 03-21-2013 |
20130071978 | FABRICATING METHOD OF TRANSISTOR - A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain. | 03-21-2013 |
20130068264 | WAFER SCRUBBER APPARATUS - A wafer scrubber apparatus is disclosed, including a chamber, and holder connecting to a spindle disposed in the chamber, wherein the holder supports a wafer, and a gas purge pipe disposed at the top of a wall of the chamber, wherein the gas purge pipe comprises a plurality of gas injection holes facing downward to purge gas along the chamber wall making water flow along the chamber wall more smoothly and more quickly for preventing the water from scattering back to the wafer. | 03-21-2013 |
20130052820 | METHOD OF FORMING CONDUCTIVE PATTERN - A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other. | 02-28-2013 |
20130051495 | INTERACTIVE DIGITAL DUTY CYCLE COMPENSATION CIRCUIT FOR RECEIVER - A receiver circuit. A receiving stage is coupled to a first supply voltage and an input signal, and operative to generate a first intermediate signal from the input signal based on the first supply voltage. A compensation stage is coupled to a second supply voltage and the first intermediate signal, and operative to generate a second intermediate signal by adjusting duty cycle of the first intermediate signal upon detecting changes in the first supply voltage to compensate for the changes in the first supply voltage. An outputting stage is coupled to the second supply voltage and operative to generate an output signal based on the second supply voltage upon receiving the second intermediate signal. A voltage of the output signal is adjusted to a level of the second supply voltage and the output signal has a 50% duty cycle. | 02-28-2013 |
20130045600 | METHOD FOR FORMING FIN-SHAPED SEMICONDUCTOR STRUCTURE - A method for fabricating a fin-shaped semiconductor structure is provided, including: providing a semiconductor substrate with a semiconductor island and a dielectric layer formed thereover; forming a mask layer over the semiconductor island and the dielectric layer; forming an opening in the mask layer, exposing a top surface of the semiconductor island and portions of the dielectric layer adjacent to the semiconductor island; performing an etching process, simultaneously etching portions of the mask layer, and portions of the semiconductor island and the dielectric layer exposed by the opening; and removing the mask layer and the dielectric layer, leaving an etched semiconductor island with curved top surfaces and various thicknesses over the semiconductor substrate. | 02-21-2013 |
20130017687 | METHOD FOR FORMING OPENINGS IN SEMICONDUCTOR DEVICEAANM Lin; Chih-ChingAACI Taoyuan CountyAACO TWAAGP Lin; Chih-Ching Taoyuan County TWAANM Chen; Yi-NanAACI Taoyuan CountyAACO TWAAGP Chen; Yi-Nan Taoyuan County TWAANM Liu; Hsien-WenAACI Taoyuan CountyAACO TWAAGP Liu; Hsien-Wen Taoyuan County TW - A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O | 01-17-2013 |
20130017684 | PROCESS OF FORMING SLIT IN SUBSTRATEAANM Wang; Wen-ChiehAACI Taoyuan CountyAACO TWAAGP Wang; Wen-Chieh Taoyuan County TWAANM Chen; Yi-NanAACI Taipei CityAACO TWAAGP Chen; Yi-Nan Taipei City TWAANM Liu; Hsien-WenAACI Taoyuan CountyAACO TWAAGP Liu; Hsien-Wen Taoyuan County TW - A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl | 01-17-2013 |
20130017666 | METHOD OF FORMING ISOLATION STRUCTUREAANM Chung; Jui HsuanAACI New Taipei CityAACO TWAAGP Chung; Jui Hsuan New Taipei City TW - A method of forming an isolation structure includes the steps of forming an insulating spacer on the side surfaces of a trench in a substrate, exposing a portion of the substrate, growing an epitaxial silicon layer above a bottom surface of the trench, oxidizing the epitaxial silicon layer to form a thermal oxide layer, and filling a portion of the trench above the thermal oxide layer with a dielectric material. | 01-17-2013 |
20130001658 | CORNER TRANSISTOR AND METHOD OF FABRICATING THE SAME - A method of fabricating a corner transistor is described. An isolation structure is formed in a substrate to define an active region. A treating process is performed to make the substrate in the active region have sharp corners at top edges thereof. The substrate in the active region is covered by a gate dielectric layer. A gate conductor is formed over the gate dielectric layer. A source region and a drain region are formed in the substrate beside the gate conductor. | 01-03-2013 |
20120309192 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion. | 12-06-2012 |
20120309155 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. A substrate is provided, gates each including a silicon layer, a silicide layer and a cap layer are formed thereon, and doped regions are formed at two sides of each gate. An insulating layer is formed to cover a memory region and a periphery region. First contact holes are formed in the insulating layer in the memory region, and each first contact hole is disposed between the two adjacent gates and exposes the doped region. A contact plug is formed in each first contact hole to electrically connect the doped region. A patterned mask layer is formed on the substrate to cover the memory region and expose a portion of the periphery region. Using the patterned mask layer as a mask, second and third contact holes are formed in the insulating layer in the periphery region, to expose the silicide layer and the doped region. | 12-06-2012 |
20120302070 | METHOD AND SYSTEM FOR PERFORMING PULSE-ETCHING IN A SEMICONDUCTOR DEVICE - A method for performing pulse-etching in a semiconductor device includes the steps of providing a semiconductor substrate, wherein a metal layer is disposed on the semiconductor substrate, and a hard mask layer is blanketed over the metal layer; introducing the semiconductor substrate into a processing container; introducing, into the processing container, etching gases in which a deposition-type gas composed of at least two of C, H, and F is added to etching gas selected from the group consisting of Cl | 11-29-2012 |
20120302065 | PULSE-PLASMA ETCHING METHOD AND PULSE-PLASMA ETCHING APPARATUS - The present invention relates to a pulse-plasma etching method and apparatus for preparing a depression structure with reduced bowing. The pulse-plasma etching apparatus comprises a container, an upper electrode plate, a lower electrode plate, a gas source, a first ultrahigh RF power supply, a bias RF power supply, and a pulsing module. When the pulsing module supplies an ultrahigh-frequency voltage between the upper electrode plate and the lower electrode plate, an ultrahigh-frequency voltage is switched to the off state, and a large amount of electrons pass through the plasma and reach the substrate to neutralize the positive ions during the duration of the off state (T | 11-29-2012 |
20120302062 | METHOD FOR VIA FORMATION IN A SEMICONDUCTOR DEVICE - A method of via formation in a semiconductor device includes the following steps of providing a photoresist with a photoresist pattern defining an opening of a via, wherein the photoresist comprising a thermally cross-linking material is disposed on a structure layer; dry-etching the structure layer to a first depth through the opening; baking the thermally cross-linking material to reduce the opening; and dry-etching the structure layer to a second depth through the reduced opening, wherein the second depth is greater than the first depth. | 11-29-2012 |
20120302060 | METHOD FOR MANUFACTURING MEMORY DEVICE - The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide. | 11-29-2012 |
20120302049 | METHOD FOR IMPLANTING WAFER - The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different. | 11-29-2012 |
20120302031 | PLASMA ETCHING METHOD AND PLASMA ETCHING APPARATUS FOR PREPARING HIGH-ASPECT-RATIO STRUCTURES - The present invention relates to a plasma etching method and apparatus for preparing high-aspect-ratio structures. The method includes the steps of placing the substrate into a plasma etching apparatus, wherein the plasma etching apparatus includes an upper electrode plate and a lower electrode plate; continuously supplying an upper source RF power and a DC power to the upper electrode plate; and discontinuously supplying a bias RF power to the lower electrode plate. When the bias RF power is switched to the off state, a large amount of secondary electrons pass through the bulk plasma and reach the substrate to neutralize the positive ions during the duration time of the off state (T | 11-29-2012 |
20120299204 | OVERLAY MARK AND METHOD FOR FABRICATING THE SAME - A method for fabricating an overlay mark, including the steps of: forming a patterned layer on a substrate, wherein the patterned layer comprises at least one mark element forming region, wherein each mark element forming region comprises two column recesses and a plurality of row recesses, and the row recesses connect the two column recesses; growing a mark material from the sidewalls of the column recesses and the row recesses so that the mark material merges in the column recesses and the row recesses; and removing the patterned layer. Consequently, an overlay mark including mark elements with high image contrast is fabricated. | 11-29-2012 |
20120295408 | METHOD FOR MANUFACTURING MEMORY DEVICE - The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor. | 11-22-2012 |
20120293196 | TEST KEY STRUCTURE FOR MONITORING GATE CONDUCTOR TO DEEP TRENCH MISALIGNMENT AND TESTING METHOD THEREOF - The disclosure provides a test key structure for monitoring gate conductor to deep trench misalignment and a testing method thereof. The test key structure for monitoring gate conductor to deep trench misalignment includes: a deep trench capacitor structure comprising a plurality of parallel deep trench capacitor lines and a deep trench capacitor connect; a buried strap out-diffusion adjacent to a first side of the deep trench capacitor line; a first gate conductor structure comprising a plurality of parallel first gate conductor lines and a first gate conductor connect, wherein each first gate conductor line is disposed directly over the corresponding deep trench capacitor line; and a second gate conductor structure comprising a plurality of parallel second gate conductor lines and a second gate conductor connect, wherein the first gate conductor lines are electrically connected to each other via the second gate conductor connect, and wherein the first gate conductor lines and the second gate conductor lines are parallel to each other, and the first gate conductor lines and the second gate conductor lines are arranged alternately. | 11-22-2012 |
20120292716 | DRAM STRUCTURE WITH BURIED WORD LINES AND FABRICATION THEREOF, AND IC STRUCTURE AND FABRICATION THEREOF - A DRAM structure with buried word lines is described, including a semiconductor substrate, cell word lines buried in the substrate and separated from the same by a first gate dielectric layer, and isolation word lines buried in the substrate and separated from the same by a second gate dielectric layer. The top surfaces of the cell word lines and those of the isolation word lines are lower than the top surface of the substrate. The bottom surfaces of the isolation word lines are lower than those of the cell word lines. | 11-22-2012 |
20120282777 | METHOD FOR INCREASING ADHESION BETWEEN POLYSILAZANE AND SILICON NITRIDE - A method for increasing adhesion between polysilazane and silicon nitride is disclosed, comprising, providing a substrate comprising a trench, forming a silicon nitride liner layer on a bottom surface and a sidewall of the trench, performing a treating process to the silicon nitride liner layer for producing a hydrophilic surface with OH groups that can increase adhesion between the silicon nitride liner layer and a subsequently formed polysilazane coating layer, and forming a polysilazane coating layer into the trench and on the silicon nitride liner layer. | 11-08-2012 |
20120276731 | METHOD FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; and performing a thermal treating process at 1150-1400° C. for a period of 400-800 milliseconds, to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure. | 11-01-2012 |
20120276730 | METHODS FOR FABRICATING A GATE DIELECTRIC LAYER AND FOR FABRICATING A GATE STRUCTURE - A method for fabricating a gate dielectric layer comprises the steps of: forming a dielectric layer on a semiconductor substrate; performing a nitrogen treating process to form a nitride layer on the dielectric layer; performing an oxygen treating process to implant oxygen into the nitride layer; and performing a thermal treating process to form a gate dielectric layer. A step of forming a gate layer on the gate dielectric layer may be performed to form a gate structure. | 11-01-2012 |
20120276714 | METHOD OF OXIDIZING POLYSILAZANE - A method of oxidizing polysilazane is disclosed, comprising providing a substrate, comprising a trench, forming a polysilazane layer in the trench, and treating the polysilazane layer in an acid containing solution applied with mega-sonic waves to oxidize the polysilazane layer, wherein the acid containing solution comprises phosphoric acid, sulfuric acid, H | 11-01-2012 |
20120276707 | METHOD FOR FORMING TRENCH ISOLATION - A method for forming a trench isolation is disclosed, comprising, providing a substrate comprising a trench, forming a polysilicon layer in the trench, and subjecting the substrate to a treating process to convert the polysilicon layer to an isolating layer, wherein the treating process is fine tuned for the isolating layer on opposite sidewalls of the trench to expand to contact with each other so that the isolating layer fills the trench. | 11-01-2012 |
20120275238 | MEMORY CIRCUIT AND CONTROL METHOD THEREOF - A memory circuit according to one embodiment of the present invention includes a clock driver and an ODT timer. The clock driver is configured to provide a system clock signal based on a root clock signal when the memory circuit is in a read mode, and is configured to stop providing the system clock signal when the memory circuit is not in the read mode. The ODT timer is configured to provide a system ODT signal when the memory circuit is not in the read mode, wherein the transition edge of the system ODT signal is aligned with the transition edge of the root clock signal. | 11-01-2012 |
20120273950 | INTEGRATED CIRCUIT STRUCTURE INCLUDING COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a CuSiN layer and a method for fabricating the same are provided. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer including a CuSiN layer on the copper layer; forming a wetting layer on the barrier layer; and forming an aluminum (Al) layer on the wetting layer. | 11-01-2012 |
20120273948 | INTEGRATED CIRCUIT STRUCTURE INCLUDING A COPPER-ALUMINUM INTERCONNECT AND METHOD FOR FABRICATING THE SAME - An integrated circuit structure including a copper-aluminum interconnect with a barrier layer including a titanium nitride layer and a method for fabricating the same are disclosed. The method for fabricating an integrated circuit structure including a copper-aluminum interconnect according to the present invention comprises the steps of providing a copper (Cu) layer; forming a barrier layer connected to the copper layer, wherein the barrier layer comprises a first layer including a tantalum layer and a tantalum nitride layer and a second layer including a titanium nitride layer, the first layer contacts the copper layer and is disposed between the copper layer and the second layer, and the barrier layer has a recess correspondingly above the copper layer; and forming an aluminum (Al) layer disposed in the recess. | 11-01-2012 |
20120270474 | POLISHING PAD WEAR DETECTING APPARATUS - A polishing pad wear detecting apparatus suitable for a chemical mechanical polishing (CMP) apparatus is provided. The polishing pad wear detecting apparatus includes an arm and a height detector. One end of the arm is fastened on the CMP apparatus. The height detector is disposed on the arm for detecting height variation of a polishing pad. | 10-25-2012 |
20120270411 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N | 10-25-2012 |
20120270408 | MANUFACTURING METHOD OF GATE DIELECTRIC LAYER - A manufacturing method of a gate dielectric layer that includes a nitride layer and an oxide layer is provided. A substrate is provided. A nitridation treatment is performed to form the nitride layer on the substrate. An oxidation treatment is performed subsequent to the formation of the nitride layer to form the oxide layer between the nitride layer and the substrate. | 10-25-2012 |
20120270394 | METHOD OF BEVEL TRIMMING THREE DIMENSIONAL SEMICONDUCTOR DEVICE - A method of bevel trimming a three dimensional (3D) semiconductor device is disclosed, comprising providing a substrate with stack layers thereon and through substrate vias (TSV) therein, wherein an edge of the substrate is curved, performing a bevel trimming step to the curved edge of the substrate for obtaining a planar edge, and thinning the substrate to expose the through substrate vias. | 10-25-2012 |
20120270386 | METHOD FOR PREPARING CONTACT PLUG STRUCTURE - In a further embodiment of the present invention, a method for preparing a contact structure includes the steps of forming a conductive stack on the semiconductor substrate; forming a patterned mask on the conductive stack; forming a depression in an upper portion of the conductive stack; forming a spacer layer on the surface of the depression and the patterned mask; forming a mask block filling the depression; removing a portion of the spacer layer not covered by the mask block; and removing a portion of the conductive stack by using the mask block and the patterned mask to form the contact structure including at least one tall contact plug under the patterned mask and at least one the short contact plug under the mask block. | 10-25-2012 |
20120267760 | CAPACITOR AND MANUFACTURING METHOD THEREOF - A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer. | 10-25-2012 |
20120267727 | METHOD FOR FORMING SELF-ALIGNED CONTACT - An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor. | 10-25-2012 |
20120264359 | MEMBRANE - A membrane is suitable to be mounted on a polishing head of a chemical mechanical polishing apparatus and includes a main portion and an edge portion. The edge portion is located at an edge of the main portion, wherein a first included angle between the main portion and the edge portion is an obtuse angle. | 10-18-2012 |
20120264354 | DISTANCE MONITORING DEVICE - A distance monitoring device is provided. The device is suitable for a chemical mechanical polishing (CMP) apparatus. A polishing head of the CMP apparatus includes a frame and a membrane. The membrane is mounted on the frame, and a plurality of air bags is formed by the membrane and the frame in the polishing head. The distance monitoring device includes a plurality of distance detectors disposed on the frame corresponding to the air bags respectively to set a location of each of the distance detectors on the frame as a reference point, wherein each of the distance detectors is configured to measure a distance between each of the reference points and the membrane. | 10-18-2012 |
20120264300 | METHOD OF FABRICATING SEMICONDUCTOR COMPONENT - A method of fabricating the semiconductor component including following steps is provided. A substrate is provided, wherein an opening is already formed in the substrate. A material layer is formed on the substrate, wherein the material layer fills up the opening, and the material layer outside and above the opening has a recess therein. A sacrifice layer is formed on a surface of the recess. A chemical mechanical polishing (CMP) process is performed to remove the sacrifice layer and the material layer outside the opening, wherein a polishing rate of the CMP process on the material layer is greater than that of the CMP process on the sacrifice layer. | 10-18-2012 |
20120264299 | CHEMICAL MECHANICAL POLISHING METHOD - A chemical mechanical polishing (CMP) method is provided The method is capable of polishing a substrate in a CMP apparatus by using a hydrophobic polishing pad and includes following steps. A first CMP process is performed to the substrate. A first cleaning process is performed to the hydrophobic polishing pad. A second CMP process is performed to the substrate, wherein the first CMP process, the first cleaning process and the second CMP process are performed in sequence. | 10-18-2012 |
20120259445 | METHOD FOR MATCHING ASSISTANT FEATURE TOOLS - A method for matching assistant feature tools includes the steps of: generating an objective assistant feature according to a specific test layout by a first assistant feature tool; generating a compared assistant feature according to the specific test layout by a second assistant feature tool; and determining whether to accept or reject the second assistant feature tool by comparing the compared assistant feature with the objective assistant feature. | 10-11-2012 |
20120258386 | MODEL OF DEFINING A PHOTORESIST PATTERN COLLAPSE RULE, AND PHOTOMASK LAYOUT, SEMICONDUCTOR SUBSTRATE AND METHOD FOR IMPROVING PHOTORESIST PATTERN COLLAPSE - A model of defining a photoresist pattern collapse rule is provided. A portion of the photoresist pattern which corresponds to a second line pattern of a photomask layout is defined as non-collapse if d≧5a and c≧1.5b or if 5a>d≧3a and c≧1.2b, wherein b is the widths of two first line patterns, c is the width of a second line pattern of the photomask layout, and a and d are distances between the second line pattern and the two first line patterns. Accordingly, a photomask layout, a semiconductor substrate and a method for improving photoresist pattern collapse for post-optical proximity correction are also provided. | 10-11-2012 |
20120256298 | MONITORING PATTERN, AND PATTERN STITCH MONITORING METHOD AND WAFER THEREWITH - A monitoring pattern for pattern stitch in double patterning is provided with a plurality of pattern cuts that include at least one line-ended cut and at least one non-line-ended cut, wherein every pattern cut has a stitching critical dimension (CD). A semiconductor wafer having at least one target pattern corresponding to the monitoring pattern is also provided. A method for monitoring pattern stitch can be preformed to check for pattern cut displacement in stitching areas and to increase reliability and printability of layouts, by comparing corresponding stitching critical dimensions of the target pattern and the monitoring pattern. | 10-11-2012 |
20120248518 | ISOLATION STRUCTURE AND DEVICE STRUCTURE INCLUDING THE SAME - An isolation structure is described, including a doped semiconductor layer disposed in a trench in a semiconductor substrate and having the same conductivity type as the substrate, gate dielectric between the doped semiconductor layer and the substrate, and a diffusion region in the substrate formed by dopant diffusion through the gate dielectric from the doped semiconductor layer. A device structure is also described, including the isolation structure and a vertical transistor in the substrate beside the isolation structure. The vertical transistor includes a first S/D region beside the diffusion region and a second S/D region over the first S/D region both having a conductivity type different from that of the doped semiconductor layer. | 10-04-2012 |
20120241865 | INTEGRATED CIRCUIT STRUCTURE - One aspect of the present invention provides an integrated circuit structure including a semiconductor substrate, a bottom dielectric layer positioned on the substrate, at least two capping dielectric layers positioned on the bottom dielectric layer, and a metal layer positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer. Another aspect of the present invention provides an integrated circuit structure including a bottom electrode, a bottom dielectric layer positioned on the bottom electrode, at least two capping dielectric layers positioned on the bottom dielectric layer, and a top electrode positioned on the at least two capping dielectric layers, wherein one of the two capping dielectric layers is an aluminum oxide layer, and the other is a silicon oxide layer. | 09-27-2012 |
20120237858 | PHOTOMASK AND A METHOD FOR DETERMINING A PATTERN OF A PHOTOMASK - The present invention relates to a photomask and a method for determining a pattern of the photomask. The photomask includes a base and a plurality of square areas, wherein the light transmittancy of the square areas is different from that of the base. The square areas are arranged on the base with an array arrangement, and the gaps between adjacent square areas are not even. Whereby, the photomask has better normalized image log-slope (NILS) or depth of focus (DOF). | 09-20-2012 |
20120212273 | SYNCHRONOUS SIGNAL GENERATING CIRCUIT - A synchronous signal generating circuit. The synchronous signal generating circuit includes a delay locked loop (DLL), an emulator and a multiplexer. The DLL is operative to delay a reference clock signal according to a count value to generate a first output clock signal. The count value is generated according to phase difference between the first output clock signal and the reference clock signal. The emulator is operative to provide a function of the DLL and includes a programmable delay line which is operative to receive the reference clock signal and a reference count value, wherein the reference clock signal is delayed according to the reference count value to generate a second output clock signal. The multiplexer is operative to receive the first and second output clock signal and selectively output the first or second output clock signal. The first output clock signal is outputted in a first mode and the second output clock signal is outputted in a second mode. | 08-23-2012 |
20120194273 | DIFFERENTIAL RECEIVER - A differential receiver includes a first amplifying circuit and a second amplifying circuit. The first amplifying circuit comprises a first differential pair of PMOS transistors, a first current source, and a first load resistance section, while the second amplifying circuit comprises a second differential pair of NMOS transistors, a second current source, and a second load resistance section. With the structure of the first and second amplifying circuits, an increased input common mode range can be obtained. | 08-02-2012 |
20120190213 | METHOD FOR FABRICATING DIELECTRIC LAYER WITH IMPROVED INSULATING PROPERTIES - A method for fabricating a dielectric layer with improved insulating properties is provided, including: providing a dielectric layer having a first resistivity; performing a hydrogen plasma doping process to the dielectric layer; and annealing the dielectric layer, wherein the dielectric layer has a second resistivity greater than that of the first resistivity after annealing thereof. | 07-26-2012 |
20120175745 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES USING THE SAME - A method for fabricating a fine pattern of a semiconductor device is provided. The method includes forming a base layer, a first mask pattern having identical features of a first width with inclined sidewalls and a second mask pattern having identical features of a second width in sequence on a substrate, wherein a smallest distance between any two adjacent inclined sidewalls is equal to the second width. The base layer is etched by using the first mask pattern as an etch mask to form first openings of the second width and a fill layer is formed covering the substrate. The second mask pattern is removed to form second openings in the fill layer and then the first mask pattern and the base layer are etched through the second openings to form third openings. The fill layer and the first mask pattern are removed to form a pattern of the base layer having identical features of a third width, wherein the third width of the features of the base layer pattern is equal to the second width. | 07-12-2012 |
20120153373 | GATE STRUCTURE - A gate structure is described, including a dielectric layer, a gate conductive layer and a stacked cap structure. The dielectric layer is disposed between a substrate and the gate conductive layer. The gate conductive layer is disposed between the dielectric layer and the stacked cap structure. The stacked cap structure disposed on the gate conductive layer includes at least two insulating layers having different materials and contacting each other. | 06-21-2012 |
20120149197 | MANUFACTURING METHOD OF DEVICE AND PLANARIZATION PROCESS - A manufacturing method of a device is provided. In the manufacturing method, a substrate is provided. The substrate has a plurality of patterns and a plurality of openings formed thereon, and the openings are located among the patterns. A first liquid supporting layer is formed on the patterns, and the openings are filled with the first liquid supporting layer. The first liquid supporting layer is transformed into a first solid supporting layer. The first solid supporting layer includes a plurality of supporting elements formed in the openings, and the supporting elements are formed among the patterns. A treatment process is performed on the patterns. The first solid supporting layer that includes the supporting elements is transformed into a second liquid supporting layer. The second liquid supporting layer is removed. | 06-14-2012 |
20120149172 | METHOD FOR FABRICATING TRENCH ISOLATION STRUCTURE - A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench. | 06-14-2012 |
20120140193 | DYNAMIC WAFER ALIGNMENT METHOD IN EXPOSURE SCANNER SYSTEM - A dynamic wafer alignment method and an exposure scanner system are provided. The exposure scanner system having a scan path, includes an exposure apparatus, an optical sensor apparatus and a wafer stage. The method comprises the steps of: (a) providing a wafer, having a plurality of shot areas, wherein each shot area has a plurality of alignment marks thereon; (b) forming a photo-resist layer on the wafer; (c) detecting the alignment marks at a portion of a shot area along the scan path by the optical sensor apparatus to obtain compensation data for wafer alignment of the portion of the shot area; (d) performing real time feedback of the compensation data for wafer alignment to the wafer stage; (e) exposing the photo-resist layer at the portion of the shot area along the scan path; (f) continuously repeating the steps (c) to (e) at the shot area along the scan path until all of the photo-resist layer at the shot area are exposed; and (g) repeating the step (f) until the photo-resist layer of all of the shot areas on the wafer are exposed. | 06-07-2012 |
20120126394 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR PREPARING THE SAME - An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer. | 05-24-2012 |
20120068719 | MEASURED DEVICE AND TEST SYSTEM UTILIZING THE SAME - A measured device coupled to test equipment providing at least two test factors and receiving a test result is disclosed. The measured device includes a combinatorial logic circuit and a main circuit. The combinatorial logic circuit includes a first storage module and a second storage module. The first storage module stores the test factors according to a first operation clock. The second storage module stores and outputs at least two output factors according to a second operation clock. The frequency of the second operation clock is higher than the frequency of the first operation clock. When the test factors are stored in the first storage module, the test factors stored in the first storage module are served as the output factors and the output factors are output and stored in the second storage module. The main circuit generates the test result according to the output factors output by the second storage module. The test equipment obtains information as to whether the main circuit is normal according to the test result. | 03-22-2012 |
20120056301 | STACK CAPACITOR OF MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates. | 03-08-2012 |
20120056265 | SEMINCONDUCTOR DEVICE AND FABRICATIONS THEREOF - A semiconductor device is disclosed, including a substrate, a fin type semiconductor layer disposed on the substrate, a gate dielectric layer disposed on a top and sidewalls of the fin type semiconductor layer, a metal nitride layer disposed on the gate dielectric layer, and an aluminum doped metal nitride layer disposed on the metal nitride layer. In an embodiment of the invention, the metal nitride layer is a titanium nitride layer and the aluminum doped metal nitride layer is an aluminum doped titanium nitride layer. | 03-08-2012 |
20120038052 | SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF - A fabricating method of a semiconductor device is provided. Pillars are formed on a substrate. A first oxide layer is continuously formed on upper surfaces and side walls of the pillars by non-conformal liner atomic layer deposition. The first oxide layer continuously covers the pillars and has at least one first opening. The first oxide layer is partially removed to expose the upper surfaces of the pillars, and a first supporting element is formed on the side wall of each of the pillars. The first supporting element is located at a first height on the side wall of the corresponding pillar and surrounds the periphery of the corresponding pillar. The first supporting elements around two adjacent pillars are connected and the first supporting elements around two opposite pillars do not mutually come into contact and have a second opening therebetween. | 02-16-2012 |
20120032339 | INTEGRATED CIRCUIT STRUCTURE WITH THROUGH VIA FOR HEAT EVACUATING - An integrated circuit structure includes a semiconductor substrate, an active device disposed on a first region of the semiconductor substrate, a layer stack disposed on a second region of the semiconductor substrate, a through via penetrating through the layer stack and the semiconductor substrate, and a third dielectric layer disposed between the through via and the semiconductor substrate. In one embodiment of the present invention, the layer stack includes a first dielectric layer disposed on the semiconductor substrate and a heat-conducting member disposed on the first dielectric layer. | 02-09-2012 |
20110317483 | Data Programming Circuits and Memory Programming Methods - A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data. | 12-29-2011 |
20110291255 | CARRIER FOR CHIP PACKAGES - A carrier for holding a plurality of chip packages and a carrier assembly are provided, wherein the chip package has a central area without solder balls and a peripheral area with solder balls formed thereon. The carrier includes a tray component and a plurality of supports disposed on the tray component, wherein each support holds the central area of a respective chip package. The carrier assembly is formed by stacking a plurality of the carriers through a plurality of peripheral projections disposed at a periphery of each tray component, wherein each peripheral projection has a pin formed thereon and a hole formed thereunder. | 12-01-2011 |
20110226736 | METHOD OF PATTERNING METAL ALLOY MATERIAL LAYER HAVING HAFNIUM AND MOLYBDENUM - A method of patterning a metal alloy material layer having hafnium and molybdenum. The method includes forming a patterned mask layer on a metal alloy material layer having hafnium and molybdenum on a substrate. The patterned mask layer is used as a mask and an etching process is performed using an etchant on the metal alloy material layer having hafnium and molybdenum so as to form a metal alloy layer having hafnium and molybdenum. The etchant includes at least nitric acid, hydrofluoric acid and sulfuric acid. The patterned mask layer is removed. | 09-22-2011 |
20110222030 | IMMERSION LITHOGRAPHIC APPARATUSES - Apparatuses for specially designed gradient immersion lithography are presented. The gradient immersion lithographic apparatus includes a radiation system providing a patterned beam of radiation, a substrate table with a substrate structure held thereon, a projection system with an optical lens element arranged to project the patterned beam of radiation onto the substrate structure, multiple layers of media of gases, liquids, or liquid crystals partitioned by moveable plates arranged in sequence between the projection system and the substrate structure, and a controller for displacement of the moveable plates to adjust relative thicknesses of the multiple layers of media. | 09-15-2011 |
20110159652 | FABRICATING METHOD OF VERTICAL TRANSISTOR - A substrate is provided. A pillar protruding out of a surface of the substrate is already formed on the substrate, and a patterned layer is already formed on the pillar. The pillar includes a lower part, a channel region, and an upper part from bottom to top, and the lower part has a first doped region. A gate dielectric layer is formed on a sidewall at one side of the pillar. A surrounding gate is formed on the gate dielectric layer located on the channel region, and a base line electrically connected to the channel region is formed on a sidewall at the other side of the pillar. A second doped region is formed in the upper part of the pillar. | 06-30-2011 |
20110147887 | STACK CAPACITOR OF MEMORY DEVICE AND FABRICATION METHOD THEREOF - The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates. | 06-23-2011 |
20110097899 | METHOD OF FORMING FUNNEL-SHAPED OPENING - A method of forming a funnel-shaped opening is provided. First, a substrate is provided, wherein a conductive layer is formed on the substrate. Then, a dielectric layer is formed over the conductive layer. Further, a first opening is formed in the dielectric layer, wherein the first opening exposes the conductive layer. Thereafter, a portion of the dielectric layer at a top corner of the first opening is removed to form a second opening by an etching gas containing argon in a reaction chamber, wherein a power of the reaction chamber is about 500˜1800 W. | 04-28-2011 |
20110087359 | INTEGRATED CIRCUITS MODELING MANUFACTURING PROCEDURE AND MANUFACTURING SYSTEM UTILIZING THE SAME - An ICs modeling manufacturing procedure is disclosed. A first pattern is printed on a first surface of a printed circuit board (PCB). The first pattern includes a first barcode and a plurality of production codes. A plurality of elements are disposed on the first surface of the PCB. The PCB is heated to fix the elements on the first surface and secure the first pattern on the first surface of the PCB. When the first pattern is read, a first production information is obtained. | 04-14-2011 |
20110084720 | TEST APPARATUS FOR ELECTRONIC DEVICE PACKAGE AND METHOD FOR TESTING ELECTRONIC DEVICE PACKAGE - A test apparatus for an electronic device package is provided, which includes a test socket having a first portion with a recess for receiving an electronic device package having external terminals arranged in a terminal configuration and a second portion. An interchangeable insert board is disposed between the first portion and the second portion and extended on the recess, which includes first contact pads arranged in a first pad configuration compatible with the terminal configuration and facing the recess and second contact pads arranged in a second pad configuration and disposed between the first and the second portions. Trace layers each electrically connects one of the first contact pads to one of the second contact pads. The contact pins each penetrates through the second portion and electrically connects to one of the second pads, wherein the contact pins are arranged in a pin configuration compatible with the second pad configuration. | 04-14-2011 |
20110084248 | CROSS POINT MEMORY ARRAY DEVICES - Cross point memory arrays with CBRAM and RRAM stacks are presented. A cross point memory array includes a first group of substantially parallel conductive lines and a second group of substantially parallel conductive lines, oriented substantially perpendicular to the first group of substantially parallel conductive lines. An array of memory stack is located at the intersections of the first group of substantially parallel conductive lines and the second group of substantially parallel conductive lines, wherein each memory stack comprises a conductive bridge memory element in series with a resistive-switching memory element. | 04-14-2011 |
20110081618 | LITHO-LITHO ETCH (LLE) DOUBLE PATTERNING METHODS - Litho-litho-etch double patterning (LLE-DP) methods using silylation freeze technology are presented. The LLE-DP method using a silylation freeze reaction comprises providing a substrate with a first photoresist layer thereon. A first exposure process is performed defining a first latent image in a first photoresist. The first patterned structures on the substrate is developed and baked for photo-generated acid diffusion. The photo-generated acid is reacted with a silylation agent to freeze the first patterned structures. A second photoresist layer is formed overlying the substrate. A second lithography process is performed to create second patterned structures on the substrate. The first patterned structures and the second patterned structures are interlaced each other. | 04-07-2011 |
20110079823 | VERTICAL TRANSISTOR AND ARRAY OF VERTICAL TRANSISTOR - A vertical transistor includes a substrate, a gate, a source region, a drain region, a channel region and a gate dielectric layer. A trench is formed in the substrate, and the gate is disposed in the trench. The source region is disposed in the substrate beneath the gate. The drain region is disposed above the gate. The channel region is disposed at two sides of the gate and located between the source region and the drain region. The gate dielectric layer is located between the gate and the channel region. | 04-07-2011 |
20110068805 | SENSING CIRCUIT FOR SENSING ELECTRIC FUSE AND SENSING METHOD THEREOF - A sensing circuit for sensing an electric fuse and a sensing method thereof are provided. The sensing circuit includes a capacitor, a detection circuit, and an output circuit. The capacitor is coupled to the electric fuse. The detection circuit is coupled to the capacitor and the electric fuse. The detection circuit controls the capacitor to discharge according to a pulse width and a present resistance value of the electric fuse so as to generate a detection voltage. The output circuit is coupled to the detection circuit. The output circuit outputs a state of the electric fuse according to the detection voltage and a reference voltage. | 03-24-2011 |
20110059622 | SEMICONDUCTOR MANUFACTURING PROCESS - A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer. | 03-10-2011 |
20110004703 | ILLEGAL COMMAND HANDLING - A circuit for handling an illegal command embodies a control decode stage, illegal command handling stage and an output stage. The control decode circuit receives a clock signal, receives and decodes an external command, and latches the decoded external command based on the clock signal to generate a first signal. The first device is coupled to the control decode circuit for receiving the first signal, receives a second signal indicating whether the illegal command is detected in the external command, and generates a third signal based on the first and the second signals. The output circuit is coupled to the first device, receives the clock signal and the third signal, and generates a first output based on the clock signal and the third signal. If there is an illegal command, then there will be no control output generated. On the other hand, in the absence of an illegal command a control output will be generated. | 01-06-2011 |
20100323521 | PATTERNING METHOD - A patterning method has a mask layer and undoped patterns sequentially formed on a target layer. A doping process is performed to surfaces of the undoped patterns to form doped patterns from the surfaces of the undoped patterns. A material is filled in the gaps between the doped patterns. A portion of the doped patterns are then removed to expose the top surfaces of the remaining undoped patterns. The material and the exposed undoped patterns are removed. A portion of the mask layer is removed using the remaining doped patterns as a mask to form a first pattern on the mask layer. A portion of the target layer is removed using the mask layer having the first pattern thereon as a mask so as to form on the target layer a second pattern complementary to the first pattern. | 12-23-2010 |
20100317194 | METHOD FOR FABRICATING OPENING - A method for fabricating openings is provided. A dielectric layer is formed on a substrate, and a first patterned mask layer is formed on the dielectric layer along a first direction. A second patterned mask layer is then formed on the dielectric layer along a second direction which intersects with the first direction. A portion of the dielectric layer is removed using the first patterned mask layer and the second patterned mask layer as a mask so as to from the openings. The dielectric layer, the first patterned mask layer and the second patterned mask layer have different etching selectivities. | 12-16-2010 |
20100310790 | METHOD OF FORMING CARBON-CONTAINING LAYER - A method of forming a carbon-containing layer is provided. First, a substrate having a target layer thereon is provided. Next, a plasma containing C | 12-09-2010 |
20100279472 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY - In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions. | 11-04-2010 |
20100213432 | PHASE CHANGE MEMORY DEVICE AND FABRICATION THEREOF - A method for forming a phase change memory device is disclosed. A substrate with a bottom electrode thereon is provided. A heating electrode and a dielectric layer are formed on the bottom electrode, wherein the heating electrode is surrounded by the dielectric layer. The heating electrode is etched to form recess in the dielectric layer. A phase change material is deposited on the dielectric layer, filling into the recess. The phase change material is polished to remove a portion of the phase change material exceeding the surface of the dielectric layer and a phase change layer is formed confined in the recess of the dielectric layer. A top electrode is formed on the phase change layer and the dielectric layer. | 08-26-2010 |
20100203693 | MANUFACTURING METHOD OF DYNAMIC RANDOM ACCESS MEMORY - A manufacturing method of DRAM is provided. A substrate having a deep trench is provided, and then a deep trench capacitor including a bottom electrode, an upper electrode and a capacitor dielectric layer is formed in the deep trench. A part of the upper electrode of the deep trench capacitor is removed to form a first trench. A buried strap is formed in the substrate on one side of the upper electrode. An isolation structure is formed in the first trench to define an active region. A part of the substrate adjacent to the isolation structure is removed to form a second trench. A first heavily doped region is formed on the bottom of the second trench, and the first heavily doped region is electrically connected to the buried strap. A dielectric layer is formed on the bottom of the second trench. | 08-12-2010 |
20100200903 | NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench. | 08-12-2010 |
20100192009 | OPERATION METHOD OF SUPPRESSING CURRENT LEAKAGE IN A MEMORY AND ACCESS METHOD FOR THE SAME - A method for suppressing current leakage in a memory includes a column redundancy evaluation which is executed when a memory is powered on so as to find out a failed memory unit of the memory. A current path between the failed memory unit and a pre-charging power source is disconnected according to the column redundancy evaluation result. Thus, bit lines in the failed memory cells are not pre-charged to avoid current leakage occurred between bit lines and word lines in the failed memory cells. | 07-29-2010 |
20100165722 | Phase Change Memory - A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein. | 07-01-2010 |
20100165720 | VERIFICATION CIRCUITS AND METHODS FOR PHASE CHANGE MEMORY ARRAY - A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state | 07-01-2010 |
20100163828 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A phase change memory device is provided, including a semiconductor substrate with a first conductive semiconductor layer disposed thereover, wherein the first conductive semiconductor layer has a first conductivity type. A first dielectric layer is disposed over the semiconductor substrate. A second conductive semiconductor layer having a second conductivity type opposite to the first conductivity type is disposed in the first dielectric layer. A heating electrode is disposed in the first dielectric layer and formed over the second conductive semiconductor layer, wherein the heating electrode has a tapered cross section and includes metal silicide. A second dielectric layer is disposed over the first dielectric layer. A phase change material layer is disposed in the second dielectric layer. An electrode is disposed over the second dielectric layer, covering the phase change material layer. | 07-01-2010 |
20100133608 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - An embodiment of the invention provides a method for forming a semiconductor device comprising providing a substrate with a pad layer formed thereon. The pad layer and the substrate are patterned to form a plurality of trenches. A trench top insulating layer is formed in each trench. Wherein the trench top insulating layer protrudes from the substrate and has an extension portion extending to the pad layer. The pad layer and the substrate are etched by using the trench top insulating layers and the extension portions as a mask to form a recess in the substrate. And a recess gate is formed in the recess. | 06-03-2010 |
20100117050 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with an electrically isolated conductor is provided. The phase-change memory element includes: a first electrode and a second electrode; a phase-change material layer electrically connected to the first electrode and the second electrode; and at least two electrically isolated conductors, disposed between the first electrode and the second electrode, directly contacting the phase-change material layers. | 05-13-2010 |
20100102361 | VERTICAL TRANSISTOR AND FABRICATING METHOD THEREOF AND VERTICAL TRANSISTOR ARRAY - A vertical transistor including a substrate, a gate, a base line and a gate dielectric layer is provided. The substrate includes a pillar protruding out of a surface of the substrate. The pillar includes a first doped region, a channel region and a second doped region from bottom to top. The gate is disposed on a sidewall at one side of the channel region. The base line is disposed on a sidewall at the other side of the channel region and not contacted with the gate. The gate dielectric layer is disposed between the gate and the channel region. | 04-29-2010 |
20100097854 | FLASH MEMORY AND FLASH MEMORY ARRAY - A flash memory including a substrate having a recess, a buried bit line, a word line, a single side insulating layer, a floating gate, a tunneling dielectric layer, a control gate, and an inter-gate dielectric layer is provided. The buried bit line extends below the recess of the substrate along a first direction. The word line is on the substrate, and extends above the recess along a second direction. The single side insulating layer is on a first sidewall of the recess. The floating gate is on a second sidewall of the recess to be opposite to the single side insulating layer. The tunneling dielectric layer is sandwiched by the floating gate and the substrate to contact the buried bit line. The control gate fills the recess and contacts the word line. The inter-gate dielectric layer is sandwiched by the control gate and the floating gate. | 04-22-2010 |
20100097596 | SCANNING EXPOSURE METHOD - A scanning exposure method is provided. A mask and a substrate are oppositely moved along a direction. The mask and the substrate are moved in at least two different uniform relative velocities during a one shot exposure, thus producing an exposed shot area of an expected size on the substrate. | 04-22-2010 |
20100062604 | METHOD FOR FABRICATING DEVICE PATTERN - A method for fabricating a device pattern includes the following steps. A first pattern having a first density is formed in a pre-determined region on a substrate. The first pattern includes a base portion along a first direction and at least two protruding portions along a second direction and connected to the base portion. A spacer is formed on a sidewall of each protruding portion. The spacers are free of connecting with the base portion, and the spacers between two adjacent protruding portions are free of connecting with each other, so as to form a gap between the two adjacent protruding portions. Then, a second pattern is formed on the substrate and located in the gap, such that a third pattern having a second density is defined in the pre-determined region by the first pattern and the second pattern. | 03-11-2010 |
20100047960 | METHOD OF FABRICATING A PHASE-CHANGE MEMORY - A phase-change memory comprises a bottom electrode formed on a substrate. A first isolation layer is formed on the bottom electrode. A top electrode is formed on the isolation layer. A first phase-change material is formed in the first isolation layer, wherein the top electrode and the bottom electrode are electrically connected via the first phase-change material. Since the phase-change material can have a diameter less than the resolution limit of the photolithography process, an operating current for a state conversion of the phase-change material pattern may be reduced so as to decrease a power dissipation of the phase-change memory device. | 02-25-2010 |
20100038709 | VERTICAL TRANSISTOR AND ARRAY WITH VERTICAL TRANSISTORS - A vertical transistor includes a substrate, a semiconductor structure, a gate, a gate dielectric layer, and a conductive layer. The semiconductor structure is disposed on the substrate and includes two vertical plates and a bottom plate. The bottom plate has an upper surface connected to bottoms of the two vertical plates and a bottom surface connected to the substrate. The gate surrounds the semiconductor structure to fill between the two vertical plates, and the gate is disposed around the two vertical plates. The gate dielectric layer is sandwiched in between the gate and the semiconductor structure, and the conductive layer is disposed on the semiconductor structure and electrically connected with tops of the two vertical plates. | 02-18-2010 |
20100022065 | DEEP TRENCH DEVICE WITH SINGLE SIDED CONNECTING STRUCTURE AND FABRICATION METHOD THEREOF - A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed. | 01-28-2010 |
20100006814 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory cell is proposed. The phase-change memory includes a bottom electrode; a phase-change spacer formed to contact the bottom electrode; an electrical conductive layer having a vertical portion and a horizontal portion, wherein the electrical conductive layer electrically connects to the phase-change spacer via the horizontal portion; and a top electrode electrically connected to the electrical conductive layer via the vertical portion of the electrically conductive layer. | 01-14-2010 |
20090296450 | Memory And Writing Method Thereof - A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level. | 12-03-2009 |
20090294750 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - An exemplary phase change memory device is provided, including a substrate with a first electrode formed thereover. A first dielectric layer is formed over the first electrode and the substrate. A plurality of cup-shaped heating electrodes is respectively disposed in a portion of the first dielectric layer. A first insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A second insulating layer is formed over the first dielectric layer, partially covering the cup-shaped heating electrodes and the first dielectric layer therebetween. A pair of phase change material layers is respectively disposed on opposing sidewalls of the second insulating layer and contacting with one of the cup-shaped heating electrodes. A pair of first conductive layers is formed on the second insulating layer along the second direction, respectively. | 12-03-2009 |
20090289649 | TESTER WITH LOW SIGNAL ATTENUATION - A tester with low signal attenuation and suitable for measuring an electrical characteristic of a subject to be tested includes a circuit board and a first probe. The circuit board has a first surface and a second surface respectively having a first signal transmission line and a second signal transmission line. The first probe has a contact end contacting the subject to be tested and a first signal end and a second signal end respectively connecting the first signal transmission line and the second signal transmission line. The first probe receives a testing signal from the first signal transmission line through the first signal end and transmits the testing signal from the contact end to the subject to be tested, such that the subject to be tested generates a response signal, and the first probe transmits the response signal to the second signal transmission line through the second signal end. | 11-26-2009 |
20090259820 | OPERATION METHOD FOR MEMORY - An operation method for a memory is provided. When the memory is under a reset mode, a main data line (MDQ) and a local data line (LDQ) of the memory is forced to be a logic high level. Then, the memory cells in the memory are turned on by choosing corresponding column selection lines (CSL) and corresponding word lines of the memory. Finally, the turned on memory cells are reset after the logic high level of the main data line and the local data line is written into the turned on memory cells. | 10-15-2009 |
20090257262 | DRAM AND MEMORY ARRAY - A dynamic random access memory (DRAM) includes a substrate, a plurality of bit lines, a plurality of word lines, a plurality of recess channels, a plurality of conductive plugs and a plurality of trench capacitors. In the DRAM, the bit lines are disposed on the substrate in a first direction, and the word lines are disposed on the bit lines in a second direction. Each recess channel is in the substrate between two bit lines below the word line, and each conductive plug connects each recess channel and the word lines. Each trench capacitor is disposed in the substrate between two bit lines where the recess channels are not formed. Because the word lines can be electrically connected with the recess channels directly without using an additional chip area, the WL access time can be accelerated without an increase of the chip size. | 10-15-2009 |
20090251979 | METHOD FOR SUPPRESSING CURRENT LEAKAGE IN MEMORY - A method for suppressing a current leakage of a memory is provided. The memory at least includes a memory cell, an equalizing circuit, a current limiter, a word line and a pair of complementary bit lines. The method includes: having the memory cell entering a pre-charging mode; having the equalizing circuit and the current limiter being normally operated, so as for pre-charging the pair of complementary bit lines; applying a periodic control signal to the current limiter for controlling the current limiter to be either conducting or non-conducting, in which when the current limiter is non-conducting, a standby current leakage of the memory is suppressed, in which the standby current leakage is caused by a short circuit between the word line and the pair of complementary bit lines. | 10-08-2009 |
20090250822 | MULTI-CHIP STACK PACKAGE - A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip. | 10-08-2009 |
20090250691 | PHASE CHANGE MEMORY ELEMENT AND METHOD FOR FORMING THE SAME - A phase change memory and method for fabricating the same are provided. The phase change memory element includes: a substrate; rectangle-shaped dielectric patterns formed on the substrate and parallel with each other; electric conductive patterns partially covering a first sidewall and the top surface of the dielectric pattern and the substrate to expose the first sidewall and a second sidewall of the dielectric pattern, wherein the electric conductive patterns covering the same dielectric pattern are apart from each other; a phase change spacer formed on the substrate and directly in contact with the exposed first and second sidewalls of the dielectric patterns, wherein the two adjacent electric conductive patterns covering the same dielectric pattern are electrically connected by the phase change spacer; and a dielectric layer formed on the substrate. | 10-08-2009 |
20090191367 | MEMORY DEVICES, STYLUS-SHAPED STRUCTURES, ELECTRONIC APPARATUSES, AND METHODS FOR FABRICATING THE SAME - An exemplary hollow stylus-shaped structure is disclosed, including a hollow column spacer formed over a base layer and a hollow cone spacer stacked over the hollow column spacer, wherein the hollow cone spacer, the hollow column spacer, and the base layer form a space, and sidewalls of the hollow cone spacer and the hollow column spacer are made of silicon-containing organic or inorganic materials. | 07-30-2009 |
20090189142 | Phase-Change Memory - A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact. | 07-30-2009 |
20090189140 | PHASE-CHANGE MEMORY ELEMENT - A phase-change memory element with side-wall contacts is disclosed. The phase-change memory element comprises a bottom electrode. A first dielectric layer is formed on the bottom electrode. A first electrical contact is formed on the first dielectric layer and electrically connects to the bottom electrode. A second dielectric layer is formed on the first electrical contact. A second electrical contact is formed on the second dielectric layer, wherein the second electrical contact comprises an outstanding terminal. An opening passes through the second electrical contact, the second dielectric layer, and the first electrical contact. A phase-change material occupies at least one portion of the opening. A third dielectric layer is formed on and covers the second electrical contact, exposing a top surface of outstanding terminal. A top electrode is formed on the third dielectric layer, contacting the outstanding terminal. | 07-30-2009 |
20090175102 | METHOD FOR CONTROLLING ACCESS OF A MEMORY - A memory access control method is provided. By decoding a read-write command, a mode register set (MRS) signal is generated. When the MRS signal is enabled, a latch outputs a bank-select signal. The bank-select signal is then decoded to generate a register-select signal. Then, an address signal is written into a register selected by the register-select signal. The value of a certain register can be used to determine whether to enable the error check function. Thus, the next generation memory structure with the CRC function can be compatible with the conventional memory structure. | 07-09-2009 |
20090168579 | RANDOM ACCESS MEMORY DATA RESETTING METHOD - A random access memory data resetting method is provided. The method includes following steps. First, a state machine resetting signal is provided to a RAM. Next, the state machine resetting signal is extended for a predetermined time period. Afterwards, a data resetting operation is executed in the RAM within the predetermined time period. | 07-02-2009 |
20090166847 | SEMICONDUCTOR CHIP PACKAGE - A semiconductor chip package is provided. The semiconductor chip package comprises a package substrate having a first surface and a second surface opposite to the first surface. A through hole extends through the package substrate. A semiconductor chip is disposed on the first surface of the package substrate, wherein a bottom surface of the semiconductor chip covers one end of the through hole. At least two bonding fingers are disposed on the second surface of the package substrate and arranged on sides of the through hole. A conductive line is disposed on the second surface of the package substrate and between the two bonding fingers and the through hole, wherein two terminals of the conductive line are electrically connected to the two bonding fingers, respectively. | 07-02-2009 |
20090166703 | MEMORY DEVICE WITH A LENGTH-CONTROLLABLE CHANNEL - A memory device is provided. The memory device includes a substrate, a trench having an upper portion and a lower portion formed in the substrate, a trench capacitor formed in the lower portion of the trench, a collar dielectric layer formed on a sidewall of the trench capacitor and extending away from a top surface of the substrate, a first doping region formed on a side of the upper portion of the trench in the substrate for serving as source/drain, a conductive layer formed in the trench and electrically connected to the first doping region, a top dielectric layer formed on conductive layer, a gate formed on the top dielectric layer, an epitaxy layer formed on both sides of the gate and on the substrate and a second doping area formed on a top of the epitaxy layer for serving as source/drain. | 07-02-2009 |
20090155733 | METHOD OF FORMING ISO SPACE PATTERN - A method of forming an iso space pattern is provided. In the method, a first material layer is provided, and then a second material layer and a patterned material layer are formed thereon. After that, a first patterned photoresist layer is formed on the patterned material layer to partially cover the patterned material layer and to partially expose the patterned material layer, and the second material layer is then partially removed by using the first patterned photoresist layer and the patterned material layer as a mask. Afterwards, the iso space pattern constituted by the etched second material layer is formed after the first patterned photoresist layer and the patterned material layer are removed. Due to twice photolithography and etching processes, it is likely to form the relatively narrow iso space pattern with use of existing photolithography equipments according to the method. | 06-18-2009 |
20090148993 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING A RECESS CHANNEL STRUCTURE THEREIN - A method of fabricating a semiconductor device having a recess channel structure is provided. A first recess is formed in a substrate. A liner and a filling layer are formed in the first recess. A portion of the substrate adjacent to the first recess and a portion of the liner and the filling layer are removed to form trenches. An insulation layer fills the trenches to form isolation structures. The filling layer is removed, using the liner as an etching stop layer, to expose the insulation layer. A portion of the exposed insulation layer is removed to form a second recess having divots adjacent to the sidewalls of the substrate. The liner is removed. A dielectric layer and a gate are formed over the substrate covering the second recess. Source and drain regions are formed in the substrate adjacent to the second recess. | 06-11-2009 |
20090148980 | METHOD FOR FORMING PHASE-CHANGE MEMORY ELEMENT - A method for forming a phase-change memory element. The method includes providing a substrate with an electrode formed thereon; sequentially forming a conductive layer and a first dielectric layer on the substrate; forming a patterned photoresist layer on the first dielectric layer; subjecting the patterned photoresist layer to a trimming process, remaining a photoresist pillar; etching the first dielectric layer with the photoresist pillar as etching mask, remaining a dielectric pillar; comformally forming a first phase-change material layer on the conductive layer and the dielectric pillar to cover the top surface and side walls of the dielectric pillar; forming a second dielectric layer to cover the first phase-change material layer; subjecting to the second dielectric layer and the first phase-change material layer to a planarization until exposing the top surface of the dielectric pillar; and forming a second phase-change material layer on the second dielectric layer. | 06-11-2009 |
20090147607 | RANDOM ACCESS MEMORY AND DATA REFRESHING METHOD THEREOF - A random access memory and a data refreshing method thereof are provided. The random access memory includes a memory array having a plurality of word lines; a control logic unit which is used for outputting a refreshment indicating signal, a thermal sensor which is used for outputting a temperature indicating signal; a refresh counter which is used for outputting a row address counting signal; and a row address decoder which is used for performing a decoding operation on the row address counting signal in response to the refreshment indicating signal and the temperature indicating signal, and simultaneously enabling the plurality of word lines of the memory array based on a result of the decoding operation. | 06-11-2009 |
20090147566 | Phase Change Memory And Control Method Thereof - A phase change memory wherein several phase change storage elements are coupled in series to share a single current source. The current provided by the current source is directed by a plurality of switches. To write/read the phase change storage elements, the invention provides techniques to control the current value generated by the current source and controls the states of the switches. The impedance summation of the phase change storage elements vary with the data stored therein. | 06-11-2009 |
20090146283 | STACKED-TYPE CHIP PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF - A stacked-type chip package structure in which stacked chips and stacked flexible circuit boards are disposed on a substrate. A plurality of spacer layers is respectively sandwiched between two adjacent chips and stacked on top of each other. In addition, conductive bumps are disposed on the substrate and between the stacked flexible circuit boards, such that the stacked flexible circuit boards are electrically connected to the substrate. Besides, conductive wires are electrically connected between the flexible circuit boards and the chips, so as to form a package structure with multi-layer chips on the substrate. Thereby, electrical performance and reliability of the chips are improved. | 06-11-2009 |
20090146127 | PHASE CHANGE MEMORY - Phase change memories comprising a top electrode, a phase change element, a plurality of via holes allocated between the top electrode and the phase change element, at least four heaters aiming at different regions of the phase change element, and a plurality of bottom electrodes and transistors corresponding to the heaters. The bottom electrodes are respectively coupled to the heaters. Regarding the transistors, their first terminals are respectively coupled to the bottom electrodes, their control terminals are used for coupling to word lines, and their second terminals are used for coupling to bit lines. In an embodiment with four heaters, the regions the heaters aimed at the phase change element form a 2×2 storage array. | 06-11-2009 |
20090146101 | ETCHANT FOR METAL ALLOY HAVING HAFNIUM AND MOLYBDENUM - An etchant for etching a metal alloy having hafnium and molybdenum includes 20 to 80 percent by weight of nitric acid, 1 to 49 percent by weight of hydrofluoric acid, 1 to 96 percent by weight of sulfuric acid, and 1 to 30 percent by weight of water, based on the total weight of the etchant. | 06-11-2009 |
20090141548 | MEMORY AND METHOD FOR DISSIPATION CAUSED BY CURRENT LEAKAGE - Memories with low power consumption and methods for suppressing current leakage of a memory. The memory cell of the memory has a storage element and a transistor coupled in series. The invention sets a voltage across the transistor approaching to zero when the memory is not been accessed. | 06-04-2009 |
20090135645 | Data Programming Circuits And Memory Programming Methods - A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data. | 05-28-2009 |
20090127610 | NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF - A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions. | 05-21-2009 |
20090122599 | WRITING SYSTEM AND METHOD FOR PHASE CHANGE MOMORY - An embodiment of a writing system for a phase change memory based on a present application is disclosed. The writing system comprises a first phase change memory (PCM) cell, a second PCM cell, a first writing circuit and a verifying circuit. The first writing circuit executes a writing procedure, receives and writes a first data to the first PCM cell. The verifying circuit executes a verifying procedure and the circuit further comprises a processing unit and a second writing circuit. The processing unit reads and compares the data stored in the second PCM cell with a second data. The second writing circuit writes the second data to the second PCM cell when the data stored in the second PCM cell and the second data are not matched. | 05-14-2009 |
20090111060 | EXPOSURE METHOD - An exposure method suitable for a photolithography process is described. First, a wafer with a group of alignment marks formed thereon is provided. A first alignment step is conducted by using the group of the alignment marks on the wafer to obtain a first calibration data. Next, a second alignment step is conducted by using a portion of the group of alignment marks on the wafer to obtain a second calibration data. The first calibration data is then compared with the second calibration data to obtain a comparison result. Next, a photoresist exposure step is conducted on the wafer according to the comparison result. | 04-30-2009 |
20090108321 | FLASH MEMORY - A flash memory is provided. The flash memory includes a substrate, a first insulation layer formed on the substrate, a control gate disposed on the first insulation layer, and two floating gates coplanar with the substrate respectively disposed on both sides of the control gate. | 04-30-2009 |
20090108319 | DRAM STACK CAPACITOR AND FABRICATION METHOD THEREOF - A DRAM stack capacitor and a fabrication method thereof has a first capacitor electrode formed of a conductive carbon layer overlying a semiconductor substrate, a capacitor dielectric layer and a second capacitor electrode. The first capacitor electrode is of crown shape geometry and possesses an inner surface and an outer surface. The DRAM stack capacitor features the outer surface of the first capacitor electrode as an uneven surface. | 04-30-2009 |