| NANYA TECHNOLOGY CORP. Patent applications |
| Patent application number | Title | Published |
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| 20120126412 | INTEGRATED CIRCUIT DEVICE AND METHOD OF FORMING THE SAME - An integrated circuit device includes a semiconductor substrate having a first region and second region, a conductive via positioned in the first region of the semiconductor substrate, at least one active element positioned in the second region of the semiconductor substrate, a conductive layer extending from the first region to the second region and electrically connecting the conductive via to the active element, and an auxiliary structure positioned in the first region of the semiconductor substrate and proximate to the conductive via. The auxiliary structure can be a stress-absorbing structure, and the volume of the stress-absorbing structure decreases as the volume of the conductive via increases. The auxiliary structure can be a heat-evacuating structure, and the heat-evacuating structure is configured to transfer the operating heat generated by the active element from the first region of the semiconductor substrate to the conductive via through the conductive layer. | 05-24-2012 |
| 20120119355 | INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming an integrated circuit structure comprises the steps of: providing a semiconductor substrate having a first side and a second side opposite the first side; forming a hole extending from the first side of the semiconductor substrate into the semiconductor substrate; filling the hole with conductive material; thinning the second side of the semiconductor substrate to a first predetermined thickness, so that the bottom of the hole does not protrude from the second side of the semiconductor substrate; and etching the second side of the semiconductor to substrate to a second predetermined thickness, thereby exposing the bottom of the hole. | 05-17-2012 |
| 20120119277 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region. | 05-17-2012 |
| 20120119276 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory device includes a mesa structure and a word line. The mesa structure, having two opposite side surfaces, includes at least one pair of source/drain regions and at least one channel base region corresponding to the pair of source/drain regions formed therein. The word line includes two linear sections and at least one interconnecting portion. Each linear section extends on the respective side surface of the mesa structure, adjacent to the channel base region. The at least one interconnecting portion penetrates through the mesa structure, connecting the two linear sections. | 05-17-2012 |
| 20120098088 | METHOD OF FORMING ISOLATION STRUCTURE AND SEMICONDUCTOR DEVICE WITH THE ISOLATION STRUCTURE - A semiconductor device includes a substrate and an isolation structure, which includes a trench in the substrate, a lower filling layer at the bottom of the trench, and an upper filling layer on the lower filling layer, wherein the lower filling layer is denser than the upper filling layer, and the lower filling layer contains chlorine. The method for forming an isolation structure includes the steps of forming a trench in a substrate wherein the trench comprises side surfaces and a bottom surface, forming a nitride liner on the side surfaces of the trench, growing an epitaxial silicon layer from to the bottom surface of the trench, oxidizing the epitaxial silicon layer to form a lower filling layer in the lower portion of the trench, and filling a portion of the trench above the lower filling layer with dielectric material. | 04-26-2012 |
| 20110207034 | MATCHING METHOD OF PATTERN LAYOUTS FROM INVERSE LITHOGRAPHY - The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical. | 08-25-2011 |
| 20110085392 | METHOD FOR WRITING DATA TO MEMORY ARRAY - A method is provided for writing data to a memory array operating in synchronization with a clock signal having a transition edge. A data strobe signal having a transition edge corresponding to the transition edge of the clock signal is provided. The transition edge of the clock signal is used to relay the data corresponding to the transition edge of the data strobe signal if the transition edge of the data strobe signal is coming in earlier than the transition edge of the clock signal, wherein the clock signal has a rising edge and a falling edge, the data strobe signal has a rising edge and a falling edge respectively corresponding to the rising and the falling edges of the clock signal, and the transition edge of the clock signal is one of the rising and the falling edges of the clock signal. | 04-14-2011 |
| 20110080771 | DRAM POSITIVE WORDLINE VOLTAGE COMPENSATION DEVICE FOR ARRAY DEVICE THRESHOLD VOLTAGE AND VOLTAGE COMPENSATING METHOD THEREOF - The configurations of a DRAM positive wordline voltage compensation device and a voltage compensating method thereof are provided in the present invention. The proposed device includes a comparator having a first input terminal receiving a positive wordline voltage feedback signal, a second input terminal receiving a compensating reference of array device threshold voltage and an output terminal generating a first enable signal, an oscillator receiving the first enable signal and generating an oscillating signal when the first enable signal is active and a charge pump having a first input terminal receiving a second enable signal, a second input terminal receiving the oscillating signal and an output terminal generating a positive wordline voltage being a sum of a bitline high voltage, an array device threshold voltage and a voltage margin. | 04-07-2011 |
| 20110044100 | FLASH MEMORY CELL AND METHOD FOR OPERATING THE SAME - A flash memory cell according to the present invention includes a first charge-trapping region and a second charge-trapping region disposed in a semiconductor substrate, a first doped region disposed in the semiconductor substrate at a first side of the first charge-trapping region, a second doped region disposed in the semiconductor substrate at a second side of the first charge-trapping region, a first dielectric layer separating the semiconductor substrate from the first charge-trapping region and the second charge-trapping region, a first conductor disposed above the first charge-trapping region, and a second dielectric layer separating the first charge-trapping region from the first conductor, wherein the second charge-trapping region is configured to influence the conduction behavior of a carrier channel in the semiconductor substrate under the first charge-trapping region. | 02-24-2011 |
| 20110042722 | INTEGRATED CIRCUIT STRUCTURE AND MEMORY ARRAY - An integrated circuit structure includes a plurality of first doped regions disposed in a substrate in a matrix having odd columns and even columns each immediately adjacent to a corresponding one of the odd columns, a plurality of buried bit lines disposed in the substrate to electrically connect to the plurality of first doped regions of the same odd column in the matrix, and a plurality of surface bit lines disposed above an uppermost surface of the substrate, wherein each of the surface bit lines electrically connects to the first doped regions of the same even column in the matrix. | 02-24-2011 |
| 20110008961 | METHOD FOR FABRICATING INTEGRATED CIRCUIT STRUCTURES - A method for fabricating an integrated circuit structure includes the steps of forming a second dielectric layer on a substrate including a first conductive layer and a first dielectric layer, forming the second dielectric layer on the first conductive layer and the first dielectric layer, forming a hole exposing the first conductive layer in the second dielectric layer, forming a barrier layer inside the hole, and forming a second conductive layer on the barrier layer. In one embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal layer. In another embodiment of the present invention, the forming of the barrier layer comprises the steps of forming a metal nitride layer in the hole, and performing a treating process in an atmosphere including a plasma formed from a gas including oxidant to form a metal oxide layer on the metal and metal nitride layer. | 01-13-2011 |
| 20100258917 | CONDUCTIVE THROUGH CONNECTION AND FORMING METHOD THEREOF - A conductive through connection having a body layer and a metal layer is disposed on a semiconductor device, which the metal layer is on a top of body layer and includes a conductive body configured to penetrate the body layer and the metal layer. The width/diameter of one end of the conductive body is larger than that of another end thereof. The shape of these two ends of the body layer can be rectangular or circular. | 10-14-2010 |
| 20100240214 | METHOD OF FORMING MULTI METAL LAYERS THIN FILM ON WAFER - A method of forming the multi metal layers thin film has Ti sputtered on top surface of a substrate by PVD first. Then, Ti is transformed into TiN via CVD. Thus, by skipping the extra process steps of wafer cleaning and surface treating, the method not only solves the stress problems between two different metal layers but also improves the cycle time and particle performance for the production without any yield impact. | 09-23-2010 |
| 20100233881 | METHOD OF MANUFACTURING SUPPORTING STRUCTURES FOR STACK CAPACITOR IN SEMICONDUCTOR DEVICE - A method of manufacturing a supporting structure for a stack capacitor in a semiconductor device is provided. The method includes the following steps. The first step is providing a multi-layer structure including an etching stop layer, a silicon oxide layer and a silicon nitride layer. The second step is etching the silicon nitride layer and the silicon oxide layer to form a plurality of filling recesses in the silicon oxide layer, in which each the filling recess has a lateral surface and a bottom surface. The third step is forming a protecting layer at each the lateral surface. The fourth step is etching the silicon oxide layer to expose the etching stop layer. The fifth step is removing the protecting layer on the each lateral surface, thereby forming the supporting structure. | 09-16-2010 |
| 20100227069 | APPARATUS FOR REDUCING COST OF DEVELOPER AND THE METHOD THEREOF - An apparatus for homogenizing the developer concentration on the wafer and reducing the developer cost and the method thereof are provided in the present invention. The developer is provided on the wafer which then is spun to distribute the developer on the wafer. Next, the mechanical turbulence of the developer is produced on the wafer by the turbulence device or the mega-sonic vibrator. The apparatus is able to improve the uniformity of developer concentration, and the developer consumption is reduced. | 09-09-2010 |
| 20100202234 | POWER-ON MANAGEMENT CIRCUIT FOR MEMORY - A power-on management circuit for a memory device is provided. The power-on management circuit comprises a first external power-on voltage detector, a second external power-on voltage detector, a delay unit, a logic circuit, an internal power-on voltage detector, a voltage control circuit, a plurality of first electric pumps and a second electric pump. The first external power-on voltage detector has a first voltage threshold, receives a first external voltage, and generates a first control signal when the first external voltage is higher than the first voltage threshold. The second external power-on voltage detector has a second voltage threshold, receives a second external voltage, and generates a second control signal when the second external voltage is higher than the second voltage threshold. | 08-12-2010 |
| 20100193762 | NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and a fabrication method thereof are provided. The non-volatile memory cell includes an anode; a cathode having a surface facing the anode; a specific structure disposed on the surface; and an ion conductor disposed among the anode, the cathode and the specific structure, wherein the specific structure is one of a bulging area on the surface of the cathode and an insulating layer with an opening. | 08-05-2010 |
| 20100181545 | NON-VOLATILE MEMORY CELL AND FABRICATION METHOD THEREOF - A non-volatile memory cell and the fabrication method thereof are provided. The non-volatile memory cell comprises a top electrode, a bottom electrode and an oxide layer disposed between the top electrode and the bottom electrode. The oxide layer comprises a relatively low oxygen content layer adjacent to the bottom electrode, a relatively high oxygen content layer adjacent to the top electrode, and a transition layer disposed between the relatively high and the relatively low oxygen content layers. The transition layer has an oxygen concentration within a range between those of the relatively high and the relatively low oxygen content layers. | 07-22-2010 |
| 20100177587 | CIRCUIT AND METHOD FOR CONTROLLING DRAM COLUMN-COMMAND ADDRESS - The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address. | 07-15-2010 |
| 20100156452 | TESTING APPARATUS AND METHOD FOR TESTING A SEMICONDUCTOR DEVICES ARRAY - A testing apparatus and a method for testing a semiconductor devices array, which includes a plurality of rows and a plurality of columns, are provided. The testing apparatus includes a first testing circuit and a second testing circuit. The first testing circuit connects and transmits a clock signal, an input command signal and a data signal to at least one of the rows of the semiconductor devices array. The second testing circuit connects and transmits a selecting signal to at least one of the columns of the semiconductor devices array. Between two devices in a row, a difference in arrival times of the clock signal, a difference in arrival times of the input command signal, and a difference in arrival times of the data signal are equal. | 06-24-2010 |
| 20100104954 | MATCHING METHOD OF PATTERN LAYOUTS FROM INVERSE LITHOGRAPHY - The present invention relates to a matching method of pattern layouts from inverse lithography, which makes the pattern cells in the same groups identical to avoid a repeated verification and to improve the yield. The method comprises the step of: analyzing a target designed layout by hierarchy; categorizing the pattern cells with the same shape into a group; inversing the target designed layout by inverse lithography; inspecting the inversed pattern cells in the group with each other and replacing the variant ones to make all the inversed pattern cells identical. | 04-29-2010 |
| 20100013062 | NONVOLATILE MEMORY CELL - A nonvolatile memory cell is provided. A semiconductor substrate is provided. A conducting layer and a spacer layer are sequentially disposed above the semiconductor substrate. At least a trench having a bottom and plural side surfaces is defined in the conducting layer and the spacer layer. A first oxide layer is formed at the bottom of the trench. A dielectric layer is formed on the first oxide layer, the spacer layer and the plural side surfaces of the trench. A first polysilicon layer is formed in the trench. And a first portion of the dielectric layer on the spacer layer is removed, so that a basic structure for the nonvolatile memory cell is formed. | 01-21-2010 |
| 20090311878 | METHOD FOR DEPOSITING A DIELECTRIC MATERIAL - A depositing method for a dielectric material is provided, where the dielectric material has the first and the second primary elements, and a single precursor includes the first and the second primary elements. The depositing method includes pulsing the single precursor, purging a redundant part of the single precursor, pulsing an oxidant for oxidizing the single precursor, and purging a redundant part of the oxidant. | 12-17-2009 |
| 20090296779 | TEMPERATURE DETECTOR AND THE METHOD USING THE SAME - A temperature detector includes a plurality of comparators, an electronic component and a controller. Each of the comparators is responsible for detecting different temperature ranges. The electronic component has a temperature-dependent threshold voltage and an output connected to inputs of the plurality of comparators. The controller is configured to enable only one of the comparators at one time and to generate a value to the other inputs of the plurality of comparators. | 12-03-2009 |
| 20090268778 | TEMPERATURE DETECTOR AND THE METHOD USING THE SAME - A temperature detector comprises a first current mirror, a second current mirror, a first pulse generator, a second pulse generator, a phase detector and a controller. The current of the first current mirror is in variation with temperature, but the current of the second current mirror is not. If the output pulse of the first pulse generator appears earlier than that of the second pulse generator, the controller enhances the output current of the second current mirror. If the output pulse of the first pulse generator appears later than that of the second pulse generator, the controller decreases the output current of the second current mirror. | 10-29-2009 |
| 20090245011 | WORDLINE DRIVER FOR DRAM AND DRIVING METHOD THEREOF - A wordline driver for DRAM comprises a multiplexer, an inverter and a transistor switch. One end of the multiplexer is connected to a wordline charging voltage, and the other end is connected to an external voltage, wherein the external voltage is less than the wordline charging voltage, and initially the external voltage is outputted. The output end of the inverter is connected to the select line of the multiplexer, and the input end thereof is electrically connected to the output end of the multiplexer. One end of the transistor switch is connected to the input end of the inverter, and the other end thereof is connected to the word line. | 10-01-2009 |
| 20090233448 | LITHOGRAPHY RESOLUTION IMPROVING METHOD - A method of improving lithography resolution on a semiconductor, including the steps of providing a substrate on which a protecting layer, a first etching layer and a photoresist layer are sequentially formed; patterning the photoresist layer to form an opening so as to partially reveal the first etching layer; implanting a first ion into the revealed first etching layer to form a first doped area; and implanting a second ion into the revealed first etching layer to form a second doped area, wherein the first doped area is independent from the second doped area is provided. | 09-17-2009 |
| 20090220868 | MASK AND DESIGN METHOD THEREOF - A mask and the design method thereof are provided. The mask includes a light-shielding area shielding off a light, wherein the light-shielding area includes a photonic crystal having a lattice constant, and a ratio of the lattice constant to a wavelength of the light is a specific value within a band gap of the photonic crystal. | 09-03-2009 |
| 20090166702 | TRENCH-TYPE SEMICONDUCTOR DEVICE STRUCTURE - A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings. | 07-02-2009 |
| 20090137093 | METHOD OF FORMING FINFET DEVICE - A method of forming a FINFET device includes providing a substrate with a plurality of trench devices arranged in array therein, each of the trench devices comprising a plug protruding above the substrate; forming a plurality of isolation structures along a first direction in the substrate adjacent to the trench devices so as to define an active area exposing the substrate; forming a spacer on each of the plug to define a reactive area between the active area and the spacer; and removing the isolation structures on the reactive area to form a fin structure in the active area. | 05-28-2009 |
| 20090134442 | RECESSED CHANNEL DEVICE AND METHOD THEREOF - A method for forming a recessed channel device includes providing a substrate with a plurality of trench capacitors formed therein, each of the trench capacitors including a plug protruding above the substrate; forming a spacer on each of the plugs; forming a plurality of trench isolations along a first direction in the substrate adjacent to the trench capacitors so as to define an active area exposing the substrate; removing a portion of the substrate by using the spacers and the trench isolations as a mask to form a recessed channel; and trimming the recessed channel so that a surface profile of the recessed channel presents a three-dimensional shape. A recessed channel device with a rounded channel profile is also provided. | 05-28-2009 |
| 20090124085 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE HAS A LENGTHENED CHANNEL LENGTH - The present invention discloses a method for forming a semiconductor device. The method includes providing a substrate; forming at least one first opening in the substrate to a predetermined depth and exposing a sidewall of the substrate in the first opening; forming a spacer on the sidewall and exposing a portion of the substrate in the bottom of the first opening; etching the exposed substrate in the bottom of the first opening by using the spacer as a mask to form a second opening; forming an isolation layer in the second opening and a portion of the first opening; forming a gate dielectric layer on the surface of the substrate; and forming a conductive layer covering the substrate. | 05-14-2009 |
| 20090124059 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device, includes the steps of providing a substrate; forming a patterned stack on the substrate including a first dielectric layer on the substrate, a first conductive layer on the first dielectric layer and a mask layer on the first conductive layer, wherein a width of the mask layer is smaller than a width of the first conductive layer; forming a second dielectric layer on the sidewall of the patterned stack; forming a third dielectric layer on the substrate; forming a second conductive layer over the substrate; and removing the mask layer and a portion of the first conductive layer covered by the mask layer to form an opening so as to partially expose the first conductive layer. | 05-14-2009 |
| 20090117727 | METHOD OF FORMING A FLASH MEMORY - A method of forming a flash memory is provided. The method includes the steps of providing a substrate; forming a plurality of floating gates on the substrate; forming a first conformal dielectric layer to cover the substrate and the plurality of floating gates; forming a second conformal dielectric layer to cover the first conformal dielectric layer; partially removing the second conformal dielectric layer to partially expose the first conformal dielectric layer; forming a conformal precursor layer to cover the second conformal dielectric layer and the exposed portion of the-first conformal dielectric layer; oxidizing the conformal precursor layer to form a control gate dielectric layer between the plurality of floating gates; and forming a control gate on the control gate dielectric layer. | 05-07-2009 |
| 20090053873 | METHOD OF FORMING SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate. Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer. | 02-26-2009 |
| 20090040820 | Phase Change Memory - A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units, is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least, one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result. | 02-12-2009 |
| 20090040536 | MARK FOR ALIGNMENT AND OVERLAY, MASK HAVING THE SAME, AND METHOD OF USING THE SAME - A mark for alignment and overlay, a mask having the same, and a method of using the same are provided. The mark includes a first mark pattern and a second mark pattern. The first mark pattern includes a first pattern and a second pattern, and the second mark pattern includes a third pattern and a fourth pattern. The first pattern includes a plurality of rectangular regions arranged in a first direction, and for each rectangular region, a sideline in a second direction is longer than a sideline in the first direction, wherein the first direction is perpendicular to the second direction. The second pattern is disposed on both sides of the first pattern in the second direction and includes a plurality of rectangular regions arranged in the second direction, and for each rectangular region, the sideline in the first direction is longer than a sideline in the second direction. The third pattern includes two rectangular regions disposed on both sides of the first pattern in the first direction, and the fourth pattern includes two rectangular regions disposed on both sides of the second pattern in the second direction. | 02-12-2009 |
| 20090003102 | METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE - A method for testing a semiconductor memory device is provided. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Each word line is controlled by a corresponding control line and a corresponding driving line. The method includes selecting a plurality of word lines controlled by one driving line; enabling a plurality of control lines respectively corresponding to the selected word lines; actuating one of the selected word lines; and adding a disturbing signal on the actuated word line and measuring signals on the plurality of bit lines. | 01-01-2009 |
| 20080303103 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - The present invention provides a semiconductor structure and a method of forming the same. The method includes the steps of providing a substrate, forming a mask layer with an opening on the substrate, locally oxidizing the substrate to form an oxide layer within the opening, removing the oxide layer, such that a partial surface of the substrate becomes a curve surface, forming a sacrificial layer on the curve surface, forming a first doped region in the substrate and under the hard mask layer, forming a gate stack within the opening, removing the hard mask layer, forming a spacer on a sidewall of the gate stack, and forming a second doped region in the substrate and under the spacer. The second doped region has a dopant concentration is larger than that of the first doped region. Therefore, the oxide layer increases the surface area of the substrate so as to increase the channel length. Thus, the leakage between the source region and the drain region can be improved. | 12-11-2008 |
| 20080286934 | METHOD OF FORMING A TRENCH CAPACITOR - A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench. | 11-20-2008 |
| 20080268590 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH A SINGLE-SIDED BURIED STRAP - A method for forming a semiconductor device with a single-sided buried strap is provided. The method includes the steps of providing a substrate with a trench, forming a semiconductor component in a lower portion of the trench to expose a higher portion of the trench, forming a first dielectric layer on a sidewall of the higher portion of the trench, forming a first conductive layer in the trench and adjacent to the first dielectric layer, forming a second dielectric layer on the first dielectric layer and the first conductive layer, forming a plurality of gate structures on the substrate, wherein one of the gate structures on the second dielectric layer is offset for a distance from the second dielectric layer, removing a portion of the second dielectric layer and a portion of the first dielectric layer to form an opening by using the gate structure as a mask, and forming a second conductive layer in the opening to electrically couple to the first conductive layer, whereby the semiconductor device with the single sided buried strap is formed. | 10-30-2008 |
| 20080268557 | METHOD FOR MEASURING A THIN FILM THICKNESS - A method for measuring a thin film thickness is provided. The method includes the following steps: providing a plurality of structures, each including a semiconductor substrate, a thin film, and a metal layer; measuring resistances of the metal layers of the plurality of structures and thicknesses of the thin films of the plurality of structures to obtain a plurality of resistance values and a plurality of corresponding thickness values; establishing a thickness-resistance table based on the plurality of resistance values and thickness values; providing a structure to be tested including a semiconductor substrate, a thin film, and a metal layer; and measuring resistance of the metal layer of the structure to be tested to determine a thickness value of the thin film of the structure to be tested according to the thickness-resistance table. | 10-30-2008 |
| 20080217779 | SEMICONDUCTOR STRUCTURE AND THE FORMING METHOD THEREOF - The present invention provides a semiconductor structure and the forming method thereof. The structure includes a substrate having a plurality of stacks; a conformal layer on the substrate and a portion of sidewalls of the plurality of the stacks; and a plurality of plugs between the plurality of stacks. In addition, the present invention also provides a method of forming the semiconductor structure, comprising steps of providing a substrate; forming a plurality of stacks on the substrate; forming a conformal layer on the stacks and on the substrate; removing a portion of the conformal layer to expose a sidewall and a top surface of the plurality of stacks; and forming a plurality of plugs between the stacks. | 09-11-2008 |
| 20080206684 | METHOD FOR FORMING RING PATTERN - A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall. | 08-28-2008 |
