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MOSEL VITELIC INC.

MOSEL VITELIC INC. Patent applications
Patent application numberTitlePublished
20100163104SOLAR CELL - A solar cell includes a semiconductor substrate, an emitter layer, an anti-reflective coating, a first electrode, a second electrode, and a first light conversion layer. The emitter layer is formed on a light-receiving side of the semiconductor substrate. A p-n junction is formed between the emitter layer and the semiconductor substrate. The anti-reflective coating is formed on the emitter layer. The first electrode is connected to the emitter layer. The second electrode is formed on a back-lighted side of the semiconductor substrate. The first light conversion layer is formed on the anti-reflective coating. The first light conversion layer absorbs a first light with a first wavelength and emits a second light with a second wavelength, thereby performing a photoelectric converting operation.07-01-2010
20100015750Process of manufacturing solar cell - A process of manufacturing a solar cell is disclosed. The process comprises steps of (a) providing a semiconductor substrate, (b) forming a dielectric layer with amorphous silicon structure on the semiconductor substrate, (c) partially removing the dielectric layer with amorphous silicon structure to expose parts of the semiconductor substrate, (d) simultaneously forming a heavily doped region on a surface of the exposed semiconductor substrate and a lightly doped region on a surface of the unexposed semiconductor substrate using the dielectric layer with amorphous silicon structure as a translucent barrier layer, (e) removing the dielectric layer with amorphous silicon structure, (f) forming an anti-reflection coating on the semiconductor substrate, and (g) forming a first electrode on the anti-reflection coating and coupled with the heavily doped region.01-21-2010
20090263928METHOD FOR MAKING A SELECTIVE EMITTER OF A SOLAR CELL - A method for manufacturing a selective emitter of a solar cell is provided. The method includes steps of providing a substrate; forming an emitter layer on the substrate, wherein the emitter layer has a heavily doped portion located on a top thereof and a relatively lightly doped portion located at a bottom thereof; forming a patterned mask layer on the emitter layer; and performing a wet etching for exposing a region of the relatively lightly doped portion which is not covered by the patterned mask layer.10-22-2009
20090056807Solar cell and fabricating process thereof - A solar cell includes a semiconductor substrate, an emitter layer, at least one emitter contact region and at least one first electrode. The emitter layer is formed on at least one surface of the semiconductor substrate. A p-n junction is formed between the emitter layer and the semiconductor substrate. The emitter contact region is formed on portions of the emitter layer and has the same type of dopant as the emitter layer. The emitter contact region has a higher dopant concentration than the emitter layer. The first electrode is coupled with the emitter contact region.03-05-2009
20080302412PHOTOVOLTAIC POWER DEVICE AND MANUFACTURING METHOD THEREOF - A photovoltaic power device is provided. The photovoltaic power device includes a donor substrate, a first emitting substrate; a second emitting substrate, a first anti-reflection layer, a first metal electrode, a second metal electrode and a second anti-reflection layer. In the photovoltaic power device, the first and the second emitting substrate are disposed in the opposite sides of the donor substrate to generate two electronic flows, and the first metal electrode is insulated from the second metal electrode by the second anti-reflection layer.12-11-2008
20080280430METHOD OF FORMING FILMS IN A TRENCH - A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.11-13-2008

Patent applications by MOSEL VITELIC INC.