MOSAID Technologies Corporation Patent applications |
Patent application number | Title | Published |
20100060319 | LOW LEAKAGE AND DATA RETENTION CIRCUITRY - An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry. | 03-11-2010 |
20090152948 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 06-18-2009 |
20090140800 | INTEGRATED CIRCUIT WITH SIGNAL BUS FORMED BY CELL ABUTMENT OF LOGIC CELLS - An integrated circuit with a signal bus formed by the cell abutment of logic cells. The integrated circuit comprises at least two logic cells. The signal bus is formed by cell abutment of the at least two logic cells. The signal bus is configured to receive a signal and to distribute the signal to each of the at least two logic cells. | 06-04-2009 |
20080276105 | POWER MANAGERS FOR AN INTEGRATED CIRCUIT - A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands. | 11-06-2008 |
20080263116 | BALANCED PSEUDO-RANDOM BINARY SEQUENCE GENERATOR - Disclosed is a method for producing, in an electronic circuit, a varying digital output in response to edges of a received clock signal. The method includes generating, within circuitry of the electronic circuit, an unbalanced, pseudo-random binary output of the circuitry. The method also includes generating, within the electronic circuit and from the received clock, a sub-rate clock version of the received clock. The method also includes carrying out, within the electronic circuit, an exclusive OR operation between the sub-rate clock and the pseudo-random binary output of the circuitry to produce a balanced, pseudo-random binary output. | 10-23-2008 |
20080258835 | CIRCUIT AND METHOD FOR GLITCH CORRECTION - Correction of glitches output from a delta-sigma modulator is accomplished using an integer boundary crossing detector and a FIR filter. The detector monitors a portion of an input to the modulator. The detector recognizes a transition from an all 1's bit pattern to an all 0's bit pattern or vice versa as representative of potential for a glitch to be present on the output of the modulator. The detector responsively generates condition detection output. Receipt of such condition detection output triggers the generation of a correction signal by the filter. The correction signal is, at least substantially similar, in magnitude but opposite in sign from to the expected glitch at the output of the modulator. The correction signal is added to the output of the modulator to substantially eliminate the glitch. | 10-23-2008 |