| MOS Art Pack Corporation Patent applications |
| Patent application number | Title | Published |
|---|
| 20120043639 | FABRICATING METHOD AND STRUCTURE OF SUBMOUNT - A fabricating method and structure of a submount are provided. The submount includes a semiconductor substrate, a first electrode, a second electrode and a first insulating adhesive member. The fabricating method of the submount includes the following steps. A semiconductor substrate is provided. An isolating groove is formed on a first surface of the semiconductor substrate, thereby defining a first region and a second region. A first electrode is formed on the first surface in the first region and a second electrode is formed on the first surface in the second region. A first insulating adhesive member is filled in the isolating groove. The semiconductor substrate is thinned from the second surface so as to expose the first insulating adhesive member from the second surface, thereby insulating the first region of the semiconductor substrate from the second region of the semiconductor substrate. | 02-23-2012 |
| 20120038060 | STACKING METHOD AND STACKING CARRIER - A stacking carrier and a stacking method are provided. The stacking method is used between a wafer and a stacking carrier having the same shape. The stacking method includes the following steps. Firstly, an adhesive layer is coated on a surface of the carrier. Then, the adhesive layer corresponding to an edge of the carrier is partially removed, thereby defining at least one adhesive layer indentation. Afterwards, the wafer is stacked on the carrier through the adhesive layer having the adhesive layer indentation. | 02-16-2012 |
| 20120009716 | PACKAGE PROCESS OF BACKSIDE ILLUMINATION IMAGE SENSOR - In a package process of backside illumination image sensor, a wafer including a plurality of pads is provided. A first carrier is processed to form a plurality of blind vias therein. The first carrier is adhered to the wafer so that the blind vias face to the pads correspondingly. A spacing layer is formed and a plurality of sensing components are disposed. A second carrier is adhered on the spacing layer. Subsequently, a carrier thinning process is performed so that the blind vias become the through holes. An insulating layer is formed on the first carrier. An electrically conductive layer is formed on the insulating layer and filled in the though holes to electrically connect to the pads. The package process can achieve the exact alignment of the through holes and the pads, thereby increasing the package efficiency and improving the package quality. | 01-12-2012 |
| 20120009394 | BONDING METHOD AND BONDING SUBSTRATE - A bonding method and a bonding substrate are provided. The bonding substrate is applied to a silicon wafer having the same shape. The bonding method includes the following steps. Firstly, the optical glass substrate is processed to form a first alignment mark. Then, an adhesive layer is coated on a surface of the optical glass substrate. The adhesive layer on the surface of the optical glass substrate is partially removed, thereby defining an adhesive structure. According to the first alignment mark of the optical glass substrate and a second first alignment mark of the silicon wafer, alignment between the optical glass substrate and the silicon wafer is performed. Afterwards, the optical glass substrate and the silicon wafer are bonded together through the adhesive structure. | 01-12-2012 |
| 20120007249 | SILICON BASED SUBSTRATE AND MANUFACTURING METHOD THEREOF - A silicon based substrate includes a silicon wafer, a first circuit substrate and a second circuit substrate. The silicon wafer includes a first surface and a second surface and at least a through silicon via. The first circuit substrate is disposed on the first surface and includes a plurality of first dielectric layers and a plurality of first conductive trace layers alternately stacked. The second circuit substrate is disposed on the second surface and includes a plurality of second dielectric layers and a plurality of second conductive trace layers alternately stacked. The trace density of the first conductive trace layers is higher than the trace density of the second conductive trace layers. Otherwise, the first dielectric layer includes an inorganic material and the second dielectric layer includes an organic material. A manufacturing method of the silicon based substrate is also provided. | 01-12-2012 |
