Microsemi SoC Corporation Patent applications |
Patent application number | Title | Published |
20160140357 | SECURITY METHOD AND APPARATUS TO PREVENT REPLAY OF EXTERNAL MEMORY DATA TO INTEGRATED CIRCUITS HAVING ONLY ONE-TIME PROGRAMMABLE NON-VOLATILE MEMORY - A method for generating a secure nonce using a one-time programmable (OTP) memory within an integrated circuit to provide persistence, the method including randomly selecting k currently-unprogrammed bits in the OTP memory, creating a data set using data derived from current contents of the OTP memory altered by changing the states of the k currently-unprogrammed bits of the OTP memory, and employing as the secure nonce the data set or data derived from the data set. The selected k bits are programmed in the OTP memory. | 05-19-2016 |
20160026472 | METHOD FOR IMPLEMENTING "INSTANT BOOT" IN A CUSTOMIZABLE SOC - A method for implementing an instant boot function in a customizable system on a chip (SoC) integrated circuit having an application specific integrated circuit portion including configuration registers includes providing a field programmable gate array fabric on the SoC, providing non-volatile memory cells on the SoC, and initializing the configuration registers using data from the non-volatile memory cells during a system reset mode of operation of the integrated circuit. | 01-28-2016 |
20160020772 | APPARATUS AND METHOD FOR DETECTING AND PREVENTING LASER INTERROGATION OF AN FPGA INTEGRATED CIRCUIT - A circuit internal to a programmable integrated circuit for preventing laser interrogation of the programmable integrated circuit includes a sense resistor connected between a deep n-well and a source of bias voltage for the deep n-well. A voltage-sensing circuit is coupled across the sense resistor to measure voltage across the sense resistor. A tamper trigger circuit responsive to the voltage sensing circuit generates a tamper signal in response to a voltage sensed in the voltage sensing circuit having a magnitude greater than a threshold value. | 01-21-2016 |
20150370247 | IDENTIFYING INTEGRATED CIRCUIT ORIGIN USING TOOLING SIGNATURE - A method for determining if an individual integrated circuit was manufactured using an individual instance of tooling includes collecting from the individual integrated circuit first data representing at least one attribute that varies as a function of the tooling used to manufacture the individual integrated circuit and second data identifying the integrated circuit as having been manufactured using the individual instance of tooling. The first data is compared to a signature of the individual instance of tooling identified by the second data. The signature is derived from the at least one attribute measured from a population of integrated circuits that were manufactured using the individual instance of tooling. The individual integrated circuit is identified as having been manufactured using the individual instance of tooling identified in the second data collected from the individual integrated circuit if the first data correlates to the signature by a predetermined threshold. | 12-24-2015 |
20150318853 | Gate Boosting Transmission Gate - A gate-boosting transmission gate includes an input node and an output node. An n-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the n-channel transistor having a low threshold. A p-channel transistor has a first source/drain terminal connected to the input node and a second source/drain terminal connected to the output node, the p-channel transistor having a very low threshold. | 11-05-2015 |
20150318278 | Circuit and Method for Reducing BVii on Highly Overdriven Devices - An integrated circuit is formed on a p-type semiconductor substrate connected to ground potential. A deep n-well is disposed in the p-type substrate. A p-well is disposed in the deep n-well. An n+ drain region and an n+ source region are disposed in the p-well, the n+ source region connected to a common potential. A p-type contact is disposed in the p-well and is connected to ground potential through a resistor. | 11-05-2015 |
20150242620 | METHODS FOR CONTROLLING THE USE OF INTELLECTUAL PROPERTY IN INDIVIDUAL INTEGRATED CIRCUIT DEVICES - A method for controlling the use of intellectual property (IP) in an individual integrated circuit includes loading data including the IP into the individual integrated circuit, loading an IP license certificate into the individual integrated circuit, the certificate including identification of the IP authorized for the individual integrated circuit, determining inside the individual integrated circuit whether the IP is authorized for the individual integrated circuit, enabling operation of the individual integrated circuit if the IP circuit is authorized for use in the individual integrated circuit, and imposing a penalty on operation of the individual integrated circuit if the IP is not authorized for use in the individual integrated circuit. | 08-27-2015 |
20150242615 | METHODS FOR CONTROLLING THE USE OF INTELLECTUAL PROPERTY IN INDIVIDUAL INTEGRATED CIRCUIT DEVICES - A method for controlling the use of intellectual property (IP) in an individual integrated circuit includes loading data including the IP into the individual integrated circuit, loading an IP license certificate into the individual integrated circuit, the certificate including identification of the IP authorized for the individual integrated circuit, determining inside the individual integrated circuit whether the IP is authorized for the individual integrated circuit, enabling operation of the individual integrated circuit if the IP circuit is authorized for use in the individual integrated circuit, and imposing a penalty on operation of the individual integrated circuit if the IP is not authorized for use in the individual integrated circuit. | 08-27-2015 |
20150137233 | HIGH VOLTAGE DEVICE FABRICATED USING LOW-VOLTAGE PROCESSES - A high-voltage transistor includes an active region including a diffused region of a first conductivity type defined by inner edges of a border of shallow trench isolation. A gate having side edges and end edges is disposed over the active region. Spaced apart source and drain regions of a second conductivity type opposite the first conductivity type are disposed in the active region outwardly with respect to the side edges of the gate. Lightly-doped regions of the second conductivity type more lightly-doped than the source and drain regions surround the source and drain regions and extend inwardly between the source and drain regions towards the gate to define a channel, and outwardly towards all of the inner edges of the shallow trench isolation. Outer edges of the lightly-doped region from at least the drain region are spaced apart from the inner edges of the shallow trench isolation. | 05-21-2015 |
20140291771 | TID Hardened and Single Even Transient Single Event Latchup Resistant MOS Transistors and Fabrication Process - A radiation-hardened transistor is formed in a p-type body. An active region is disposed within the p-type body and has a perimeter defined by a shallow-trench isolation region filled with a dielectric material. Spaced-apart source and drain regions are disposed in the active region, forming a channel therebetween. A polysilicon gate is disposed above, aligned with, and insulated from the channel region. A p-type isolation ring is disposed in the p-type body separating outer edges of at least one of the source and drain regions from the perimeter of the active region. A body contact is disposed in the p-type isolation ring. | 10-02-2014 |
20140281775 | System on a Chip FPGA Spatial Debugging Using Single Snapshot - A method for performing on-chip spatial debugging of a user circuit programmed into a user-programmable integrated circuit includes halting an internal clock driving synchronous logic elements in the integrated circuit and reading the states of all synchronous logic elements programmed into the integrated circuit while the internal clock is halted. An interrupt to an embedded processor in the integrated circuit running a user application can also be generated. The output of at least one synchronous logic element can be forced to a desired state while the internal clock is halted. The clock can then be restarted or stepped. | 09-18-2014 |
20140269133 | Background Auto-refresh Apparatus and Method for Non-Volatile Memory Array - A method for automatically refreshing a non-volatile memory array in the background without memory interruption includes selecting an unrefreshed segment of the memory, reading data from each row in the selected segment during memory dead time and storing the data read from each row in a local temporary storage memory until an entire segment is read out, remapping all memory addresses in the selected segment to the temporary storage memory, isolating column lines in the selected segment from global column lines, erasing the data in the selected segment without disturbing the column lines, rewriting memory data in each row of the selected segment, remapping all memory addresses in the selected segment to the memory, and repeating the process until all segments have been refreshed. | 09-18-2014 |
20140246719 | Non-Volatile Push-Pull Non-Volatile Memory Cell Having Reduced Operation Disturb and Process for Manufacturing Same - A non-volatile memory cell includes a p-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel and an n-channel non-volatile transistor having a source and a drain defining a channel and a gate overlying the channel. In at least one of the p-channel non-volatile transistor and the n-channel non-volatile transistor, a lightly-doped drain region extends from the drain into the channel. | 09-04-2014 |
20140246644 | Front to Back Resistive Random Access Memory Cells - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 09-04-2014 |
20140138755 | Non-volatile Programmable Memory Cell and Array for Programmable Logic Array - A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor. | 05-22-2014 |