| MICRON TECHNOLOGY, INC. Patent applications |
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| 20120036411 | METHOD, SYSTEM, AND APPARATUS FOR DISTRIBUTED DECODING DURING PROLONGED REFRESH - Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode. | 02-09-2012 |
| 20120034753 | Methods of Forming a Plurality of Capacitors - A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors. | 02-09-2012 |
| 20120034740 | PRE-ENCAPSULATED CAVITY INTERPOSER - Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame. | 02-09-2012 |
| 20120033493 | ERASE COMPLETION RECOGNITION - Embodiments include but are not limited to apparatuses and systems including a main memory array, at least one erase status memory cell associated with the main memory array and configured to store a value indicative of an erase completion status of the main memory array, and a control module operatively coupled to the at least one erase status memory cell, the control module configured to perform operations on the main memory array based at least in part on the value stored in the at least one erase status memory cell. Other embodiments may be described and claimed. | 02-09-2012 |
| 20120033477 | MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS - Examples described include memory units coupled to a controller using a daisy chain wiring configuration. A filter located between a first memory unit and the controller attenuates a particular frequency, which may improve ringback in a signal received at the memory units. In some examples, a quarter-wavelength stub is used to implement the filter. In some examples, signal components at 800 MHz may be attenuated by a stub, which may improve ringback. | 02-09-2012 |
| 20120032257 | Dual Work Function Recessed Access Device and Methods of Forming - A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device. | 02-09-2012 |
| 20120032252 | THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL - Methods and devices are disclosed, such as those involving memory cell devices with improved charge retention characteristics. In one or more embodiments, a memory cell is provided having an active area defined by sidewalls of neighboring trenches. A layer of dielectric material is blanket deposited over the memory cell, and etched to form spacers on sidewalls of the active area. Dielectric material is formed over the active area, a charge trapping structure is formed over the dielectric material over the active area, and a control gate is formed over the charge trapping structure. In some embodiments, the charge trapping structure includes nanodots. In some embodiments, the width of the spacers is between about 130% and about 170% of the thickness of the dielectric material separating the charge trapping material and an upper surface of the active area. | 02-09-2012 |
| 20120032182 | SOLID STATE LIGHTS WITH THERMAL CONTROL ELEMENTS - A solid state light (“SSL”), a solid state emitter (“SSE”), and methods of manufacturing SSLs and SSEs. In one embodiment, an SSL comprises a packaging substrate having an electrical contact and a light emitting structure having a front side and a back side. The back side of the light emitting structure is superimposed with the electrical contact of the packaging substrate. The SSL can further include a temperature control element aligned with the light emitting structure and the electrical contact of the packaging substrate. | 02-09-2012 |
| 20120032137 | SOLID STATE LIGHTING DEVICES WITH DIELECTRIC INSULATION AND METHODS OF MANUFACTURING - Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The solid state lighting device also includes an indentation extending from the second semiconductor material toward the active region and the first semiconductor material and an insulating material in the indentation of the solid state lighting structure. | 02-09-2012 |
| 20120030638 | METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME - Methods are disclosed for defining evaluation points for use in optical proximity correction of a rectangular target geometry. A method for defining evaluation points for use in optical proximity correction of a rectangular target geometry may comprise predicting a contour of an image to be produced in an optical proximity correction simulation of a target geometry. The target geometry may comprise a plurality of line segments, each line segment of the plurality having one evaluation point defined thereon. The method may further comprise shifting at least one evaluation point to an associated point on the predicted contour of the image. | 02-02-2012 |
| 20120030545 | ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING - Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes. | 02-02-2012 |
| 20120030452 | MODIFYING COMMANDS - The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured to modify at least a number of commands in the queue and execute the modified commands. | 02-02-2012 |
| 20120028410 | METHODS OF FORMING GERMANIUM-ANTIMONY-TELLURIUM MATERIALS AND A METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE INCLUDING THE SAME - A method of forming a material. The method comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal precursor and a co-reactive first metal precursor. An ALD layer cycle of a second metal is conducted, the ALD layer cycle comprising a reactive second metal precursor and a co-reactive second metal precursor. An ALD layer cycle of a third metal is conducted, the ALD layer cycle comprising a reactive third metal precursor and a co-reactive third metal precursor. The ALD layer cycles of the first metal, the second metal, and the third metal are repeated to form a material, such as a GeSbTe material, having a desired stoichiometry. Additional methods of forming a material, such as a GeSbTe material, are disclosed, as is a method of forming a semiconductor device structure including a GeSbTe material. | 02-02-2012 |
| 20120025402 | METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE LINES - Methods of forming semiconductor device structures are disclosed. One method comprises forming a plurality of loops of a conductive material. Each loop of the plurality of loops comprises a uniform pattern. In one embodiment, a portion of the conductive material is removed from at least one location in each loop of the plurality of loops. Contacts are formed to the conductive material. A semiconductor device structure is also disclosed. | 02-02-2012 |
| 20120023294 | MEMORY DEVICE AND METHOD HAVING ON-BOARD PROCESSING LOGIC FOR FACILITATING INTERFACE WITH MULTIPLE PROCESSORS, AND COMPUTER SYSTEM USING SAME - A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function. | 01-26-2012 |
| 20120021610 | Methods of Forming Material on a Substrate, and a Method of Forming a Field Effect Transistor Gate Oxide on a Substrate - The invention includes methods of forming material on a substrate and methods of forming a field effect transistor gate oxide. In one implementation, a first species monolayer is chemisorbed onto a substrate within a chamber from a gaseous first precursor. The first species monolayer is discontinuously formed over the substrate. The substrate having the discontinuous first species monolayer is exposed to a gaseous second precursor different from the first precursor effective to react with the first species to form a second species monolayer, and effective to form a reaction product of the second precursor with substrate material not covered by the first species monolayer. The substrate having the second species monolayer and the reaction product is exposed to a third gaseous substance different from the first and second precursors effective to selectively remove the reaction product from the substrate relative to the second species monolayer. Other implementations are contemplated. | 01-26-2012 |
| 20120021601 | Methods of Forming Through Substrate Interconnects - A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material. | 01-26-2012 |
| 20120021594 | Methods of Forming a Plurality of Transistor Gates, and Methods of Forming a Plurality of Transistor Gates Having at Least Two Different Work Functions - A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate. | 01-26-2012 |
| 20120021587 | Systems and Methods for Forming Metal Oxide Layers - A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds. | 01-26-2012 |
| 20120021573 | Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate - A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed. | 01-26-2012 |
| 20120019349 | CONFINED RESISTANCE VARIABLE MEMORY CELLS AND METHODS - Methods, devices, and systems associated with resistance variable memory device structures are described herein. In one or more embodiments, a method of forming a confined resistance variable memory cell structure includes forming a resistance variable material such that a first unmodified portion of the resistance variable material contacts a bottom electrode and a second unmodified portion of the resistance variable material contacts a top electrode. | 01-26-2012 |
| 20120019293 | DELAY LOCK LOOP PHASE GLITCH ERROR FILTER - A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter unit to provide filtering of noise on a phase control signal to substantially reduce a false delay lock loop state. | 01-26-2012 |
| 20120018887 | MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES - A stackable microelectronic package includes a first microelectronic die attached to and electrically connecting with a first substrate. A second microelectronic die is attached to the first die on one side, and to a second substrate on the other side. Electrical connections are made between the first die and the first substrate, between the second die and the second substrate, and between the first and second substrates, e.g., via wire bonding. The electrical connecting elements are advantageously encased in a molding compound. Exposed contacts on the first and/or second substrates, not covered by the molding compound, provide for electrical connections between the package, and another package stacked onto the package. The package may avoid coplanarity factors, can be manufactured using existing equipment, allows for intermediate testing, and can also offer a thinner package height. | 01-26-2012 |
| 20120018789 | Systems and Devices Including Multi-Gate Transistors and Methods of Using, Making, and Operating the Same - Disclosed are methods of forming transistors. In one embodiment, the transistors are formed by forming a plurality of elliptical bases in a substrate and forming fins form the elliptical bases. The transistors are formed within the fin such that they may be used as access devices in a memory array. | 01-26-2012 |
| 20120018693 | CONFINED RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS - Confined resistance variable memory cell structures and methods are described herein. One or more methods of forming a confined resistance variable memory cell structure includes forming a via in a memory cell structure and forming a resistance variable material in the via by performing a process that includes providing a germanium amidinate precursor and a first reactant to a process chamber having the memory cell structure therein and providing an antimony ethoxide precursor and a second reactant to the process chamber subsequent to removing excess germanium. | 01-26-2012 |
| 20120016651 | Simulating the Transmission of Asymmetric Signals in a Computer System - Methods implementable in a computer system for simulating the transmission of signals are disclosed. The disclosed techniques simulate the effect of the transmitter as well as the channel on a positive and negative pulse, which assures that asymmetry in the transmitter is captured. The resulting positive and negative pulse responses are then used to generate two separate PDFs: one indicative of received logic ‘1’s and another indicative of received logic ‘0’s at a point in time. Generating a plurality of such PDFs at different times allows the reliability of data reception to be assessed, and appropriate sensing margins to be set at a receiver, without the need to simulate the transmission of a very long random stream of data bits. | 01-19-2012 |
| 20120016650 | Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System - Methods implementable in a computer system for simulating the transmission of signals across a plurality of data channels (bus) are disclosed. The disclosed techniques simulate the effects of Intersymbol Interference (ISI), cross talk, and Simultaneous Switching Output (SSO) noise by generating Probability Distribution Functions (PDFs) for each. The resulting PDFs are convolved to arrive at a total PDF indicative of the reception of data subject to each of these non-idealities. The total PDF, and its underlying terms, can be indexed to particular channels of the bus as well as to particular logic states. Use of the disclosed technique allows bit error rates and sensing margins to be determined with minimal computation and simulation. | 01-19-2012 |
| 20120015526 | Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors - Embodiments disclosed herein pertain to silicon dioxide deposition methods using at least ozone and tetraethylorthosilicate (TEOS) as deposition precursors. In one embodiment, a silicon dioxide deposition method using at least ozone and TEOS as deposition precursors includes flowing precursors comprising ozone and TEOS to a substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material having an outer surface onto the substrate. The outer surface is treated effective to one of add hydroxyl to or remove hydroxyl from the outer surface in comparison to any hydroxyl presence on the outer surface prior to said treating. After the treating, precursors comprising ozone and TEOS are flowed to the substrate under subatmospheric pressure conditions effective to deposit silicon dioxide-comprising material onto the treated outer surface of the substrate. Other embodiments are contemplated. | 01-19-2012 |
| 20120015524 | Process for Enhancing Solubility and Reaction Rates In Supercritical Fluids - Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate. | 01-19-2012 |
| 20120014185 | CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY - An integrated circuit bit line driver system includes a plurality of bit line drivers coupled to respective bit lines of an array of non-volatile memory cells. Each of the bit line drivers includes a bias transistor through which an input signal is coupled to the respective bit line. The bit line driver system includes a bias voltage circuit that generates a bias voltage that is coupled to the respective gates of the bias transistors. The bias voltage circuit initially accelerates the charging of the transistor gates, and subsequently completes charging the gates at a slower rate. The bias voltage is generated using a diode-coupled transistor having electrical characteristics the match those of the bias transistors so that the bias voltage varies with process or temperature variations of the integrated circuit in the same manner as the threshold voltage of the bias transistors vary with process or temperature variations. | 01-19-2012 |
| 20120014166 | RESISTIVE MEMORY - The present disclosure includes resistive memory devices and systems having resistive memory cells, as well as methods for operating the resistive memory cells. One memory device embodiment includes at least one resistive memory element, a programming circuit, and a sensing circuit. For example, the programming circuit can include a switch configured to select one of N programming currents for programming the at least one resistive memory element, where each of the N programming currents has a unique combination of current direction and magnitude, with N corresponding to the number of resistance states of the at least one memory element. In one or more embodiments, the sensing circuit can be arranged for sensing of the N resistance states. | 01-19-2012 |
| 20120013368 | METHOD AND SYSTEM FOR ELECTRICALLY COUPLING A CHIP TO CHIP PACKAGE - A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds. | 01-19-2012 |
| 20120013314 | VOLTAGE REGULATOR SYSTEM - The present disclosure includes circuits, systems and methods for regulating voltage. One voltage regulator system embodiment includes a voltage regulator having an output and a number of stages coupled in parallel to the output of the voltage regulator. Each stage includes a source follower circuit, and a sample and hold circuit coupled in series between the output of the voltage regulator and an input of the source follower circuit. | 01-19-2012 |
| 20120013273 | SOLID STATE LIGHTING DEVICES WITHOUT CONVERTER MATERIALS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The active region includes a first sub-region having a first center wavelength and a second sub-region having a second center wavelength different from the first center wavelength. | 01-19-2012 |
| 20120012914 | Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - The invention includes methods of utilizing compositions containing iridium and tantalum in semiconductor constructions, and includes semiconductor constructions comprising compositions containing iridium and tantalum. The compositions containing iridium and tantalum can be utilized as barrier materials, and in some aspects can be utilized as barriers to copper diffusion. | 01-19-2012 |
| 20120012855 | SOLID-STATE LIGHT EMITTERS HAVING SUBSTRATES WITH THERMAL AND ELECTRICAL CONDUCTIVITY ENHANCEMENTS AND METHOD OF MANUFACTURE - Solid-state lighting devices (SSLDs) including a carrier substrate with conductors and methods of manufacturing SSLDs. The conductors can provide (a) improved thermal conductivity between a solid-state light emitter (SSLE) and a package substrate and (b) improved electrical conductivity for the SSLE. In one embodiment, the conductors have higher thermal and electrical conductivities than the carrier substrate supporting the SSLE. | 01-19-2012 |
| 20120012812 | SOLID STATE LIGHTING DEVICES WITH REDUCED CRYSTAL LATTICE DISLOCATIONS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures. | 01-19-2012 |
| 20120011409 | DEVICES, METHODS, AND APPARATUSES FOR DETECTION, SENSING, AND REPORTING FUNCTIONALITY FOR SEMICONDUCTOR MEMORY - Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system. | 01-12-2012 |
| 20120011335 | MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS - The present disclosure includes methods and devices for a memory controller. In one or more embodiments, a memory controller includes a plurality of back end channels, and a command queue communicatively coupled to the plurality of back end channels. The command queue is configured to hold host commands received from a host. Circuitry is configured to generate a number of back end commands at least in response to a number of the host commands in the command queue, and distribute the number of back end commands to a number of the plurality of back end channels. | 01-12-2012 |
| 20120009793 | METHOD FOR SELECTIVELY MODIFYING SPACING BETWEEN PITCH MULTIPLIED STRUCTURES - Methods for circuit material processing are provided. In at least one such method, a substrate is provided with a plurality of overlying spacers. The spacers have substantially straight inner sidewalls and curved outer sidewalls. An augmentation material is formed on the plurality of spacers such that the inner or the outer sidewalls of the spacers are selectively expanded. The augmentation material can bridge the upper portions of pairs of neighboring inner sidewalls to limit deposition between the inner sidewalls. The augmentation material is selectively etched to form a pattern of augmented spacers having a desired augmentation of the inner or outer sidewalls. The pattern of augmented spacers can then be transferred to the substrate through a series of selective etches such that features formed in the substrate achieve a desired pitch. | 01-12-2012 |
| 20120009779 | CONTACT FORMATION - The present disclosure includes various methods of contact embodiments. One such method embodiment includes forming a trench in an insulator stack material of a particular thickness. This method includes forming a filler material in the trench and removing the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes forming a spacer material on at least one side surface of the trench to the particular depth of the filler material and forming a conductive material in the trench over the filler material. | 01-12-2012 |
| 20120009776 | SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate. | 01-12-2012 |
| 20120008440 | DATA RETENTION KILL FUNCTION - Various data protection techniques are provided. In one embodiment, a memory device is provided. The memory device may initiate a security measure upon occurrence of one or more triggering events. The one or more triggering events may include receipt of a command signal. Various additional methods, devices, and systems are also provided. | 01-12-2012 |
| 20120008404 | SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME - Methods, memory devices and systems are disclosed. In one embodiment, a non-volatile memory device receives command signals through the same input/output terminals that receive address signals and write data signals and transmit read data signals. The input/output terminals are connected to a multiplexer, which is responsive to a received mode control signal to couple the input/output terminals to either a command bus or an input/output bus. A latch in the memory device latches the command signals when the mode control signal causes the input/output terminals to be coupled to the input/output bus. As a result, the command signals continue to be applied to the command bus. When the mode control signal causes the input/output terminals to be coupled to the input/output bus, write data signals are clocked into the memory device and read data signals are clocked out of the memory device responsive to a received clock signal. | 01-12-2012 |
| 20120007256 | REDISTRIBUTION LAYERS FOR MICROFEATURE WORKPIECES, AND ASSOCIATED SYSTEMS AND METHODS - Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a pre-formed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device. | 01-12-2012 |
| 20120007209 | SEMICONDUCTOR DEVICE STRUCTURES INCLUDING DAMASCENE TRENCHES WITH CONDUCTIVE STRUCTURES AND RELATED METHOD - A method and apparatus for providing a conductive structure adjacent to a damascene conductive structure in a semiconductor device structure. The semiconductor device structure includes an insulation layer with at least one damascene conductive structure formed therein, wherein the at least one damascene conductive structure includes an insulative, protective layer disposed thereon. The insulative material of the protective layer is able to resist removal by at least some suitable etchants for the insulative material of the insulation layer adjacent to the at least one damascene conductive structure. A self-aligned opening is formed by removing a portion of an insulation layer adjacent the at least one damascene conductive structure. The self-aligned opening is then filled with a conductive material to thereby provide another conductive structure adjacent to the at least one damascene conductive structure. | 01-12-2012 |
| 20120005411 | NON-VOLATILE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY - Example embodiments for configuring a serial non-volatile memory device may comprise a non-volatile configuration register to store a configuration value received from the processor, the configuration value to specify one or more attributes of a memory access operation. The configuration value may be read at least in part in response to power being applied to the memory device. | 01-05-2012 |
| 20120003810 | SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE - A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor. | 01-05-2012 |
| 20120003573 | Photomasks - Some embodiments include methods of forming photomasks. A stack of at least three different materials is formed over a base. Regions of the stack are removed to leave a mask pattern over the base. The mask pattern includes a pair of spaced-apart adjacent segments of the stack. A liner is formed to cover sidewalls of the segments. Some embodiments include photomasks. The photomasks may include a transparent base supporting a pair of spaced-apart adjacent features. The spaced-apart adjacent features may include sidewalls, with inner sidewalls of the spaced-apart features being adjacent one another, and spaced from one another by a gap. A coating layer of from about 5 Angstroms thick to about 50 Angstroms thick may be along the entirety of the sidewalls of the spaced-apart adjacent features. Some embodiments include methods of photolithographically patterning substrates. | 01-05-2012 |
| 20120002489 | SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL - A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage. | 01-05-2012 |
| 20120002467 | SINGLE TRANSISTOR MEMORY CELL - A semiconductor device along with circuits including same and methods of operating same are disclosed. In one particular embodiment, the device may comprise a memory cell including a transistor. The transistor may comprise a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device may be refreshed during hold operations. | 01-05-2012 |
| 20120002465 | METHODS, STRUCTURES, AND DEVICES FOR REDUCING OPERATIONAL ENERGY IN PHASE CHANGE MEMORY - Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material. | 01-05-2012 |
| 20120001682 | APPARATUSES AND METHODS TO REDUCE POWER CONSUMPTION IN DIGITAL CIRCUITS - An apparatus and method for reducing power consumption in digital circuits, particularly circuits including a charge pump. A driver may selectively drive a signal line, such as a memory device wordline, between a first voltage, which may be a voltage generated by the charge pump, and a different second voltage. A coupling circuit may be coupled between the signal line and the charge pump to selectively couple the signal line to the charge pump responsive to the signal line being driven from the first voltage to the second voltage. For example, the first voltage may be a voltage generated by the charge pump, and the second voltage may be a voltage having a lesser magnitude. As a result, the voltage on the signal line may be discharged into the charge pump when the voltage of the signal line transitions from the first voltage to the second voltage. | 01-05-2012 |
| 20120001680 | ISOLATION CIRCUIT - The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor configured for connection to a supply voltage via a first terminal; a register connected to the first transistor; a second transistor in parallel with a resistor, wherein the second transistor is configured for connection to the first terminal, with a gate of the second transistor configured for connection to an output of the register; and wherein the second transistor is configured for connection to a second terminal, the second transistor having a state that depends on a status of the register. | 01-05-2012 |
| 20120001539 | Plasma-Generating Structures, Display Devices, and Methods of Forming Plasma-Generating Structures - Some embodiments include methods of forming plasma-generating microstructures. Aluminum may be anodized to form an aluminum oxide body having a plurality of openings extending therethrough. Conductive liners may be formed within the openings, and circuitry may be formed to control current flow through the conductive liners. The conductive liners form a plurality of hollow cathodes, and the current flow is configured to generate and maintain plasmas within the hollow cathodes. The plasmas within various hollow cathodes, or sets of hollow cathodes, may be independently controlled. Such independently controlled plasmas may be utilized to create a pattern in a display, or on a substrate. In some embodiments, the plasmas may be utilized for plasma-assisted etching and/or plasma-assisted deposition. Some embodiments include constructions and assemblies containing multiple plasma-generating structures. | 01-05-2012 |
| 20120001299 | Semiconductor Constructions - Some embodiments include methods of forming capacitors. A first section of a capacitor may be formed to include a first storage node, a first dielectric material, and a first plate material. A second section of the capacitor may be formed to include a second storage node, a second dielectric material, and a second plate material. The first and second sections may be formed over a memory array region, and the first and second plate materials may be electrically connected to first and second interconnects, respectively, that extend to over a region peripheral to the memory array region. The first and second interconnects may be electrically connected to one another to couple the first and second plate materials to one another. Some embodiments include capacitor structures, and some embodiments include methods of forming DRAM arrays. | 01-05-2012 |
| 20120001248 | METHODS OF FORMING NANOSCALE FLOATING GATE - A memory cell is provided including a tunnel dielectric layer overlying a semiconductor substrate. The memory cell also includes a floating gate having a first portion overlying the tunnel dielectric layer and a second portion in the form of a nanorod extending from the first portion. In addition, a control gate layer is separated from the floating gate by an intergate dielectric layer. | 01-05-2012 |
| 20120001246 | MEMORY DEVICE AND METHOD OF FABRICATING THEREOF - Subject matter disclosed herein relates to a process flow to form a gate structure of a memory device. | 01-05-2012 |
| 20120001245 | Recessed Access Device for a Memory - Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess. | 01-05-2012 |
| 20120001147 | Non-Volatile Resistive Oxide Memory Cells, Non-Volatile Resistive Oxide Memory Arrays, And Methods Of Forming Non-Volatile Resistive Oxide Memory Cells And Memory Arrays - A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated. | 01-05-2012 |
| 20120001144 | RESISTIVE RAM DEVICES AND METHODS - The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element. | 01-05-2012 |
| 20110318921 | Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM - The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure. Other aspects and implementations are contemplated. | 12-29-2011 |
| 20110318899 | Methods of Forming Capacitors - Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O | 12-29-2011 |
| 20110317509 | MEMORY DEVICE WORD LINE DRIVERS AND METHODS - Memory subsystems and methods, such as those involving a memory cell array formed over a semiconductor material of a first type, such as p-type substrate. In at least one such subsystem, all of the transistors used to selectively access cells within the array are transistors of a second type, such as n-type transistors. Local word line drivers are coupled to respective word lines extending through the array. Each local word line drivers includes at least one transistor. However, all of the transistors in the local word line drivers are of the second type. A well of semiconductor material of the second type, is also formed in the material of the first type, and a plurality of global word line drivers are formed using the well. Each global word line driver includes at least one transistor of the first type. Other subsystems and methods are disclosed. | 12-29-2011 |
| 20110317502 | CONTROL OF INPUTS TO A MEMORY DEVICE - A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode. | 12-29-2011 |
| 20110317473 | SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE - The present disclosure includes devices, methods, and systems for programming memory, such as resistance variable memory. One embodiment can include an array of resistance variable memory cells, wherein the resistance variable memory cells are coupled to one or more data lines, a row decoder connected to a first side of the array, a column decoder connected to a second side of the array, wherein the second side is adjacent to the first side, a gap located adjacent to the row decoder and the column decoder, and clamp circuitry configured to control a reverse bias voltage associated with one or more unselected memory cells during a programming operation, wherein the clamp circuitry is located in the gap and is selectively coupled to the one or more data lines. | 12-29-2011 |
| 20110317046 | MISSING PIXEL ARRAY - An active pixel sensor (APS) comprises a regular repeating pattern of geometrically similar pixel regions, active pixels of which have photodiodes formed therein. A remainder of the geometrically similar regions has electrical components shared amongst neighboring photodiodes, such as for collecting and amplifying signals from the photodiodes. A 4-way sharing arrangement is shown, with four active pixel regions aligned in a column and the shared electrical components in a pixel region, the pixel region being shaped and sized similarly to the active pixel regions, in an adjacent column. | 12-29-2011 |
| 20110316726 | LOW POWER MULTI-LEVEL SIGNALING - Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output. | 12-29-2011 |
| 20110316599 | MULTI-PHASE CLOCK GENERATION - An apparatus and method for multi-phase clock generation are disclosed. One embodiment of the apparatus includes a module generating first and second intermediate signals delayed from first edges of a clock signal having a first frequency. Each of the first and second intermediate signals has a second frequency that is half of the first frequency. The first and second intermediate signals have a phase difference of 180° from each other. The apparatus also includes a first delay line delaying the first intermediate signal by a first delay amount; a second delay line delaying the first intermediate signal by a second delay amount; a third delay line delaying the second intermediate signal by a third delay amount; and a fourth delay line delaying the second intermediate signal by a fourth delay amount. The apparatus also includes a closed feedback loop for detecting and adjusting the second and fourth delay amount. | 12-29-2011 |
| 20110316512 | VOLTAGE TRIMMING - Embodiments are provided that include a memory die, memory devices, and methods, such as those comprising a voltage generator, including an output voltage and an adjustment circuit configured to cause adjustment of the output voltage based on a latch signal. Further one such method includes applying an input voltage to an input of a voltage generator, adjusting the input voltage to an adjusted voltage, comparing the adjusted voltage to a reference voltage, generating trim data based on the comparison and storing the trim data. | 12-29-2011 |
| 20110316125 | INTERMEDIATE STRUCTURES FOR FORMING CIRCUITS - In order to form a more stable silicon pillar which can be used for the formation of vertical transistors in DRAM cells, a multi-step masking process is used. In a preferred embodiment, an oxide layer and a nitride layer are used as masks to define trenches, pillars, and active areas in a substrate. Preferably, two substrate etch processes use the masks to form three levels of bulk silicon. | 12-29-2011 |
| 20110316114 | SIMPLIFIED PITCH DOUBLING PROCESS FLOW - A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material. | 12-29-2011 |
| 20110316091 | Semiconductor Devices, Assemblies And Constructions - Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material. | 12-29-2011 |
| 20110316068 | FLASH MEMORY WITH RECESSED FLOATING GATE - A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell. | 12-29-2011 |
| 20110316042 | THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants. | 12-29-2011 |
| 20110315944 | RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include conformally forming a cell material in an opening in an interlayer dielectric such that a seam is formed in the cell material, forming a conductive pathway by modifying the seam, and forming an electrode on the cell material and the seam. | 12-29-2011 |
| 20110315543 | FORMING MEMORY USING HIGH POWER IMPULSE MAGNETRON SPUTTERING - Forming memory using high power impulse magnetron sputtering is described herein. One or more method embodiments include forming a resistive memory material on a structure using high power impulse magnetron sputtering (HIPIMS), wherein the resistive memory material is formed on the structure in an environment having a temperature of approximately 400 degrees Celsius or less. | 12-29-2011 |
| 20110314215 | MULTI-PRIORITY ENCODER - A multi-priority encoder includes a plurality of interconnected, single-priority encoders arranged in descending priority order. The multi-priority encoder includes circuitry for blocking a match output by a lower level single-priority encoder if a higher level single-priority encoder outputs a match output Match data is received from a content addressable memory, and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator. Each single-priority encoder includes a highest priority indicator which has a plurality of indicator segments, each indicator segment being associated with a match line input. | 12-22-2011 |
| 20110310689 | POWER SOURCE AND POWER SOURCE CONTROL CIRCUIT - Power sources, backup power circuits, power source control circuits, data storage devices, and methods relating to controlling application of power to a node are disclosed. An example power source includes an input, backup power source, and a backup power source control circuit. The input is configured to be coupled to a primary power source and further configured to couple the primary power source to the output when the input is coupled to the primary power source. The backup power source control circuit is configured to control a current path from the backup power source to the output based at least in part on a voltage applied to the input. | 12-22-2011 |
| 20110310687 | CURRENT SENSE AMPLIFIERS, MEMORY DEVICES AND METHODS - A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals. | 12-22-2011 |
| 20110310679 | DEVICES, SYSTEMS, AND METHODS FOR A POWER GENERATOR SYSTEM - Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference voltage and the second reference voltage. The power generator system may also include a power generator operably coupled to the control device, and the power generator may be configured to receive the first reference voltage and the second reference voltage and to output a voltage that is greater than or substantially equal to the first reference voltage and less than or substantially equal to the second reference voltage. | 12-22-2011 |
| 20110310661 | MEMORY SENSING DEVICES, METHODS, AND SYSTEMS - The present disclosure includes devices, methods, and systems for sensing memory, such as resistance variable memory, among other types of memory. One or more embodiments can include a method for generating currents to be used in sensing a memory cell, the method including providing a number of initial currents, and generating a number of reference currents by summing particular combinations of the initial currents. | 12-22-2011 |
| 20110309506 | CONDUCTIVE INTERCONNECT STRUCTURES AND FORMATION METHODS USING SUPERCRITICAL FLUIDS - Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via. | 12-22-2011 |
| 20110309393 | PACKAGED LEDS WITH PHOSPHOR FILMS, AND ASSOCIATED SYSTEMS AND METHODS - Packaged LEDs with phosphor films, and associated systems and methods are disclosed. A system in accordance with a particular embodiment of the disclosure includes a support member having a support member bond site, an LED carried by the support member and having an LED bond site, and a wire bond electrically connected between the support member bond site and the LED bond site. The system can further include a phosphor film carried by the LED and the support member, the phosphor film being positioned to receive light from the LED at a first wavelength and emit light at a second wavelength different than the first. The phosphor film can be positioned in direct contact with the wire bond at the LED bond site. | 12-22-2011 |
| 20110309324 | SOLID STATE DEVICES WITH SEMI-POLAR FACETS AND ASSOCIATED METHODS OF MANUFACTURING - Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material. | 12-22-2011 |
| 20110309319 | HORIZONTALLY ORIENTED AND VERTICALLY STACKED MEMORY CELLS - Horizontally oriented and vertically stacked memory cells are described herein. One or more method embodiments include forming a vertical stack having a first insulator material, a first memory cell material on the first insulator material, a second insulator material on the first memory cell material, a second memory cell material on the second insulator material, and a third insulator material on the second memory cell material, forming an electrode adjacent a first side of the first memory cell material and a first side of the second memory cell material, and forming an electrode adjacent a second side of the first memory cell material and a second side of the second memory cell material. | 12-22-2011 |
| 20110305021 | SOLID STATE LIGHTING DEVICE WITH DIFFERENT ILLUMINATION PARAMETERS AT DIFFERENT REGIONS OF AN EMITTER ARRAY - Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a plurality of SSL emitters carried by the support. The emitter array has a central region and a peripheral region outward from the central region. Individual SSL emitters in both the central and the peripheral regions have a primary emission direction along which an intensity of light from the SSL emitters is highest, and the primary emission direction of the SSL emitters in the central region is at least substantially the same direction as the primary emission direction of the SSL emitters in the peripheral region. Additionally, a first coverage area ratio of the SSL emitters in the central region is different than a second coverage area ratio of the SSL emitters in the peripheral region. | 12-15-2011 |
| 20110304358 | TRANSISTOR VOLTAGE THRESHOLD MISMATCH COMPENSATED SENSE AMPLIFIERS AND METHODS FOR PRECHARGING SENSE AMPLIFIERS - Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored. | 12-15-2011 |
| 20110303957 | Concentric or Nested Container Capacitor Structure for Integrated Circuits - Disclosed are embodiments for a container capacitor structure in which at least two container capacitors, e.g., an inner and outer container capacitor, are made concentric and nested with respect to one another. The nested capacitors are formed in one embodiment by defining a hole in a dielectric layer for the nested container capacitors in the vicinity of two capacitor contact plugs. An outer capacitor plate is formed by etching back poly | 12-15-2011 |
| 20110303929 | MULTI-DIMENSIONAL LED ARRAY SYSTEM AND ASSOCIATED METHODS AND STRUCTURES - A formed, multi-dimensional light-emitting diode (LED) array is disclosed. A substrate is bent into a trapezoidal shape having different sections facing in different directions. Each section has one or more mounted LEDs that emit light with an azimuthally non-circular, monotonic angular distribution. A converter material is placed in an optical path of the LEDs to alter characteristics of the light from the LEDs. | 12-15-2011 |
| 20110302470 | TEST MODE FOR PARALLEL LOAD OF ADDRESS DEPENDENT DATA TO ENABLE LOADING OF DESIRED DATA BACKGROUNDS - One or more embodiments of the invention enable a memory device to load its memory array with desired background data, such as to reduce total test time and costs associated with testing. A background data loading circuit according to one embodiment of the invention includes a buffer, a data loading circuit, and a pattern generating logic. The buffer is coupled to the array of memory cells. The data loading circuit is coupled to load data into the buffer to be transferred to a respective row of the memory cells. The pattern generating logic is coupled to the data loading circuit. The pattern generating logic applies a pattern generating algorithm corresponding to a test mode when the memory devices is in the test mode and generates patterns of data each for a respective row of the memory cells according to the pattern generating algorithm. The pattern generating logic further causes the data loading circuit to load each of the generated patterns of data into the buffer for transferring to a respective row of the memory cells. | 12-08-2011 |
| 20110301383 | Beta-Diketiminate Ligand Sources and Metal-Containing Compounds Thereof, and Systems and Methods Including Same - The present invention provides metal-containing compounds that include at least one β-diketiminate ligand, and methods of making and using the same. In certain embodiments, the metal-containing compounds include at least one β-diketiminate ligand with at least one fluorine-containing organic group as a substituent. In other certain embodiments, the metal-containing compounds include at least one β-diketiminate ligand with at least one aliphatic group as a substituent selected to have greater degrees of freedom than the corresponding substituent in the β-diketiminate ligands of certain metal-containing compounds known in the art. The compounds can be used to deposit metal-containing layers using vapor deposition methods. Vapor deposition systems including the compounds are also provided. Sources for β-diketiminate ligands are also provided. | 12-08-2011 |
| 20110300782 | APPARATUSES AND METHODS FOR CONDITIONING POLISHING PADS USED IN POLISHING MICRO-DEVICE WORKPIECES - Apparatuses and methods for conditioning polishing pads used in polishing micro-device workpieces are disclosed herein. In one embodiment, an end effector for conditioning a polishing pad includes a member having a first surface and a plurality of contact elements projecting from the first surface. The member also includes a plurality of apertures configured to flow conditioning solution to the polishing pad. The apertures can extend from the first surface to a second surface opposite the first surface. The member can further include a manifold that is in fluid communication with the apertures. In another embodiment, a conditioner for conditioning the polishing pad includes an arm having at least one spray nozzle configured to spray conditioning solution onto the polishing pad and an end effector coupled to the arm. The end effector includes a first surface and a plurality of contact elements projecting from the first surface. | 12-08-2011 |
| 20110300721 | Methods of Making Crystalline Tantalum Pentoxide - There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content. | 12-08-2011 |
| 20110300689 | Methods of Forming Trench Isolation in the Fabrication of Integrated Circuitry and Methods of Fabricating Integrated Circuitry - First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material. The spin-on-dielectric is densified within the second isolation trench. | 12-08-2011 |
| 20110298512 | CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY - A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency. | 12-08-2011 |
| 20110298504 | CLOCK GENERATOR AND METHODS USING CLOSED LOOP DUTY CYCLE CORRECTION - Closed-loop duty-cycle correctors (DCCs), clock generators, memory devices, systems, and methods for generating an output clock signal having a particular duty cycle are provided, such as clock generators configured to generate an output clock signal synchronized with a received input clock signal having a predetermined duty cycle. Embodiments of clock generators include closed-loop duty cycle correctors that receive an already-controlled and corrected output signal. For example, DLL control circuitry and DCC control circuitry may each adjust a delay of a variable delay line. The DLL control circuitry adjusts the delay such that an output clock signal is synchronized with an input clock signal. The DCC control circuitry detects a duty cycle error in the output clock signal and adjusts the delay of the variable delay line to achieve a duty cycle corrected output signal. By detecting the duty cycle error in the output signal, the clock generator may achieve improved performance that can correct accumulated duty cycle error and correct for duty cycle error introduced by the duty cycle corrector itself in some embodiments. | 12-08-2011 |
| 20110298494 | METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER - Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry that provide voltages to thin-gate dielectric transistors. One such buffer may include a primary pull-up pre-driver operably coupled to a primary pull-up transistor; a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor; a primary pull-down pre-driver operably coupled to a primary pull-down transistor; and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. The pre-drivers may provide a sufficiently low voltage to a gate of a transistor operably coupled thereto so as to sustain a gate dielectric integrity of the transistor, wherein at least one of the primary pull-up pre-driver, the secondary pull-up pre-driver, primary pull-down pre-driver, and the secondary pull-down pre-driver is configured to provide a voltage greater than or equal to a ground voltage and less than or equal to a supply voltage. | 12-08-2011 |
| 20110298014 | Cross-Point Memory Structures - Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction. | 12-08-2011 |
| 20110298007 | SELECT DEVICES INCLUDING AN OPEN VOLUME, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FOR FORMING SAME - Select devices including an open volume that functions as a high bandgap material having a low dielectric constant are disclosed. The open volume may provide a more nonlinear, asymmetric I-V curve and enhanced rectifying behavior in the select devices. The select devices may comprise, for example, a metal-insulator-insulator-metal (MIIM) diode. Various methods may be used to form select devices and memory systems including such select devices. Memory devices and electronic systems include such select devices. | 12-08-2011 |
| 20110297927 | OXIDE BASED MEMORY - Methods, devices, and systems associated with oxide based memory are described herein. In one or more embodiments, a method of forming an oxide based memory cell includes forming a first electrode, forming a tunnel barrier, wherein a first portion of the tunnel barrier includes a first material and a second portion of the tunnel barrier includes a second material, forming an oxygen source, and forming a second electrode. | 12-08-2011 |
| 20110296227 | MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM - A memory system and method uses stacked memory device dice coupled to each other and to a logic die. The logic die may include a timing correction system that is operable to control the timing at which the logic die receives signals, such as read data signals, from each of the memory device dice. The timing correction controls the timing of the read data or other signals by adjusting the timing of respective strobe signals, such as read strobe signals, that are applied to each of the memory device dice. The memory device dice may transmit read data to the memory device at a time determined by when it receives the respective strobe signals. The timing of each of the strobe signals is adjusted so that the read data or other signals from all of the memory device dice are received at the same time. | 12-01-2011 |
| 20110296144 | REDUCING DATA HAZARDS IN PIPELINED PROCESSORS TO PROVIDE HIGH PROCESSOR UTILIZATION - A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data. | 12-01-2011 |
| 20110296077 | MEMORY HUB ARCHITECTURE HAVING PROGRAMMABLE LANE WIDTHS - A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus. | 12-01-2011 |
| 20110294294 | PROTECTIVE COATING FOR PLANARIZATION - Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane. | 12-01-2011 |
| 20110293833 | Zwitterionic Block Copolymers and Methods - Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic block copolymers can undergo microphase separation. | 12-01-2011 |
| 20110291237 | LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film. | 12-01-2011 |
| 20110291224 | EFFICIENT PITCH MULTIPLICATION PROCESS - Pitch multiplied and non-pitch multiplied features of an integrated circuit, e.g., features in the array, interface and periphery areas of the integrated circuit, are formed by processing a substrate through a mask. The mask is formed by patterning a photoresist layer which simultaneously defines mask elements corresponding to features in the array, interface and periphery areas of the integrated circuit. The pattern is transferred to an amorphous carbon layer. Sidewall spacers are formed on the sidewalls of the patterned amorphous carbon layer. A layer of protective material is deposited and then patterned to expose mask elements in the array region and in selected parts of the interface or periphery areas. Amorphous carbon in the array region or other exposed parts is removed, thereby leaving a pattern including free-standing, pitch multiplied spacers in the array region. The protective material is removed, leaving a pattern of pitch multiplied spacers in the array region and non-pitch multiplied mask elements in the interface and periphery areas. The pattern is transferred to a hard mask layer, through which an underlying substrate is etched. | 12-01-2011 |
| 20110291146 | DRY FLUX BONDING DEVICE AND METHOD - Methods of forming devices, including LED devices, are described. The devices may include fluorinated compound layers. The methods described may utilize a plasma treatment to form the fluorinated compound layers. The methods described may operate to produce an intermetallic layer that bonds two substrates such as semiconductor wafers together in a relatively efficient and inexpensive manner. | 12-01-2011 |
| 20110291065 | PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS - Phase change memory cell structures and methods are described herein. A number of methods of forming a phase change memory cell structure include forming a dielectric stack structure on a first electrode, wherein forming the dielectric stack structure includes creating a second region between a first region and a third region of the dielectric stack structure, the second region having a thermal conductivity different than a thermal conductivity of the first region and different than a thermal conductivity of the third region of the dielectric stack. One or more embodiments include forming a via through the first, second, and third regions of the dielectric stack structure, depositing a phase change material in the via, and forming a second electrode on the phase change material. | 12-01-2011 |
| 20110291064 | RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS - Resistance variable memory cell structures and methods are described herein. One or more resistance variable memory cell structures include a first electrode common to a first and a second resistance variable memory cell, a first vertically oriented resistance variable material having an arcuate top surface in contact with a second electrode and a non-arcuate bottom surface in contact with the first electrode; and a second vertically oriented resistance variable material having an arcuate top surface in contact with a third electrode and a non-arcuate bottom surface in contact with the first electrode. | 12-01-2011 |
| 20110287630 | Methods of Processing Semiconductor Substrates In Forming Scribe Line Alignment Marks - A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning. | 11-24-2011 |
| 20110287581 | SEMICONDUCTOR WORKPIECE CARRIERS AND METHODS FOR PROCESSING SEMICONDUCTOR WORKPIECES - Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable carrier includes a base and an adhesive layer on the base. The base has a surface, and the adhesive layer covers only a section of the surface of the base. The adhesive layer releasably attaches the replaceable carrier to the support structure. | 11-24-2011 |
| 20110287572 | SEMICONDUCTOR DEVICE FABRICATION METHODS - Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices. | 11-24-2011 |
| 20110286282 | SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD - Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines. | 11-24-2011 |
| 20110285029 | SEMICONDUCTOR STRUCTURES INCLUDING TIGHT PITCH CONTACTS - Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines. | 11-24-2011 |
| 20110284960 | NON-PLANAR THIN FIN TRANSISTOR - Methods for fabricating a non-planar transistor. Fin field effect transistors (finFETs) are often built around a fin (e.g., a tall, thin semiconductive member). During manufacturing, a fin may encounter various mechanical stresses, e.g., inertial forces during movement of the substrate and fluid forces during cleaning steps. If the forces on the fin are too large, the fin may fracture and possibly render a transistor inoperative. Supporting one side of a fin before forming the second side of a fin creates stability in the fin structure, thereby counteracting many of the mechanical stresses incurred during manufacturing. | 11-24-2011 |
| 20110284940 | Semiconductor Constructions And Electronic Systems - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory. | 11-24-2011 |
| 20110281434 | Methods of Forming Patterned Photoresist Layers Over Semiconductor Substrates - This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated. | 11-17-2011 |
| 20110281414 | SEMICONDUCTOR PROCESSING - Devices, methods, and systems for semiconductor processing are described herein. A number of method embodiments of semiconductor processing can include forming a silicon layer on a structure, forming an opening through the silicon layer and into the structure, and selectively forming a resistance variable material in the opening such that the resistance variable material does not form on the silicon layer. | 11-17-2011 |
| 20110280091 | MEMORY REPAIR SYSTEMS AND METHODS FOR A MEMORY HAVING REDUNDANT MEMORY - Memories, memory repair logic, and methods for repairing a memory having redundant memory are disclosed. One such memory includes programmable elements associated with respective redundant memory configured to have memory addresses mapped thereto, the programmable elements configured to be programmed with at least portions of the memory addresses. Such a memory further includes repair logic coupled to the programmable elements and configured to identify programmable elements available for programming to map memory addresses to respective redundant memory. One method for remapping a memory address of a memory to redundant memory includes receiving at least a portion of a memory address to be remapped to redundant memory, determining whether a programmable element associated with the redundant memory is available for programming, and when a programmable element is available, programming the programmable element such that the memory address will be mapped to the associated redundant memory. | 11-17-2011 |
| 20110280089 | DATA BUS POWER-REDUCED SEMICONDUCTOR STORAGE APPARATUS - In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system. | 11-17-2011 |
| 20110280084 | DETERMINING AND USING SOFT DATA IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes methods, devices, and systems for determining and using soft data in memory devices and systems. One or more embodiments include an array of memory cells and control circuitry coupled to the array. The control circuitry is configured to perform a number of sense operations on the memory cells using a number of sensing voltages to determine soft data associated with a target state of the memory cells, and adjust a sensing voltage used to determine the target state based, at least partially, on the determined soft data. | 11-17-2011 |
| 20110280063 | SPINTRONIC DEVICES WITH INTEGRATED TRANSISTORS - The semiconductor industry seeks to replace traditional volatile memory devices with improved non-volatile memory devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development of integrated Giant-Magneto-resistive (GMR) structures. The present teachings relates to integrated latch memory and logic devices and, in particular, concerns a spin dependent logic device that may be integrated with conventional semiconductor-based logic devices to construct high-speed non-volatile static random access memory (SRAM) cells. | 11-17-2011 |
| 20110279465 | MEMORY SYSTEM HAVING MULTIPLE ADDRESS ALLOCATION FORMATS AND METHOD FOR USE THEREOF - A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array. | 11-17-2011 |
| 20110279159 | CIRCUITS AND METHODS FOR CLOCK SIGNAL DUTY-CYCLE CORRECTION - Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion. | 11-17-2011 |
| 20110277323 | Method for Forming a Circuit Board Via Structure for High Speed Signaling - One embodiment of the invention comprises an improved method for making a via structure for use in a printed circuit board (PCB). The via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal plane. To minimize EM disturbance between the power and ground planes, signal loss due to signal return current, and via-to-via coupling, the via is shielded within two concentric cylinders, each coupled to one of the power and ground planes. | 11-17-2011 |
| 20110275211 | Methods of Etching Nanodots, Methods of Removing Nanodots From Substrates, Methods of Fabricating Integrated Circuit Devices, Methods of Etching a Layer Comprising a Late Transition Metal, and Methods of Removing a Layer Comprising a Late Transition Metal From a Substrate - Embodiments of the invention include methods of etching nanodots, to methods of removing nanodots from substrates, and to methods of fabricating integrated circuit devices. In one embodiment, a method of etching nanodots that include a late transition metal includes exposing such nanodots to a gas comprising a phosphorus and halogen-containing compound and an oxidizing agent. After the exposing, the nanodots which are remaining and were exposed are etched (either partially or completely) with an aqueous solution comprising HF. | 11-10-2011 |
| 20110274215 | Method and Apparatus for Training the Reference Voltage Level and Data Sample Timing in a Receiver - Methods and apparatuses for calculating the location of an optimal sampling point for a receiver system are disclosed. In brief, a first method comprises determining a maximum voltage margin and a maximum timing margin of a received signal, and from these margins, determining an optimal sampling point, which includes a reference voltage level (Vref) and a relative sample phase. The location of the optimal sampling point is based on the locations of the sampling point of the maximum voltage margin and the sampling point of the maximum timing margin. A second method comprises establishing an initial sampling point, and then successively refining each of the voltage and timing components of the sampling point until an optimal sampling point is reached. | 11-10-2011 |
| 20110273942 | Memory Array Having a Programmable Word Length, and Method of Operating Same - A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed. | 11-10-2011 |
| 20110273932 | NON-VOLATILE MEMORY WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - Memory arrays and methods of operating such memory arrays are described as having a memory cell operated as a single level cell interposed between and coupled to a select gate and a memory cell operated as a multiple level memory cell. In some embodiments, a memory array is described as including a number of select gates coupled in series to a number of memory cells operated as single level memory cells and a number of memory cells operated as multiple level memory cells, where a first select gate is directly coupled to a first memory cell operated as a single level memory cell interposed between and coupled to the first select gate and a continuous number of memory cells operated as multiple level memory cells. | 11-10-2011 |
| 20110273185 | METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS - Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad. | 11-10-2011 |
| 20110272806 | SEMICONDUCTOR DICE INCLUDING AT LEAST ONE BLIND HOLE, WAFERS INCLUDING SUCH SEMICONDUCTOR DICE, AND INTERMEDIATE PRODUCTS MADE WHILE FORMING AT LEAST ONE BLIND HOLE IN A SUBSTRATE - Semiconductor dice comprise at least one bond pad on an active surface of the semiconductor die. At least one blind hole extends from a back surface of the semiconductor die opposing the active surface, through a thickness of the semiconductor die, to an underside of the at least one bond pad. At least one quantity of passivation material covers at least a sidewall surface of the at least one blind hole. At least one conductive material is disposed in the at least one blind hole adjacent and in electrical communication with the at least one bond pad and adjacent the at least one quantity of passivation material. | 11-10-2011 |
| 20110272660 | RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY - Resistive memory and methods of processing resistive memory are described herein. One or more method embodiments of processing resistive memory include forming a resistive memory cell material on an electrode having an access device contact, and forming a heater electrode on the resistive memory cell material after forming the resistive memory cell material on the electrode such that the heater electrode is self-aligned to the resistive memory cell material. | 11-10-2011 |
| 20110272606 | ZINC OXIDE DIODES FOR OPTICAL INTERCONNECTIONS - The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has an input coupled to the ZnO emitter. A detector is coupled to an output of the optical waveguide. | 11-10-2011 |
| 20110271158 | METHOD AND APPARATUS FOR TESTING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES - A plurality of stacked memory device die and a logic circuit are connected to each other through a plurality of conductors. The stacked memory device die are arranged in a plurality of vaults. The logic circuit die serves as a memory interface device to a memory access device, such as a processor. The logic circuit die includes a plurality of link interfaces and downstream targets for transmitting received data to the vaults. The logic circuit die includes a packet builder and broadcaster configured to receive command, address and data signals over separate interfaces from a conventional tester, format the signals into a packet and broadcast the signals to a plurality of vaults. | 11-03-2011 |
| 20110271038 | INDEXED REGISTER ACCESS FOR MEMORY DEVICE - Example embodiments of a non-volatile memory device may comprise receiving an index value at one or more input terminals of a memory device and storing the index value in a first register of the memory device. The first register may be implemented in a first clock domain, and the index value may identify a second register of the memory device implemented in a second clock domain. | 11-03-2011 |
| 20110269288 | Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts - The invention included to methods of forming CoSi | 11-03-2011 |
| 20110269252 | METHOD FOR POSITIONING SPACERS FOR PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 11-03-2011 |
| 20110267912 | DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB ARRAYS - A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other. | 11-03-2011 |
| 20110267362 | GAMMA VARIATION USING ILLUMINATION INTENSITY - A gamma variation of image intensity is created by varying the illumination intensity during a pulse width modulated display time period. During the pulse width modulated display time period a ramp signal may be compared with the image data to determine when pixel electrodes of the pixel array are switched. The illumination intensity may be varied in concert with ramp signal to produce a quadratic variation of displayed intensity on image data value. The illumination source could be an LED illumination source and intensity of the LED illumination source could be controlled using pulse width modulation. | 11-03-2011 |
| 20110266701 | NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME - A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body. | 11-03-2011 |
| 20110266696 | SEMICONDUCTOR DEVICE PACKAGES INCLUDING A SEMICONDUCTOR DEVICE AND A REDISTRIBUTION ELEMENT - A method for fabricating a chip-scale board-on-chip substrate, or redistribution element, includes forming conductive planes on opposite sides of a substrate. A first of the conductive planes includes two sets of bond fingers, conductive traces that extend from a first set of the bond fingers, and two sets of redistributed bond pads, including a first set to which the conductive traces lead. The second conductive plane includes conductive traces that extend from locations that are opposite from the second set of bond fingers toward locations that are opposite from the locations of the second set of redistributed bond pads. Conductive vias are formed through the second set of bond fingers to the conductive traces of the second conductive plane. In addition, conductive vias are also formed to electrically connect the conductive vias of the second conductive plane to their corresponding redistributed bond pads in the first conductive plane. Redistribution elements including these features, as well as semiconductor device assemblies including the redistribution elements and assembly methods, are also disclosed. | 11-03-2011 |
| 20110266694 | METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURES AND DEVICES INCLUDING NANOTUBES, AND SEMICONDUCTOR STRUCTURES, DEVICES, AND SYSTEMS FABRICATED USING SUCH METHODS - A method of forming a plurality of nanotubes is disclosed. Particularly, a substrate may be provided and a plurality of recesses may be formed therein. Further, a plurality of nanotubes may be formed generally within each of the plurality of recesses and the plurality of nanotubes may be substantially surrounded with a supporting material. Additionally, at least some of the plurality of nanotubes may be selectively shortened and at least a portion of the at least some of the plurality of nanotubes may be functionalized. Methods for forming semiconductor structures intermediate structures, and semiconductor devices are disclosed. An intermediate structure, intermediate semiconductor structure, and a system including nanotube structures are also disclosed. | 11-03-2011 |
| 20110266689 | Methods Of Forming A Plurality Of Conductive Lines In The Fabrication Of Integrated Circuitry, Methods Of Forming An Array Of Conductive Lines, And Integrated Circuitry - A method of forming a pair of conductive lines in the fabrication of integrated circuitry includes forming a trench into a damascene material received over a substrate. Conductive material is deposited over the damascene material and to within the trench to overfill the trench. The conductive material is removed back at least to the damascene material to leave at least some of the conductive material remaining in the trench. Etching is conducted longitudinally through the conductive material within the trench to form first and second conductive lines within the trench which are mirror images of one another in lateral cross section along at least a majority of length of the first and second conductive lines. Other implementations are contemplated. | 11-03-2011 |
| 20110266647 | Methods of Forming Isolated Active Areas, Trenches, and Conductive Lines in Semiconductor Structures and Semiconductor Structures Including the Same - Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed. | 11-03-2011 |
| 20110266610 | MEMORY DEVICES HAVING REDUCED INTERFERENCE BETWEEN FLOATING GATES AND METHODS OF FABRICATING SUCH DEVICES - A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array. | 11-03-2011 |
| 20110263135 | Semiconductor Processing Methods, And Methods For Forming Silicon Dioxide - Some embodiments include methods for semiconductor processing. A semiconductor substrate may be placed within a reaction chamber. The semiconductor substrate may have an inner region and an outer region laterally outward of said inner region, and may have a deposition surface that extends across the inner and outer regions. The semiconductor substrate may be heated by radiating thermal energy from the outer region to the inner region. The heating may eventually achieve thermal equilibrium. However, before thermal equilibrium of the outer and inner regions is reached, and while the outer region is warmer than the inner region, at least two reactants are sequentially introduced into the reaction chamber. The reactants may together form a single composition on the deposition surface through a quasi-ALD process. | 10-27-2011 |
| 20110260778 | Semiconductor Temperature Sensor Using Bandgap Generator Circuit - A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature. | 10-27-2011 |
| 20110260298 | SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON AND METHOD OF FORMING SAME - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction. | 10-27-2011 |
| 20110260236 | Transistor Constructions and Processing Methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening. | 10-27-2011 |
| 20110258425 | BOOT PARTITIONS IN MEMORY DEVICES AND SYSTEMS - The present disclosure includes boot partitions in memory devices and systems, and methods associated therewith. One or more embodiments include an array of memory cells, wherein the array includes a boot partition and a number of additional partitions. Sequential logical unit identifiers are associated with the additional partitions, and a logical unit identifier that is not in sequence with the sequential logical unit identifiers is associated with the boot partition. | 10-20-2011 |
| 20110258360 | Methods and Systems to Accomplish Variable Width Data Input - Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes. | 10-20-2011 |
| 20110256711 | MICROFEATURE WORKPIECES HAVING CONDUCTIVE INTERCONNECT STRUCTURES FORMED BY CHEMICALLY REACTIVE PROCESSES, AND ASSOCIATED SYSTEMS AND METHODS - Microfeature workpieces having conductive vias formed by chemically reactive processes, and associated systems and methods are disclosed. A method in accordance with one embodiment includes disposing a conductive lining on walls of a via in a microfeature workpiece, so that a space is located between opposing portions of the lining facing toward each other from opposing portions of the wall. The method can further include chemically reacting the lining with a reactive material to form a chemical compound from a constituent of the reactive material and a constituent of the lining. The method can still further include at least partially filling the space with the compound. In particular embodiments, the conductive lining includes copper, the reactive material includes sulfur hexafluoride, and the chemical compound that at least partially fills the space in the via includes copper sulfide. | 10-20-2011 |
| 20110256706 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method for reducing the effective thickness of a gate oxide using nitrogen implantation and anneal subsequent to dopant implantation and activation is provided. More particularly, the present invention provides a method for fabricating semiconductor devices, for example, transistors, which include a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the polysilicon/gate oxide interface and a relatively small nitrogen concentration within the gate oxide and at the gate oxide/substrate interface. Additionally, the present invention provides a method for fabricating a semiconductor device having a metal gate strap (e.g., a metal silicide layer) disposed over the polysilicon layer thereof, which device includes a hardened gate oxide and which may be characterized by a relatively large nitrogen concentration at the silicide/polysilicon interface to substantially prevent cross-diffusion. | 10-20-2011 |
| 20110256694 | Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect Transistors, Methods of Forming Semiconductor-On-Insulator Substrates, Methods of Forming a Span Comprising Silicon Dioxide, Methods of Cooling Semiconductor Devices, Methods of Forming Electromagnetic Radiation Emitters and Conduits, Methods of Forming Imager Systems, Methods of Forming Nanofluidic Channels, Fluorimetry Methods, and Integrated Circuitry - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 10-20-2011 |
| 20110256644 | MASKS FOR MICROLITHOGRAPHY AND METHODS OF MAKING AND USING SUCH MASKS - Masks for microlithography apparatus, methods for making such masks, and methods for exposing photosensitive materials to form arrays of microfeatures on semiconductor wafers using such masks. In one embodiment, a method of making a mask comprises forming a mask layer on a substrate and identifying a first opening in the mask layer corresponding to a first feature site at which an intensity of the radiation at a focal zone is less than the intensity of the radiation at the focal zone for a second feature site corresponding to a second opening in the mask. The second opening is adjacent or at least proximate the first opening. The method can further include forming a first surface at the first opening and a second surface at the second opening such that radiation passing through the second opening constructively interferes with radiation passing through the first opening at the focal zone. | 10-20-2011 |
| 20110255342 | MEMORY VOLTAGE CYCLE ADJUSTMENT - The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles. | 10-20-2011 |
| 20110254627 | SIGNALING SYSTEMS, PREAMPLIFIERS, MEMORY DEVICES AND METHODS - Signaling systems, preamplifiers, memory devices and methods are disclosed, such as a signaling system that includes a transmitter configured to receive a first digital signal. The transmitter provides a transmitted signal corresponding to the digital signal to a signal path. A receiver system coupled to the signal line includes a preamplifier coupled to receive the transmitted signal from the signal path. The preamplifier includes a common-gate amplifying transistor that is configured to provide an amplified signal. The receiver system also includes a receiver coupled to receive the amplified signal from the preamplifier. The receiver is configured to provide a second digital signal corresponding to the amplified signal received by the receiver. Such a signaling system may be used in a memory device or in any other electronic circuit. | 10-20-2011 |
| 20110254604 | Control of a Variable Delay Line Using Line Entry Point to Modify Line Power Supply Voltage - Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point. | 10-20-2011 |
| 20110254163 | SLEEVE INSULATORS AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor (BLCC) to an active area of a DRAM that utilizes an insulated sleeve structure. A sleeve insulator layer is deposited in an opening to protect one or more conductor layers from conductive contacts formed in the opening. The sleeve insulator layer electrically insulates a conductive plug from the conductor layer and self-aligns the BLCC so as to improve contact plug alignment tolerances between the BLCC and the capacitor or conductive components. | 10-20-2011 |
| 20110254144 | PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES - Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member and at least one die in a stacked configuration attached to the support member. The support member may include a leadframe disposed longitudinally between first and second ends and latitudinally between first and second sides. The leadframe includes a lead extending between the first end and the first side. | 10-20-2011 |
| 20110254129 | ELECTRICAL COMPONENTS FOR MICROELECTRONIC DEVICES AND METHODS OF FORMING THE SAME - Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process. | 10-20-2011 |
| 20110254075 | USE OF DILUTE STEAM AMBIENT FOR IMPROVEMENT OF FLASH DEVICES - A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized. | 10-20-2011 |
| 20110254072 | CHARGE STORAGE STRUCTURES AND METHODS - Methods, devices, and systems associated with charge storage structures in semiconductor devices are described herein. In one or more embodiments, a method of forming nanodots includes forming at least a portion of a charge storage structure over a material by reacting a single-source precursor and a reactant, where the single-source precursor includes a metal and a semiconductor. | 10-20-2011 |
| 20110254067 | DRAM Layout with Vertical FETS and Method of Formation - DRAM cell arrays having a cell area of about 4F | 10-20-2011 |
| 20110253965 | VERTICAL TRANSISTOR PHASE CHANGE MEMORY - Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor. | 10-20-2011 |
| 20110253042 | Methods of Processing Semiconductor Substrates, Electrostatic Carriers for Retaining Substrates for Processing, and Assemblies Comprising Electrostatic Carriers Having Substrates Electrostatically Bonded Thereto - A method of processing a substrate includes physically contacting an exposed conductive electrode of an electrostatic carrier with a conductor to electrostatically bond a substrate to the electrostatic carrier. The conductor is removed from physically contacting the exposed conductive electrode. Dielectric material is applied over the conductive electrode. The substrate is treated while it is electrostatically bonded to the electrostatic carrier. In one embodiment, a conductor is forced through dielectric material that is received over a conductive electrode of an electrostatic carrier to physically contact the conductor with the conductive electrode to electrostatically bond a substrate to the electrostatic carrier. After removing the conductor from the dielectric material, the substrate is treated while it is electrostatically bonded to the electrostatic carrier. Electrostatic carriers for retaining substrates for processing, and such assemblies, are also disclosed. | 10-20-2011 |
| 20110252623 | MICROELECTRONIC DEVICES AND MICROELECTRONIC SUPPORT DEVICES, AND ASSOCIATED ASSEMBLIES AND METHODS - Microelectronic devices, associated assemblies, and associated methods are disclosed herein. For example, certain aspects of the invention are directed toward a microelectronic device that includes a microfeature workpiece having a side and an aperture in the side. The device can further include a workpiece contact having a surface. At least a portion of the surface of the workpiece contact can be accessible through the aperture and through a passageway extending between the aperture and the surface. Other aspects of the invention are directed toward a microelectronic support device that includes a support member having a side carrying a support contact that can be connectable to a workpiece contact of a microfeature workpiece. The device can further include recessed support contact means carried by the support member. The recessed support contact means can be connectable to a second workpiece contact of the microfeature workpiece. | 10-20-2011 |
| 20110250759 | Method to Reduce Charge Buildup During High Aspect Ratio Contact Etch - A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate. | 10-13-2011 |
| 20110250753 | Atomic Layer Deposition Methods - An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H | 10-13-2011 |
| 20110249507 | SENSING MEMORY CELLS - The present disclosure includes methods, devices, modules, and systems for operating memory cells. One method embodiment includes applying a ramping voltage to a control gate of a memory cell and to an analog-to-digital converter (ADC). The aforementioned embodiment of a method also includes detecting an output of the ADC at least partially in response to when the ramping voltage causes the memory cell to trip sense circuitry. | 10-13-2011 |
| 20110249499 | Integrated Circuit Including Memory Array Having a Segmented Bit Line Architecture and Method of Controlling and/or Operating Same - An integrated circuit device (e.g., a logic device or a memory device) having a memory cell array including a plurality of bit lines (e.g., first and second bit lines) and a plurality of bit line segments (e.g., first and second bit line segments) wherein each bit line segment is selectively and responsively coupled to or decoupled from its associated bit line via an associated isolation circuit. The memory cell array further includes a plurality of memory cells, wherein each memory cell includes a transistor having a first region, a second region, a body region, and a gate coupled to an associated word line via an associated word line segment. A first group of memory cells is coupled to the first bit line via the first bit line segment and a second group of memory cells is coupled to the second bit line via the second bit line segment. A plurality of isolation circuits, disposed between each bit line segment and its associated bit line, to responsively couple the associated bit line segment to or disconnect the associated bit line segment from the associated bit line. | 10-13-2011 |
| 20110249494 | MULTIPLE SELECT GATES WITH NON-VOLATILE MEMORY CELLS - Multiple select gates in association with non-volatile memory cells are described. Various embodiments include multiple select gate structure, process, and operation and their applicability for memory devices, modules, and systems. In one embodiment a memory array is described. The memory array includes a number of select gates coupled in series to a number of non-volatile memory cells. A first select gate includes a control gate and a floating gate electrically connected together and a second select gate includes a control gate and a floating gate which are electrically separated by a dielectric layer. | 10-13-2011 |
| 20110249488 | Data Cells with Drivers and Methods of Making and Operating the Same - Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate. | 10-13-2011 |
| 20110248778 | DEVICES COMPRISING COLOSSAL MAGNETOCAPACITIVE MATERIALS AND RELATED METHODS - Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical current flow through the channel region between a source and a drain. The colossal magnetocapacitive material optionally may be disposed between two structures, one or both of which may be electrically conductive, magnetic, or both electrically conductive and magnetic. Methods of fabricating semiconductor devices include forming a colossal magnetocapacitive material close to a channel region between a source and a drain of a transistor, and configuring the colossal magnetocapacitive material to exhibit colossal magnetocapacitance for generating an electrical field in the channel region. Methods of affecting current flow through a transistor include causing a colossal magnetocapacitive material to exhibit colossal magnetocapacitance and generate an electrical field in a channel region of a transistor. | 10-13-2011 |
| 20110248752 | CLOCK SIGNAL GENERATORS HAVING A REDUCED POWER FEEDBACK CLOCK PATH AND METHODS FOR GENERATING CLOCKS - Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal. | 10-13-2011 |
| 20110248385 | METHOD FOR SELECTIVELY FORMING SYMMETRICAL OR ASYMMETRICAL FEATURES USING A SYMMETRICAL PHOTOMASK DURING FABRICATION OF A SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICE - A method for patterning a material during fabrication of a semiconductor device provides for the selective formation of either asymmetrical features or symmetrical features using a symmetrical photomask, depending on which process flow is chosen. The resulting features which are fabricated use spacers formed around a patterned material. If one particular etch is used to remove a base material, symmetrical features result. If two particular etches are used to remove the base material, asymmetrical features remain. | 10-13-2011 |
| 20110247561 | Thermal Chemical Vapor Deposition Methods, and Thermal Chemical Vapor Deposition Systems - One embodiment thermal chemical vapor deposition method includes exposing a substrate within a chamber to first and second deposition precursors effective to thermally chemical vapor deposit a material on the substrate, and exhausting unreacted first and second deposition precursors from the chamber through a vacuum pump via a first exhaust line comprising a filter. A reactive gas is flowed to the material on the substrate, with the reactive gas being reactive with the material. After flowing the reactive gas, an inert purge gas is flowed through the chamber and through the vacuum pump. The flowing of the inert purge gas to the vacuum pump is through a second exhaust line not comprising the filter. The exposing, the flowing of the reactive gas, and the flowing of the inert purge gas are repeated effective to deposit material of desired thickness on the substrate. | 10-13-2011 |
| 20110244404 | Photoresist Processing Methods - A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating. | 10-06-2011 |
| 20110242925 | REDUCTION OF FUSIBLE LINKS AND ASSOCIATED CIRCUITRY ON MEMORY DIES - The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy. | 10-06-2011 |
| 20110242915 | METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS - Control signal oscillation filtering circuits, delay locked loops, clock synchronization methods and devices and systems incorporating the control signal oscillation filtering circuits are described. An oscillation filtering circuit includes a first oscillation filter configured to filter oscillations and a majority filter configured to average filter an output of a phase detector and generate in response thereto control signals to an adjustable delay line. | 10-06-2011 |
| 20110242901 | LIFETIME MARKERS FOR MEMORY DEVICES - The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells. | 10-06-2011 |
| 20110242900 | MEMORY CELL SENSING DEVICES AND METHODS - The present disclosure includes methods, devices, and systems for sensing memory cells. One or more embodiments include providing an output of a first counter to a digital-to-analog converter (DAC). An output of the DAC can correspond to a ramping voltage provided to a control gate of the memory cell. An output of a second counter can be provided to sensing circuitry coupled to a sense line of the memory cell. Conduction of the sense line in response to the ramping voltage can be sensed, and an output value of the second counter can be determined in response to the sensed conduction of the sense line. | 10-06-2011 |
| 20110241205 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 10-06-2011 |
| 20110241041 | LIGHT EMITTING DIODE THERMALLY ENHANCED CAVITY PACKAGE AND METHOD OF MANUFACTURE - Several embodiments of light emitting diode packaging configurations including a substrate with a cavity are disclosed herein. In one embodiment, a cavity is formed on a substrate to contain an LED and phosphor layer. The substrate has a channel separating the substrate into a first portion containing the cavity and a second portion. A filler of encapsulant material or other electrically insulating material is molded in the channel. The first portion can serve as a cathode for the LED and the second portion can serve as the anode. | 10-06-2011 |
| 20110240596 | Methods Using Block Co-Polymer Self-Assembly for Sub-Lithographic Patterning - Block copolymers can be self-assembled and used in methods as described herein for sub-lithographic patterning, for example. The block copolymers can be diblock copolymers, triblock copolymers, multiblock copolymers, or combinations thereof. Such methods can be useful for making devices that include, for example, sub-lithographic conductive lines. | 10-06-2011 |
| 20110239093 | FAULT-TOLERANT NON-VOLATILE INTEGRATED CIRCUIT MEMORY - Apparatus and methods are disclosed, such as those that store data in a plurality of non-volatile integrated circuit memory devices, such as NAND flash, with convolutional encoding. A relatively high code rate for the convolutional code consumes relatively little extra memory space. In one embodiment, the convolutional code is spread over portions of a plurality of memory devices, rather than being concentrated within a page of a particular memory device. In one embodiment, a code rate of m/n is used, and the convolutional code is stored across n memory devices. | 09-29-2011 |
| 20110239061 | SYSTEMS AND METHODS FOR RETRIEVING DATA - Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not. | 09-29-2011 |
| 20110237081 | Methods of Forming Memory; and Methods of Forming Vertical Structures - Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions. | 09-29-2011 |
| 20110237042 | Methods Utilizing Microwave Radiation During Formation Of Semiconductor Constructions - Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation. | 09-29-2011 |
| 20110237029 | CIRCUIT AND METHOD FOR INTERCONNECTING STACKED INTEGRATED CIRCUIT DIES - Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively. | 09-29-2011 |
| 20110236568 | MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME - A magnetic cell structure including a nonmagnetic filament contact, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, an insulative layer between the free and pinned layers, and a nonmagnetic filament contact in the insulative layer which electrically connects the free and pinned layers. The nonmagnetic filament contact is formed from a nonmagnetic source layer, also between the free and pinned layers. The filament contact directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. | 09-29-2011 |
| 20110235455 | VOLTAGE REGULATORS, AMPLIFIERS, MEMORY DEVICES AND METHODS - Circuits, devices and methods are provided, such as an amplifier (e.g., a voltage regulator) that includes a feedback circuit that supplies negative feedback through a feedback path. One such feedback path includes a capacitance coupled in series with a “one-way” isolation circuit through which a feedback signal is coupled. The “one-way” isolation circuit may allow the feedback signal to be coupled from a “downstream” node, such as an output node, to an “upstream” node, such as a node at which an error signal is generated to provide negative feedback. However, the “one-way” isolation circuit may substantially prevent variations in the voltage at the upstream node from being coupled to the capacitance in the isolation circuit. As a result, the voltage at the upstream node may quickly change since charging and discharging of the capacitance responsive to voltage variations at the upstream node may be avoided. | 09-29-2011 |
| 20110235450 | CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD - Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance. | 09-29-2011 |
| 20110235418 | DETERMINING MEMORY PAGE STATUS - The present disclosure includes methods, devices, modules, and systems for operating semiconductor memory. One method embodiment includes determining a status of a page of memory cells without using input/output (I/O) circuitry, and outputting the status through the I/O circuitry. | 09-29-2011 |
| 20110235306 | MULTI-LENS SOLID STATE LIGHTING DEVICES - Solid state lighting (SSL) devices including a plurality of SSL emitters and methods for manufacturing SSL devices are disclosed. Several embodiments of SSL devices in accordance with the technology include a support having a first lead and a second lead, a plurality of individual SSL emitters attached to the support, and a plurality of lenses. Each SSL emitter has a first contact electrically coupled to the first lead of the support and a second contact electrically coupled to the second lead of the support such that the SSL emitters are commonly connected. Each lens has a curved surface and is aligned with a single corresponding SSL emitter. | 09-29-2011 |
| 20110234324 | SYSTEM AND METHOD FOR REDUCING LOCK TIME IN A PHASE-LOCKED LOOP - Increasing loop gain is a common practice for reducing lock time of phase locked loops. Very high loop gains, however, often result in increasing the lock time or causing loop instability. For very high loop gains, delaying the feedback clock signal along the feedback path of a phase locked loop decreases lock time and prevents instability. A delay circuit may be used at any location along the feedback path of the phase locked loop. | 09-29-2011 |
| 20110234257 | OUTPUT DRIVER ROBUST TO DATA DEPENDENT NOISE - Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment. | 09-29-2011 |
| 20110233777 | THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS - A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths. | 09-29-2011 |
