| MICREL, INC Patent applications |
| Patent application number | Title | Published |
|---|
| 20120032658 | Buck-Boost Converter Using Timers for Mode Transition Control - A DC-to-DC, buck-boost voltage converter includes a duty cycle controller configured to generate control signals for a buck driver configured to drive first and second buck switching transistors at a buck duty cycle and to generate control signals for a boost driver configured to drive first and second boost switching transistors at a boost duty cycle. The duty cycle controller includes at least a duty cycle timer and an offset timer where the duty cycle controller applies the duty cycle timer and the offset timer to control transitions between the buck, the buck-boost and the boost operation modes of the voltage converter. | 02-09-2012 |
| 20110228871 | High Bandwidth Programmable Transmission Line Pre-Emphasis Method and Circuit - In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width. | 09-22-2011 |
| 20110228824 | High Bandwidth Dual Programmable Transmission Line Pre-Emphasis Method and Circuit - In one embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and a secondary signal path including a pulse shaping stage incorporating a network and a scaling stage. The pre-emphasis circuit generates an overshoot pulse with variable pulse width. In another embodiment, a transmission line pre-emphasis circuit includes a primary signal path generating a primary differential output current indicative of a digital data stream and one or more secondary signal paths incorporating a network implementing a specific transient response. Each of the secondary signal paths includes a scaling stage and a shaping stage each with programmable bias current. The scaling stage can be configured before or after the shaping amplifier. The pre-emphasis circuit generates an overshoot signal with variable amplitude and/or variable width. | 09-22-2011 |
| 20110228823 | High Bandwidth Programmable Transmission Line Pre-Emphasis Method and Circuit - A transmission line pre-emphasis circuit includes a primary signal path receiving a digital data stream and generating a primary output current indicative of the digital data stream, one or more secondary signal paths each incorporating a network implementing a specific transient response where the one or more secondary signal paths receive the digital data stream and generate secondary output currents representing one or more overshoot signals indicative of the transient response of the respective network. The one or more secondary signal paths have variable gain being programmed through respective DC programming signals. The secondary output currents are summed with the primary output current. The transmission line pre-emphasis circuit further includes an output loading stage coupled to generate from the summed current a pre-emphasized digital output signal indicative of the one or more overshoot signals added to the digital data stream. | 09-22-2011 |
| 20110227675 | High Bandwidth Programmable Transmission Line Equalizer - A transmission line equalizer includes multiple signal paths connected in parallel between an equalizer input signal and an output amplifier where each signal path has a network implementing a specific frequency dependent response and each signal path implements current gain amplification with one or more of the signal paths having a variable gain programmed through a time invariant, DC programming signal. Furthermore, one or more of the signal paths implements linear-to-nonlinear signal transformations and compensating nonlinear-to-linear signal transformations to generate linearized output signals at the one or more signal paths. The equalizer further includes the output amplifier summing output signals from the multiple signal paths to generate an equalized output signal. In operation, the gain of the one or more signal paths is varied to establish the relative proportions of the output signals generated by each signal path and summed at the output amplifier. | 09-22-2011 |
| 20110151594 | METHOD AND SYSTEM FOR CONTROLLED ISOTROPIC ETCHING ON A PLURALITY OF ETCH SYSTEMS - A method for forming identical isotropic etch patterns in an etch system is disclosed. The method comprises providing a wafer paddle, a wafer, a plurality of identical etch systems, utilizing identical etch recipes within each of the plurality of etch systems, providing a fixed temperature stability time FTST for each system so that the heat transfer from the paddle to the wafer is constant, wherein the FTST is the same on each of the plurality of etch systems; and utilizing the plurality of identical etch systems to produce identical etches on each of the wafers based upon the FTST, wherein a five-second preheat step in the etch process is not utilized. | 06-23-2011 |
| 20110084724 | UNIVERSAL PINOUT FOR BOTH RECEIVER AND TRANSCEIVER WITH LOOPBACK - An integrated circuit capable of dual configuration of data flow and operable in a plurality of operational modes is provided. The circuit includes eight corner pins, wherein the eight corner pins comprise a first corner pin and a second corner pin on each side of the circuit in each of four side sets, wherein a first corner pin of one side of the circuit is proximate and adjacent to a second corner pin of an adjacent side counterclockwise from the first corner pin and together constitute a paired corner set, each paired corner set comprising a differential input and a differential output. | 04-14-2011 |
| 20110043172 | Buck-Boost Converter With Smooth Transitions Between Modes - In a buck-boost converter, the method compensates for the boost mode power switch having a minimum on-time when entering the buck-boost mode from the buck mode by immediately decreasing a duty cycle of the buck mode power switch upon entering the buck-boost mode. This prevents the inductor current from being higher at the end of the switching cycle than at the beginning of the cycle, so the output voltage stays regulated without the converter oscillating between the buck mode and the buck-boost mode. The duty cycle of the buck power switch is increased in the buck-boost mode as the input voltage further falls and the boost power switch duty cycle is increased. Upon transitioning into the boost mode, the duty cycle of the boost power switch is immediately reduced to compensate for the buck switching being stopped and the buck power switch having a minimum off-time. | 02-24-2011 |
| 20110024839 | Lateral DMOS Field Effect Transistor with Reduced Threshold Voltage and Self-Aligned Drift Region - A method of forming a lateral DMOS transistor includes performing a low energy implantation using a first dopant type and being applied to the entire device area. The dopants of the low energy implantation are blocked by the conductive gate. The method further includes performing a high energy implantation using a third dopant type and being applied to the entire device area. The dopants of the high energy implantation penetrate the conductive gate and is introduced into the entire device active area including underneath the conductive gate. After annealing, a double-diffused lightly doped drain (DLDD) region is formed from the high and low energy implantations and is used as a drift region of the lateral DMOS transistor. The DLDD region overlaps with the body region at a channel region and interacts with the dopants of the body region to adjust a threshold voltage of the lateral DMOS transistor. | 02-03-2011 |
| 20110024836 | Field Effect Transistor With Trench-Isolated Drain - A MOS transistor includes a body region of a first conductivity type, a conductive gate and a first dielectric layer, a source region of a second conductivity type formed in the body region, a heavily doped source contact diffusion region formed in the source region, a lightly doped drain region of the second conductivity type formed in the body region where the lightly doped drain region is a drift region of the MOS transistor, a heavily doped drain contact diffusion region of the second conductivity type formed in the lightly doped drain region; and an insulating trench formed in the lightly doped drain region adjacent the drain contact diffusion region. The insulating trench blocks a surface current path in the drift region thereby forming vertical current paths in the drift region around the bottom surface of the trench. | 02-03-2011 |
| 20100320992 | Buck-Boost Converter With Sample And Hold Circuit In Current Loop - In an average-current mode control type buck-boost PWM converter, a sample and hold circuit is inserted in the current loop to avoid problems associated with ripple of the average inductor current demand signal. The rippling average inductor current is generated by a differential transconductance amplifier having applied to its inputs an error signal and a signal corresponding to the instantaneous current through the inductor, where the output of the amplifier is filtered. The rippling average inductor current is sampled and held at the beginning of each switching cycle, prior to the average inductor current demand signal being compared to buck and boost sawtooth waveforms. By using the sample and hold circuit, the feedback loops are easier to stabilize, and the converter cannot switch modes during a switching cycle. | 12-23-2010 |
| 20100296519 | Ethernet Physical Layer Repeater - An Ethernet repeater system has a plurality of identical repeaters which add substantially no delay. Each repeater has at least a first port and a second port connected to a medium, and a third port connected to a slave processor or a master processor. The master processor controls all communications on the medium. A receive multiplexer always applies data on the medium to the processor in the event the data is destined for the processor. A first transmit multiplexer has inputs connected to the second port and the processor, and an output connected to the first port. A second transmit multiplexer has inputs connected to the first port and the processor, and an output connected to the second port. The first and second transmit multiplexers act as a bridge between the first and second ports to pass through data without any variable latency since the data does not have to be buffered. | 11-25-2010 |
| 20100253385 | EDGE DETECT RECEIVER CIRCUIT - A digital signal detector detects digital signals by only sensing the rising and falling edges of a received digital signal and latches the logic state between the detected edges. Such edges contain very high frequencies that are much higher than the fundamental frequency of the digital signal train. A small high pass filter filters out at least the DC component and the fundamental frequency of the received digital signal. A filtered edge appears as a spike that goes either positive or negative depending on whether the edge is a rising or falling edge. A memory element, such as comprising an RS flip flop, is triggered by the positive and negative spikes. A positive spike triggers the flip flop to output a logical one, and a negative spike triggers the latch to output a logical zero. In this way, the digital signal is recreated without the original digital signal itself being required to pass through the high pass filter. | 10-07-2010 |
| 20100230774 | Diode Having High Breakdown Voltage and Low on-Resistance - A Schottky or PN diode is formed where a first cathode portion is an N epitaxial layer that is relatively lightly doped. An N+ buried layer is formed beneath the cathode for conducting the cathode current to a cathode contact. A more highly doped N-well is formed, as a second cathode portion, in the epitaxial layer so that the complete cathode comprises the N-well surrounded by the more lightly doped first cathode portion. An anode covers the upper areas of the first and second cathode portions so both portions conduct current when the diode is forward biased. When the diode is reverse biased, the depletion region in the central N-well will be relatively shallow but substantially planar so will have a relatively high breakdown voltage. The weak link for breakdown voltage will be the curved edge of the deeper depletion region in the lightly doped first cathode portion under the outer edges of the anode. Therefore, the N-well lowers the on-resistance without lowering the breakdown voltage. | 09-16-2010 |
| 20100202470 | Dynamic Queue Memory Allocation With Flow Control - A method in an Ethernet controller for allocating memory space in a buffer memory between a transmit queue (TXQ) and a receive queue (RXQ) includes allocating initial memory space in the buffer memory to the RXQ and the TXQ; defining a RXQ high watermark and a RXQ low watermark; receiving an ingress data frame; determining if a memory usage in the RXQ exceeds the RXQ high watermark; if the RXQ high watermark is not exceeded, storing the ingress data frame in the RXQ; if the RXQ high watermark is exceeded, determining if there are unused memory space in the TXQ; if there are no unused memory space in the TXQ, transmitting a pause frame to halt further ingress data frame; if there are unused memory space in the TXQ, allocating unused memory space in the TXQ to the RXQ; and storing the ingress data frame in the RXQ. | 08-12-2010 |
| 20100180249 | Chip-Scale Package Conversion Technique for Dies - A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology. | 07-15-2010 |
| 20100065906 | SYSTEM FOR VERTICAL DMOS WITH SLOTS - A device for providing a high power, low resistance, efficient vertical DMOS device is disclosed. The device comprises providing a semiconductor substrate with a source body structure thereon. The device further comprises a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies. | 03-18-2010 |
| 20100052708 | Tester for RF Devices - For testing an RF device, such as an RF receiver/decoder chip that receives an RF signal via an antenna terminal and outputs a digital code at an output terminal, an inexpensive non-RF programmable tester is used. The programmable tester is a commercially available tester that need only generate and receive non-RF digital and analog signals. The RF signals needed for the testing of the RF device are totally supplied by RF generators on a single printed circuit board, external to the commercial tester housing. The board contains controllable RF generating circuitry whose possible output amplitudes and frequencies need be only those necessary for testing the particular DUT. The frequencies may be changed by switching in different crystal resonators mounted on the board. | 03-04-2010 |
| 20100032753 | MOS Transistor Including Extended NLDD Source-Drain Regions For Improved Ruggedness - A MOS transistor includes a conductive gate insulated from a semiconductor layer by a dielectric layer, first and second lightly-doped diffusion regions formed self-aligned to respective first and second edges of the conductive gate, a first diffusion region formed self-aligned to a first spacer, a second diffusion region formed a first distance away from the edge of a second spacer, a first contact opening and metallization formed above the first diffusion region, and a second contact opening and metallization formed above the second diffusion region. The first lightly-doped diffusion region remains under the first spacer. The second lightly-doped diffusion region remains under the second spacer and extends over the first distance to the second diffusion region. The distance between the first edge of the conductive gate to the first contact opening is the same as the distance between the second edge of the conductive gate to the second contact opening. | 02-11-2010 |
| 20100020809 | True Ring Networks Using Tag VLAN Filtering - A method in a network device configured in a true ring network where the network device has a first port and a second port connected to the true ring network and a third port connected to a processor including: connecting the network device to transmit data packets in a single direction around the true ring network including an ingress port and an egress port; enabling ingress tag VLAN filtering on the ingress port only; configuring a VLAN table in the network device to terminate an incoming data packet when a VID tag (VLAN identifier tag) of the incoming data packet matches the local VID tag of the network device; and configuring the VLAN table in the network device to accept the incoming data packet when the VID tag of the incoming data packet does not match the local VID tag of the network device. | 01-28-2010 |
| 20100020798 | True Ring Networks With Gateway Connections Using MAC Source Address Filtering - A method in a network device implements source address filtering, including gateway address filtering, to enable network devices to be configured in a true Ethernet ring network. By implementing source address filtering or source address filtering with gateway address filtering, a true ring network can be formed using Ethernet protocols where all the links between the network devices in the ring are active paths while avoiding data packets being switched endlessly around the ring. In one embodiment, a data packet in the true ring network is terminated when the source address of the data packet matches the local address of the network device. In another embodiment, a data packet in the true ring network is terminated when the source address of the data packet matches the address of the gateway switch connected to the network device. | 01-28-2010 |
| 20100011140 | Ethernet Controller Using Same Host Bus Timing for All Data Object Access - An Ethernet controller has a host interface for coupling to a host processor and a physical layer transceiver for coupling to a data network and includes multiple data objects having different access times where the data objects communicate with the host interface over an internal data bus. The Ethernet controller includes a data object interface module coupled between the host interface and the internal data bus where the data object interface module has a first access time for handling data requests for the data objects received on the host interface from the host processor, and a control logic circuit coupled to control the operation of the data object interface module. Data requests from the host processor for accessing data stored in the multiple data objects are carried out through the data object interface module using the first access time, regardless of the different access times of the multiple data objects. | 01-14-2010 |
| 20100008378 | Ethernet Controller Implementing a Performance and Responsiveness Driven Interrupt Scheme - A method of generating frame receive interrupts in an Ethernet controller including receiving incoming data frames and storing data frames into a receive queue, monitoring the number of received data frames, and when the number of received data frames exceeds a first threshold, generating a frame receive interrupt. In another embodiment, the method further includes monitoring the amount of received data stored in the receive queue and generating a frame receive interrupt when the first threshold is exceeded and when the amount of received data stored in the receive queue exceeds a second threshold. In yet another embodiment, the method further includes monitoring the time duration of the data frames stored in the receive queue, and generating a frame receive interrupt when the number of received data frames exceeds the first threshold or when the time duration of the data frames stored in the receive queue exceeds a third threshold. | 01-14-2010 |
| 20100007363 | SYSTEM AND METHOD FOR DETERMINING IN-LINE INTERFACIAL OXIDE CONTACT RESISTANCE - The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for measuring in-line contact resistance in relation to oxide formations. The present invention, in one or more implementations, include an in-line method of determining contact resistance across a semiconductor wafer and determining the contact resistance value and the number of monolayers of the wafer. | 01-14-2010 |
| 20100007316 | Current Sensing In a Buck-Boost Switching Regulator Using Integrally Embedded PMOS Devices - A current sense device for a power transistor is described. The power transistor is formed in a cellular structure including a cellular array of transistor cells. The current sense device includes multiple transistor cells in the cellular array of transistor cells of the power transistor being used as sense transistor cells. The sense transistor cells are evenly distributed throughout the cellular array where the source terminal of each sense transistor cell is electrically connected to a first node through a metal line in the first metal layer and through a metal line in the second metal layer where the metal lines are electrically isolated from the metal lines connecting the transistor cells of the power transistor. The sense transistor cells measure a small portion of the current flowing through the power transistor based on the size ratio of the current sense device and the power transistor. | 01-14-2010 |
| 20090302378 | METHOD AND SYSTEM FOR VERTICAL DMOS WITH SLOTS - A method for providing a high power, low resistance, high efficient vertical DMOS device is disclosed. The method comprises providing a semiconductor substrate with a source body structure thereon. The method further comprises providing a plurality of slots in the source/body structure and providing a metal within the plurality of slots to form a plurality of structures. A slotted PowerFET array is disclosed. This slotted approach results in a dense PowerFET, a low Ron due to the slotted design, an oxide isolated process without any due extra steps other than the slots, lower capacitance, lower leakage, smaller die, improved heat transfer, improved electro-migration, lower ground resistance, less cross talk, drops the isolation diffusion and the sinker diffusion, mostly low temperature processing and provides double metal with single metal processing. Also disclosed is a method for integrating this vertical DMOS with CMOS, bipolar and BCD to provide an optimized small, efficient die using the buried power buss approach and these technologies. | 12-10-2009 |
| 20090284289 | METHOD OF IMPLEMENTING POWER-ON-RESET IN POWER SWITCHES - A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period,; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily. | 11-19-2009 |
| 20090284235 | Adaptive Compensation Scheme for LC Circuits In Feedback Loops - A method for providing adaptive compensation for an electrical circuit where the electrical circuit includes an inductor-capacitor network connected in a feedback loop being compensated by a first compensation capacitance value and a second compensation capacitance value defining the frequency locations of two compensation zeros includes: measuring the inductance value of the inductor; when the inductance value is greater than a first threshold value, increasing the first and second compensation capacitance values so that the frequency locations of the two compensation zeros are adjusted for compensating the poles introduced by the first inductor and the first capacitor; and when the inductance value is less than the first threshold value, decreasing the first and second compensation capacitance values so that the frequency locations of the two compensation zeros are adjusted for compensating the poles introduced by the first inductor and the first capacitor. | 11-19-2009 |
| 20090283843 | NMOS Transistor Including Extended NLDD-Drain For Improved Ruggedness - A MOS transistor includes a conductive gate insulated from a semiconductor layer by a first dielectric layer, lightly-doped source/drain regions being formed self-aligned to respective first and second edges of the conductive gate, a source region being formed self-aligned to a first spacer, a drain region being formed a first distance away from the edge of a second spacer, a source contact opening and source metallization formed above the source region, and a drain contact opening and drain metallization formed above the drain region. The lightly-doped source region remains under the first spacer while the lightly-doped drain region remains under the second spacer and extends over the first distance to the drain region. The distance between the first edge of the conductive gate to the source contact opening is the same as the distance between the second edge of the conductive gate to the drain contact opening. | 11-19-2009 |
| 20090273290 | Boost LED Driver Not Using Output Capacitor and Blocking Diode - An LED driver is disclosed that boosts an input voltage to drive any number of LEDs in series. The driver includes a switch-mode current regulator that supplies regulated current pulses to the LEDs. No high voltage output capacitor is used to smooth the current pulses, so the LEDs are turned on any off at the switching frequency. Also, no blocking diode between the switching transistor and the LEDs is used. The cathode of the “bottom” LED in the string is connected to ground via a current sense resistor. In parallel with the sense resistor is connected an RC filter using a small, low voltage filter capacitor. The RC filter provides a substantially smooth feedback voltage for the current regulator to control the duty cycle of the switching transistor so that the feedback voltage matches a reference voltage. | 11-05-2009 |
| 20090251071 | Driving Multiple Parallel LEDs with Reduced Power Supply Ripple - An LED driver is disclosed that drives LEDs connected in parallel. Instead of applying current to all the parallel-connected LEDs at the same time, under control of a common PWM brightness control signal, the application of current to each parallel path is staggered by using staggered brightness control signals. The turning on of the LEDs in the different parallel paths will have the same duty cycle but will be out of phase. This reduces ripple in the power supply by reducing the magnitude of the instantaneous current sink. In one embodiment, a shift register contains a binary representation of the PWM duty cycle, and a clock shifts the bits along the shift register. The PWM brightness control signals for each parallel path of LEDs are tapped from different positions along the shift register so that the PWM brightness control signals are identical but staggered. | 10-08-2009 |
| 20090245120 | Ethernet Physical Layer Transceiver with Auto-Ranging Function - A method in an Ethernet physical transceiver device for selecting a transmission speed includes resetting a first register and a count value, establishing a link with a remote network device at a first transmission speed, incrementing the first register to a first value, monitoring the link by counting the number of detected false carrier events in the incoming transmission as the count value, and at the expiration of a first time period, comparing the count value of false carrier events to a predetermined threshold. The method continues with reducing the first transmission speed when the count value exceeds the predetermined threshold, maintaining the first transmission speed when the count value is less than the predetermined threshold, and when the first register has a first value, incrementing the first register to a second value and repeating the steps of monitoring the link to reducing the first transmission speed. | 10-01-2009 |
| 20090230883 | Stacked LED Controllers - A driver for driving a plurality of light emitting diodes (LEDs) is formed of a plurality of LED controllers connected in series between a power supply and a reference voltage. Each controller drives one or more LEDs directly connected to it. Each controller has a voltage input terminal coupled to an output terminal of an adjacent upstream controller, and an output terminal coupled to the voltage input terminal of an adjacent downstream controller. Each controller has a normally-on bypass switch coupled between its voltage input terminal and the voltage input terminal of the adjacent upstream controller. The bypass switch completely bypasses the adjacent upstream controller when the adjacent downstream controller detects that its input voltage is below a threshold insufficient to drive the LED in the adjacent upstream controller. The bypass switch is turned off if the voltage is above the threshold. | 09-17-2009 |
| 20090210210 | METHOD OF ACCURATE PREDICTION OF ELECTROSTATIC DISCHARGE (ESD) PERFORMANCE IN MULTI-VOLTAGE ENVIRONMENT - The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to predictive, pre-fabrication methodologies for determining inefficiencies in an integrated circuit (IC) design. The present invention, in one or more implementations, provides an effective pre-production methodology for predicting the efficiency and behavior of a designed ESD protective circuit and testing the ESD protective circuit with a simulated IC. The method of the present invention yields predictive results that have been comparatively tested. | 08-20-2009 |
| 20090206919 | NO-TRIM LOW-DROPOUT (LDO) AND SWITCH-MODE VOLTAGE REGULATOR CIRCUIT AND TECHNIQUE - An optimized output voltage circuit and technique obtainable without trimming is set forth. A voltage reference circuit and method devoid of trim resistors comprising a high gain amplifier, a plurality of bandgap resistors, and at least a plurality of bipolar devices interconnected across circuitry in a predetermined configuration having emitter areas greater than traditional emitter areas of traditional bipolar devices is set forth. | 08-20-2009 |
| 20090190621 | Laser Turn-On Accelerator Independent of Bias Control Loop Bandwidth - An accelerator circuit is incorporated in a laser diode system for accelerating the turn-on operation of the laser diode independent of the control loop bandwidth of the laser diode system. The accelerator circuit provides a boost current to a compensation capacitor upon laser turn-on which compensation capacitor operates to establish the control loop bandwidth of the laser diode system. The boost current enables the control loop to increase the bias current to the laser diode quickly. When the laser diode reaches the desired operating point, the boost current is terminated and the control loop of the laser diode system resumes normal control of the bias current. In one embodiment, the accelerator circuit includes a timer circuit controlling a current source to implement open loop turn-on control. In another embodiment, the accelerator circuit includes a comparator circuit working in conjunction with an one-shot logic circuit for providing close loop control. | 07-30-2009 |
| 20090189539 | Controlling Current Through Serial LEDs Using a Low Voltage Transistor When Using a High Voltage Driver - Various circuits are described herein where a series transistor used to control current through a string of LEDs, driven by a high voltage, is not subjected to the high voltage when the transistor is turned off pursuant to a PWM signal. To avoid the transistor experiencing the high voltage, the HV regulator is disabled shortly before the transistor is turned off and is enabled shortly after the transistor has turned back on. Control circuits for controlling the regulator and transistor include delay circuits and/or voltage sensing circuits to ensure that the transistor is always on prior to the voltage regulator being enabled pursuant to the incoming PWM signal, and the voltage regulator is always disabled when the first transistor is off pursuant to the incoming PWM signal. | 07-30-2009 |
| 20090184655 | POWER MANAGEMENT SYSTEM FOR LIGHT EMITTING DIODES - A power management system comprising: providing a one pin driver circuit; sourcing a managed current from the one pin driver circuit; and illuminating a light emitting diode by the managed current including reducing the managed current when the light emitting diode is not coupled. | 07-23-2009 |
| 20090176181 | SYSTEM AND METHOD OF IMPROVED PRESSURE CONTROL IN HORIZONTAL DIFFUSION FURNACE SCAVENGER SYSTEM FOR CONTROLLING SILICON OXIDE GROWTH - The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for controlling oxide formation using pressure. The present invention, in one or more implementations, includes a pressure stabilization system to dynamically adjust scavenger pressure in a furnace during wafer fabrication in relation to a pressure formation range, value, or one or more pressure indicators in a wafer fabrication process. | 07-09-2009 |
| 20090159561 | INTEGRATED DEVICE TECHNOLOGY USING A BURIED POWER BUSS FOR MAJOR DEVICE AND CIRCUIT ADVANTAGES - A method for providing an improved integrated circuit device is disclosed. The method comprises the steps of providing active and passive areas in the substrate, providing a plurality of slots in the substrate after providing the active and passive areas, and oxidizing the plurality of slots. The method further comprises providing metal in each of the plurality of slots, providing a dielectric coating over the slots, and providing etched contacts in select areas remote from the location of the slots. Additionally, the method provides an additional layer of metal that interconnects the contacts and the buried metal in select areas where contacts were etched, resulting in metal of three levels; and provides one level of the metal is surface and two levels of the metal that comprise a buried power buss (BPB). | 06-25-2009 |
| 20090147425 | Overcurrent Protection Circuit When Setting Current Using a Package Control Pin - An overcurrent protection circuit for a current setting circuit is disclosed herein that prevents a user-selectable current from exceeding a current limit when an incorrect current selecting component (or current selecting circuit) is connected to an external control pin of a package by the user, or when the control pin is inadvertently grounded. The protection circuit senses a current (A | 06-11-2009 |
| 20090140579 | Relay Switch Including an Energy Detection Circuit - A semiconductor relay switch having two data ports receiving incoming signals and a power supply terminal receiving a power supply voltage is responsive to a power supply voltage level and an energy level of the incoming signals to open and close its conduction paths. The relay switch is open when a valid power supply level is detected and when there is no supply power on the power supply terminal but a high energy level is detected in the incoming signals. The relay switch is closed to allow conduction between the two data ports only when there is no power supply voltage on the power supply terminal and an energy level below a predetermined threshold is detected in the incoming signals. In one embodiment, the semiconductor relay switch includes a main conduction switch circuit, an energy detect circuit and a control signal generator. | 06-04-2009 |
| 20090138742 | Automatic Clock and Data Alignment - A circuit is described for automatically adjusting a phase of an input register load clock to be synchronized with transitions of data bits forming an n-bit word. The circuit detects the first transition of a data bit in the n-bit word. The circuit then time-shifts the input clock, to generate a shifted clock, so that a triggering edge of the shifted clock occurs sometime after generation of the transition detect signal, such as in the middle third of a data cycle. Shifting the input clock may be performed by multiplying the input clock to generate a plurality of sub-clock cycles and selecting one of the sub-clock cycles as the start of the shifted clock cycle. The parallel data are applied to inputs of input registers clocked using the shifted clock as the load clock. Thus, the load clock occurs at an optimum time near the middle of a data cycle. | 05-28-2009 |
| 20090130813 | Method and System to Provide a Polysilicon Capacitor with Improved Oxide Integrity - A system and method in accordance with the present invention allows for an improved oxide integrity of a polysilicon capacitor compared to capacitors manufactured using conventional semiconductor processing techniques. This is accomplished by moving the capacitor implant step to a time after the deposition of the polysilicon. As an additional benefit, a separate capacitor oxide growth does not need to be performed. | 05-21-2009 |
| 20090128110 | Compact Frequency Compensation Circuit And Method For A Switching Regulator Using External Zero - A compensation circuit in a monolithic switching regulator controller being incorporated in a closed loop feedback system of a switching regulator includes error amplifier having an output terminal with an output impedance and a degeneration resistance terminal coupled to a first terminal of the switching regulator controller. The compensation circuit includes a first resistor and a first capacitor connected in series between the output terminal of the error amplifier and a ground potential. In operation, the first capacitor and the output impedance of the error amplifier operate to introduce a pole and the first resistor and the first capacitor operate to introduce a first zero in the closed loop feedback system. When a second capacitor is coupled to the first terminal of the switching regulator controller, a second zero is introduced in the closed loop feedback system. The second capacitor is an off-chip capacitor formed external to the monolithic switching regulator controller. | 05-21-2009 |
| 20090125140 | SYSTEM AND METHOD FOR MATCHING SILICON OXIDE THICKNESS BETWEEN SIMILAR PROCESS TOOLS - The present invention is one or more implementations is a method of fabricating a semiconductor for improved oxide thickness control, defining a process tool, determining and evaluating performance variables, determining a performance impact factor and thereafter modifying control of the process tool in the fabrication process to operate in direct relation to the determined results of the present invention. The present invention sets forth definitive advantages in reducing engineering time, improving process controls and improving cycle-times. | 05-14-2009 |
| 20090093116 | Method for forming Zener Zap Diodes and Ohmic Contacts in the Same Integrated Circuit - A method for forming an ohmic contact and a zener zap diode in an integrated circuit includes forming a first contact opening in the insulating layer over a first diffusion region to expose the semiconductor substrate; forming a barrier metal layer on the insulating layer and in the first contact opening; forming a second contact opening in the barrier metal layer over a second diffusion region and the insulating layer to expose the semiconductor substrate; forming a third contact opening in the barrier metal layer and the insulating layer over a third diffusion region to expose the semiconductor substrate; forming an aluminum layer on the barrier metal layer and the insulating layer and in the first, second and third contact openings; and patterning the aluminum layer to form the ohmic contact over the first diffusion region and the zener zap diode over the second and third diffusion regions. | 04-09-2009 |
| 20090085643 | Power Distribution Current Limiting Switch Including A Current Limit Blanking Period Providing A Burst of Current - A method for operating a current limit power switch for supplying power to a load include activating the power switch to start supplying power to the load; limiting the current drawn by the power switch to a first current limit for a first, fixed duration; after the first, fixed duration, limiting the current drawn by the power switch to a second current limit for a second duration where the second current limit is less than the first current limit; and after the second duration, limiting the current drawn by the power switch to a third current limit where the third current limit is less than the second current limit. | 04-02-2009 |
| 20090085586 | DETECTION OF PRESENCE OR ABSENCE OF AC MAINTAIN POWER SIGNATURE IN POWER-OVER-ETHERNET SYSTEM - An AC maintain power signature detection circuit in a power sourcing equipment (PSE) for a Power over Ethernet system injects an AC test signal onto a power port of the PSE. The AC test signal is driven onto a first power terminal of the power port through a sense resistor. The voltages across the sense resistor are measured and scaled by first and second resistor dividers having different resistor ratios. The voltage and the scaled voltage at the first power terminal side of the sense resistor have a peak voltage being proportional to the load impedance of the load coupled to the power port. The comparator compares the scaled voltages measured across the sense resistor and generates the output signal indicative of the load impedance at the power port. | 04-02-2009 |
| 20090059948 | Low Current Method For Detecting Presence of Ethernet Signals - A signal detection circuit for an Ethernet physical layer transceiver (PHY) device includes a first capacitor AC coupling a signal on the first receive terminal of the Ethernet PHY device to a first node; a second capacitor AC coupling a signal on the second receive terminal to a second node; re-biasing resistors for re-biasing the AC-coupled signals on the first and second nodes; first and second gain stages for amplifying the AC coupled signals; and a peak detect circuit. The peak detect circuit includes first and second diodes receiving the amplified signals from the gain stages to charge a peak detect capacitor. The signal detection circuit includes a comparator for comparing the voltage on the peak detect capacitor to a reference voltage and providing an output signal being indicative of the presence or absence of a signal on the first and second receive terminals of the Ethernet PHY device. | 03-05-2009 |
| 20090055672 | Power Budget Management In Power Over Ethernet Systems - A power budget monitoring circuit in a multi-port PSE includes a differential amplifier and a transistor for setting a reference voltage across a first resistor to establish a reference current, multiple current mirror output devices each associated with a power port of the PSE, a second resistor and a comparator. Each current mirror output device provides an output current indicative of the power demanded by the associated power port where the output currents are summed at a second node into a monitor current. The second resistor has a resistance value proportional to a maximum power budget of the PSE and receives the monitor current. A monitor voltage develops across the second resistor indicative of the total power demanded by the power ports. The comparator compares the monitor voltage to the reference voltage and provides a comparator output signal indicating whether the maximum power budget of the PSE has been exceeded. | 02-26-2009 |
| 20090033243 | LED Controller IC Using Only One Pin to Dim and Set a Maximum LED Current - An LED driver IC is described that uses a single pin to both set the maximum current through one or more driven LEDs and variably control the brightness of the LEDs. A single resistor is connected to the control pin of the IC, where the value of the resistor sets the maximum current through the LEDs. A PWM source, outputting a pulse train at a particular duty cycle, is connected to the other end of the resistor, where the duty cycle controls the LED brightness level. When the PWM signal is low (e.g. ground), a sample and hold circuit connects the output of a feedback control voltage to an Imax current source to set a maximum current based on the external resistor value. An inverse of the duty cycle of the PWM controller controls a current Idim that is subtracted from the maximum current Imax set by the resistor. This difference current is used to control drivers for the LEDs. | 02-05-2009 |
| 20090032850 | N-channel MOS Transistor Fabricated Using A Reduced Cost CMOS Process - An NMOS transistor includes a semiconductor substrate of a first conductivity type, first and second well regions of a second conductivity type formed spaced apart in the substrate, a conductive gate formed over the region between the spaced apart first and second well regions where the region of the substrate between the spaced apart first and second well regions forms the channel region, dielectric spacers formed on the sidewalls of the conductive gate, first and second heavily doped source and drain regions of the second conductivity type formed in the semiconductor substrate and being self-aligned to the edges of the dielectric spacers. The first and second well regions extend from the respective heavily doped regions through an area under the spacers to the third well region. The first and second well regions bridge the source and drain regions to the channel region of the transistor formed by the third well. | 02-05-2009 |
| 20090026578 | Vertical NPN Transistor Fabricated in a CMOS Process With Improved Electrical Characteristics - A vertical NPN bipolar transistor includes a P-type semiconductor structure, an N-well as the collector, a P-Base region in the N-well and an N-type region as the emitter. The transistor further includes P-type region formed in the P-Base region and underneath the field oxide layer where the P-type region has a doping concentration higher than the P-base region. The P-type region functions to inhibit the lateral parasitic bipolar action so that the transistor action is confined to the intrinsic base region vertically underneath the emitter. In one embodiment, the P-type region is a boron field doping region. The boron field doping region can be the same field doping region used to form channel stops for NMOS transistors in a CMOS fabrication process. | 01-29-2009 |
| 20090021310 | SYSTEM AND METHOD FOR PHASE-LOCKED LOOP (PLL) FOR HIGH-SPEED MEMORY INTERFACE (HSMI) - A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures. | 01-22-2009 |
| 20090021306 | INTEGRATED CIRCUIT SYSTEM FOR LINE REGULATION OF AN AMPLIFIER - An integrated circuit system is provided including forming a differential pair; reducing a mismatch in the differential pair by: coupling an amplifier to the differential pair; and coupling a local feedback network to the amplifier in which referencing the local feedback network includes coupling a first voltage; and driving an output transistor by the amplifier. | 01-22-2009 |
| 20090016392 | Laser Driver Automatic Power Control Circuit Using Non-Linear Impedance Circuit - A laser driver circuit includes a laser APC circuit receiving a monitor current indicative of the average optical output power of a laser diode and providing a bias adjust signal for adjusting a bias current for the laser diode. The laser APC circuit includes a first non-linear impedance circuit receiving the monitor current and generating a first voltage using a first non-linear current-to-voltage transfer function, a second non-linear impedance circuit receiving a reference current and generating a second voltage and being implemented using the same or a scaled version of the first non-linear current-to-voltage transfer function, and a comparator for comparing the first voltage with the second voltage and providing the bias adjust signal indicative of the difference between the first and second voltages. The first non-linear current-to-voltage transfer function has difference resistance portions for increasing the dynamic range of the current-to-voltage conversion. | 01-15-2009 |
| 20080310861 | PON Burst Mode Receiver with Fast Decision Threshold Setting - A receiver converts an analog signal, derived from light pulses in a GPON fiber optic system, to clean digital electrical signals. A photodetector and transimpedance amplifier (TIA) convert the light pulses to analog electrical signals. A reset signal generated by a media access controller (MAC) in the GPON system signifies the start of a new burst of data. The receiver has a switchable low pass filter that establishes the threshold voltage for determining whether the analog signal is a logical 1 or a logical 0. At the very start of a new burst, the low pass filter has a fast time constant to quickly establish the threshold voltage for the burst. At a later time during the burst, the low pass filter is switched to have a slow time constant to create a relatively stable threshold voltage. | 12-18-2008 |
| 20080303097 | Power FET With Low On-Resistance Using Merged Metal Layers - In one embodiment, relatively thin but wide metal bus strips overlying a high power FET are formed to conduct current to the source and drain narrow metal strips. A passivation layer is formed over the surface of the FET, and the passivation layer is etched to expose almost the entire top surface of the bus strips. A copper seed layer is then formed over the surface of the wafer, and a mask is formed to expose only the seed layer over the bus strips. The seed layer over the bus strips is then copper or gold electroplated to deposit a very thick metal layer, which effectively merges with the underlaying metal layer, to reduce on-resistance. The plating metal does not need to be passivated due to its thickness and wide line/space. Other techniques may also be used for depositing a thick metal over the exposed bus strips. | 12-11-2008 |
| 20080297250 | INTEGRATED CIRCUIT SYSTEM FOR CONTROLLING AMPLIFIER GAIN - An integrated circuit system comprising: forming a differential amplifier including: forming a first transistor, coupling a second transistor to the first transistor in a high gain configuration, and coupling a third transistor, having a low gain configuration, in parallel with the second transistor; and adjusting a gain of the differential amplifier by adjusting a ratio of the size of the second transistor to the size of the first transistor. | 12-04-2008 |
| 20080297227 | INTEGRATED CIRCUIT SYSTEM FOR ANALOG SWITCHING - An integrated circuit system comprising: forming an analog switch including: providing a current source for driving the analog switch, coupling a first source follower to the current source for forming a first input to the analog switch, coupling a second source follower to the current source for forming a second input to the analog switch, and coupling a switch to the first source follower and the second source follower for selecting the first input, the second input, or a combination thereof; and selecting a voltage output signal from the first source follower, the second source follower, or a combination thereof including isolating the first input from the second input. | 12-04-2008 |
| 20080290849 | VOLTAGE REGULATION SYSTEM - A voltage regulation system is provided including detecting a feedback voltage less than a reference voltage; asserting a current source gate output by the feedback voltage less than the reference voltage; activating a gated current source by the current source gate output; and waiting a delay interval before negating the current source gate output for turning off the gated current source. | 11-27-2008 |
| 20080290464 | NPN DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of forming a semiconductor device is disclosed. The method includes providing a floor for a semiconductor device by utilizing a CMOS process. The method further includes providing a BiCMOS-like process on top of the floor to further fabricate the semiconductor device, wherein the BiCMOS-like process and the CMOS process provides the semiconductor device. | 11-27-2008 |
| 20080252367 | Demodulator with Multiple Operating Modes for Amplitude Shift Keyed Signals - A demodulator for demodulating an amplified shift keyed (ASK) signal includes an envelope detector generating an envelope signal, a low-pass filter generating a filtered envelope signal, a switch coupled to disengage the low-pass filter in response to a first control signal, a comparator with hysteresis comparing the envelope signal and the filtered envelope signal. In operation, the switch is open or close in response to the first control signal to cause the demodulator to operate in one of multiple operation modes. In one operation mode, the demodulator uses a small capacitor to form a low-pass filter having a cut-off frequency equal to or greater than the bit-rate of the ASK signal and the demodulator receives an ASK signal having any coding pattern, including ASK signals having unequal number of 1's and 0's. | 10-16-2008 |
| 20080248765 | Superheterodyne Receiver with Switchable Local Oscillator Frequency and Reconfigurable IF Filter Characteristics - An integrated circuit RF receiver processes multiple RF frequencies without internally changing the local oscillator to receive the multiple signals. No front-end tuner is used. In one embodiment, multiple crystals are connected to pins of the IC. A switch within the IC, controlled by a switch signal, selects one of the crystals as a reference frequency, depending on the frequency of the RF signal desired to be received. The selected reference frequency is applied to an RF synthesizer (a local oscillator) to set the output frequency of the RF synthesizer. The local oscillator signal is then mixed with the incoming RF signal to generate sum and difference signals that need to be filtered by an IF filter. The switch signal also reconfigures the IF filter to change its center frequency and filter bandwidth, based on the requirements of the RF signal data format. | 10-09-2008 |
