| Mentor Graphics Corporation Patent applications |
| Patent application number | Title | Published |
|---|
| 20120136645 | Managing Communication Bandwidth in Co-Verification of Circuit Designs - Related communication signals between a simulator and an emulator are organized into logical channels. The signals in each channel are then be transmitted only as needed, reducing the use of the communication pathways between the simulator and the emulator. Further, the circuit components that will receive the communication signals to be shared on a channel are be physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to receive the signals sent by the simulator. Similarly, emulator components that send communication signals to be shared on a channel are physically located close together within the emulator, thereby reducing the time required to select and enable components of the emulator to send these signals to the simulator. | 05-31-2012 |
| 20110307844 | Model-Based Fill - Various aspects of this disclosure relate to increasing pattern density in a circuit layout design of a circuit layer so as to control the thickness of material in a manufactured integrated circuit. For example, a layer in circuit design may be divided into separate areas, and a target thickness range may be established for all of the tiles in the integrated circuit design. Each area may be analyzed to determine if it has a sufficient pattern density for a thickness estimation model to accurately estimate its expected material thickness upon manufacture. Each tile may be analyzed to determine if the expected thickness for that tile is within the target thickness range. | 12-15-2011 |
| 20110252385 | SELECTIVE SHIELDING FOR MULTIPLE EXPOSURE MASKS - A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system. | 10-13-2011 |
| 20110246953 | SELECTIVE SHIELDING FOR MULTIPLE EXPOSURE MASKS - A system for preparing mask data to create a desired layout pattern on a wafer with a multiple exposure photolithographic printing system. In one embodiment, boundaries of features are expanded to create shields for those features, or portions thereof, that are not oriented in a direction that are printed with greater fidelity by an illumination pattern used in the multiple exposure printing system. | 10-06-2011 |
| 20110191643 | Detection And Diagnosis Of Scan Cell Internal Defects - A diagnosis technique to improve scan cell internal defect diagnostic resolution using scan cell internal fault models. | 08-04-2011 |
| 20110179326 | The Performance Of Signature-Based Diagnosis For Logic BIST - Techniques are disclosed for reducing the set of initial candidates in signature based diagnosis methodology. These techniques are based on a unique way of making optimum use of information from logic back-cone tracing along with equations that describe the test response compactor. | 07-21-2011 |
| 20110161066 | DELTA RETIMING IN LOGIC SIMULATION - Aspects of the present invention are directed to improving the speed of event-driven simulation by manipulating delta delays in a system model to reduce delta cycle executions. The manipulation is performed in a manner that preserves delta cycle accurate timing on selected signals of the system, which may be of interest to a designer. Methods and systems are provided for identifying the signals of interest, and for determining portions of the design that may have delta delays retimed. Preserving the timing on the signals of interest ensures that race conditions and glitches present in the design on the signals of interest are still viewable by the designer. To reduce simulation time, delta delays may be moved from high activity signals to low activity signals, the total number of delta delays may be reduced, or a number of processes executed may be reduced. | 06-30-2011 |
| 20110138346 | MEASURE OF ANALYSIS PERFORMED IN PROPERTY CHECKING - The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N. | 06-09-2011 |
| 20110119643 | SUM OF COHERENT SYSTEMS (SOCS) APPROXIMATION BASED ON OBJECT INFORMATION - A method for determining kernels in a sum of coherent systems (SOCS) approximation is provided. Information for an object to be simulated in a manufacturing process is determined. For example, information based on geometries that are included in a layout or mask is determined. A set of kernels from a transmission cross coefficient (TCC) matrix are also determined. The set of kernels may be weighted by importance values in an order of importance. The kernels may then be re-ordered based on the information for the object. These kernels are then re-ordered in the SOCS series to reflect their order of importance. The SOCS series of kernels is then truncated at the number of kernels desired. Accordingly, by re-ordering the kernels that may be more relevant to the object to include higher weights, when the truncation occurs, the kernels that are most relevant may be included in the SOCS approximation. | 05-19-2011 |
| 20110072401 | Model-Based Fill - Various aspects of this disclosure relate to increasing pattern density in a circuit layout design of a circuit layer so as to control the thickness of material in a manufactured integrated circuit. For example, a layer in circuit design may be divided into separate areas, and a target thickness range may be established for all of the tiles in the integrated circuit design. Each area may be analyzed to determine if it has a sufficient pattern density for a thickness estimation model to accurately estimate its expected material thickness upon manufacture. Each tile may be analyzed to determine if the expected thickness for that tile is within the target thickness range. | 03-24-2011 |
| 20100313058 | System and Method of Clocking an IP Core During a Debugging Operation - According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source. | 12-09-2010 |
| 20100199240 | Parallel Electronic Design Automation: Shared Simultaneous Editing - A method to simultaneously allow multiple users to edit in shared areas of a master design includes displaying the master design, allowing a first user to edit in a shared area of the design, while simultaneously allowing a second user to edit in a shared area of the design while preserving the integrity of the design. | 08-05-2010 |
| 20100162192 | Logic Injection - A technique for reducing a circuit listing. According to examples of the technique, at least a portion of a circuit listing is analyzed to identify occurrences of a circuit structure made up of a plurality of circuit components. For each identified occurrence of the defined circuit structure, an injection data object is created corresponding to the plurality of components, and the injection data object is substituted into the portion of the circuit listing in place of the plurality of components. For each occurrence of the defined structure, one or more properties of the occurrence of the defined structure may be determined and contained by the corresponding injection data object. | 06-24-2010 |
| 20100141297 | Configuration of Reconfigurable Interconnect Portions - Configuring reconfigurable interconnect resources employing a switch matrix and configuration bit look-up table are disclosed. Reconfigurable interconnect resources include multiplexors to decrease the number of bits needed to load a configuration. Distributed processing resources configure a selected reconfigurable interconnect resource, interconnecting each input of the reconfigurable interconnect resource with a particular output of the reconfigurable interconnect resource using configuration bits scalably extracted from a row of configuration bits of a look-up table. Use of a configuration bit look-up table allows for compression of the bits needed to load the configuration for a reconfigurable interconnect resource. | 06-10-2010 |
| 20100057426 | Logic Design Modeling and Interconnection - A dynamic reconfigurable interconnect network architecture in a logic simulation system that interconnects a plurality of simulation engines together, providing a high degree of interconnectivity in an efficient manner. The logic simulation system may create and manage linkable sub-programs for execution by a simulation engine. The logic simulation system may schedule various tasks in a design to be simulated, including horizontal and vertical partitioning of the design and determination of an order in which events such as clock edges and asynchronous signals are to be implemented by a logic simulation system. | 03-04-2010 |
| 20090276749 | GATE MODELING FOR SEMICONDUCTOR FABRICATION PROCESS EFFECTS - In one embodiment, a method for determining a contour simplification of an object for a simulation is provided. An object in a layout of a transistor design to be created with the photolithographic process is determined. The object includes a width and a length in the layout. A contour simulation is performed to determine a generated contour object. The contour simulation simulates parametric variation factors that may occur in the photolithographic process. An adjusted width and adjusted length of the object is then determined based on the generated contour object. The adjusted width and the adjusted length are usable to determine a parametric model for simulation of the object. For example, a layout versus schematic (LVS) tool may back-annotate the layout. Then, a SPICE simulation may use the output of the LVS tool to verify the electrical behavior of the transistor using the adjusted width and adjusted length. | 11-05-2009 |
| 20090235209 | Manufacturability - Techniques are disclosed for modifying an existing microdevice design to improve its manufacturability. With these techniques, a designer receives manufacturing criteria associated with data in a design. The associated design data then is identified and provided to the microdevice designer, who may choose to modify the design based upon the manufacturing criteria. In this manner, the designer can directly incorporate manufacturing criteria from the foundry in the original design of the microdevice. | 09-17-2009 |
| 20090070732 | Fracture Shot Count Reduction - Techniques are described for reducing the number of shots in a fractured layout design. Each polygon in a layout design is examined for “jogs.” For each identified jog, the surrounding region is examined to determine if there is an opposing jog or parallel edge that can be aligned with the identified jog. The surrounding region then is examined for any polygon features, such as edges or vertices, which might restrict or prevent the alignment of the identified jog with the opposing jog or edge. If the identified jog can be aligned with an opposing jog or edge without violating a specified alignment constraint, then those jogs are deemed an alignable jog pair. Next, one or more of the alignable jog pairs is selected for alignment. The alignable jog pairs may be selected for alignment based upon their impact on the size of the polygon when aligned. Once one or more of the alignable jog pairs have been selected, then the layout design data will be modified to align the selected jog pairs. | 03-12-2009 |
| 20090070731 | Distributed Mask Data Preparation - Layout data is divided into segments of data, and each segment of data is distributed to a computing node in a parallel processing fracturing tool. During the fracturing process, the fracturing tool generates one or more global parameter values for each segment of data. After the fracturing process is completed, the fracturing tool will merge the segments back together using the global parameter values to ensure that the merger of the data segments does not exceed a constraint of the reticle or mask writer in which the fractured data will be employed. | 03-12-2009 |
| 20090044157 | Acyclic Modeling of Combinational Loops - Aspects of the present invention are directed to converting non-oscillatory combinational loops into acyclic circuits. Combinational loops may be modeled as state-holding elements where non-oscillatory loops are broken using edge-sensitive latches. In addition to providing a way to model combinational loops originally consisting only of gates (i.e., without originally including any state-holding elements), loops that have paths through user latches may also be converted. The presented methodology may be used with both small and large loops. | 02-12-2009 |
| 20090013292 | CONTEXT DEPENDENT TIMING ANALYSIS AND PREDICTION - In one embodiment, a method for providing a context aware timing analysis is provided. A library of cells is pre-computed to take into account contouring that may result based on possible context situations for instances in an integrated circuit design. This results in a library that includes a characterization for each of the plurality of context situations. The timing analysis may then be run after pre-computing the library based on the context situations. The context situation for instances in the integrated circuit design are determined. Then a characterization for the instances based on the context situation is determined from the pre-computed library of characterizations. Because the characterization for the context situations was pre-computed based on possible combinations of context situations that may be found in the design, a lookup of the characterized timing information may be performed. Thus, a re-characterization during runtime does not need to be performed. | 01-08-2009 |
| 20080288907 | CROSSLINKING OF NETLISTS - In one embodiment, a method for determining crosslinking between netlists is provided. The first netlist and second netlist may have nets that have different net names but may be the same net. It is also possible that the content of individual nets in one list may need to be split or combined to accurately match the other list. Complete results will not be obtained if only 1 to 1 content matches are considered. The method determines an exploded list of one of the netlists, such as the second netlist, where the netlist is reversed such that the pins of the netlist are used as keys to an associated net name. A pin in the first netlist is then determined. The pin may be associated with a first net name in the first netlist. The pin is looked up in the exploded list using it as a key to determine a second net name for the pin. The process continues using each pin in the first netlist to determine the net name associated with the pin in the second netlist. When this process is finished, crosslinks between net names that match across netlists are determined. | 11-20-2008 |
| 20080235646 | Spacers for Reducing Crosstalk and Maintaining Clearances - In one aspect of the invention is a method for reducing crosstalk and maintaining clearances between traces on a printed circuit board design. Crosstalk caused by placing traces a virtual printed circuit board are reduced by placing artificial obstructs, called spacers, between traces and/or between traces and nets to create a user-specified clearance between the traces and/or nets. As additional traces and/or nets are added to the virtual printed circuit board, the spacers are dynamic and adjust accordingly to maintain the specified clearances. | 09-25-2008 |
| 20080204159 | Digital FM Modulator - Provided are apparatuses and methods for digital FM modulation. In one example, a message signal is integrated by an integrator to transform the message signal into a complex signal. The complex signal may include at least two complex components that may interfere to produce an FM modulated carrier signal. Hence, in this example, the method and apparatus for digital FM modulation may produce an FM modulated carrier signal without phase shifting. In another example, a lookup table is not necessary for modulation of the carrier signal. | 08-28-2008 |
