| MegaChips Corporation Patent applications |
| Patent application number | Title | Published |
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| 20130145082 | MEMORY ACCESS CONTROL APPARATUS AND MEMORY ACCESS CONTROL METHOD - A memory is readable by page and erasable by block including a plurality of pages. After a read request to the memory is issued, a memory controller specifies all blocks which can be accessed based on an address specified by a read command, as candidate blocks, and specifies an inspection target page out of pages included in the candidate blocks on the basis of a predetermined rule. The memory controller inspects whether or not there is an error in the inspection target page. | 06-06-2013 |
| 20130124743 | COMMUNICATION DEVICE AND METHOD FOR OPERATING COMMUNICATION DEVICE - A communication device includes: a first communication element configured to perform communication in a first communication scheme; a second communication element configured to perform communication in a second communication scheme different from the first communication scheme by using, as common hardware, at least part among hardware that implements the communication in the first communication scheme; a schedule management section that manages which of the first communication element and the second communication element is to be used; and a sequence control section that, in accordance with an instruction given from the schedule management section, sets the common hardware so as to enable the communication in the first communication scheme or the communication in the second communication scheme to be performed. | 05-16-2013 |
| 20130028534 | IMAGE PROCESSOR - An image processor that achieves reduction in delay amount, in comparison with code amount control GOP by GOP or frame by frame, is obtained. The controller includes a first processing unit that obtains a generated amount of code used for a first predetermined number of immediately preceding macroblocks, a second processing unit that obtains an allowable amount of code available for a third predetermined number of immediately subsequent macroblocks including a currently target macroblock, based on a target amount of code for not more than a second predetermined number of macroblocks less than a total number of macroblocks included in one frame, and the generated amount of code obtained by the first processing unit, a third processing unit that obtains an expected amount of code expected to be used for the third predetermined number of macroblocks, and a fourth processing unit that sets a quantization parameter of a currently target macroblock, based on the allowable amount of code obtained by the second processing unit and the expected amount of code obtained by the third processing unit. | 01-31-2013 |
| 20130013887 | MEMORY CONTROLLER - An address comparator stores an address of data read out by a host system. Also, a buffer reads out the data from a memory and stores the data. If an address of data which is expected to be newly read out by the host system is included in addresses which have already been stored in the address comparator, the host system | 01-10-2013 |
| 20120321207 | IMAGE CODING APPARATUS - It is an object of the present invention to provide an image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A numerical value (Ftk) is generated from the lower-order six bits of the frame number (Ft) of a coding object frame. A numerical value (Fs) is generated by shifting the numerical value (Ftk) leftward by two bits. An exclusive OR of the numerical value (Ftk) and the numerical value (Fs) is calculated, to thereby generate a numerical value (A). A numerical value (Ytk) is generated from the lower-order six bits of the Y coordinate (Yt) of a coding object macroblock. The upper-order bits of the numerical value (Ytk) and the lower-order bits thereof are inverted, to thereby generate a numerical value (Yr). Further, an exclusive OR of the numerical value (Yr) and the numerical value (A) is calculated, to thereby generate a numerical value (B). A numerical value (Xtk) is generated from the lower-order six bits of the X coordinate (Xt) of the coding object macroblock. When the numerical value (Xtk) and the numerical value (B) are identical to each other, the coding object macroblock is intra-coded. | 12-20-2012 |
| 20120317463 | MEMORY CONTROLLER - An ECC circuit can operate in a plurality of error correction modes with different correcting capabilities for data stored in a memory. The ECC circuit calculates a syndrome with respect to information data in accordance with an error correction mode set by a control part and adds a syndrome of a fixed length in which dummy bits are added to the calculated syndrome, to the information data. When code data is read out, the ECC circuit performs a correction process on the code data by using the syndrome included in the code data. | 12-13-2012 |
| 20120308151 | IMAGE CODING APPARATUS - An image coding apparatus calculates the activity of each macroblock. All the macroblocks of block lines are set as intra-candidate macroblocks (intra-candidate MBs) which are candidates for intra coding. Every other macroblock is set as an intra-candidate MB in block lines. One of the intra-candidate MBs in each block line, which has the minimum activity, is determined as an intra macroblock of a frame. The macroblock determined as the intra MB is changed from the intra-candidate MB to an intra-forbidden macroblock. After changing the setting of the intra-candidate MBs, intra macroblocks are determined for a frame inputted subsequent to the frame. | 12-06-2012 |
| 20120307881 | IMAGE CODING DEVICE, IMAGE CODING/DECODING SYSTEM, IMAGE CODING METHOD, AND IMAGE DISPLAY METHOD - A device preventing degradation of image quality caused by coding of a moving image. A compression coder performs compression coding on image data of respective pictures constituting an input moving image to generate inter-coded data or intra-coded data, and outputs the coded data to a wire or wireless transmission line. In a case of causing the compression coder to generate the inter-coded data, a controller sets a code amount equal to or smaller than a maximum code amount given by a value obtained by multiplying an upper limit transmission rate of a transmission line and a permissible time allocated per picture based on a picture rate of the input moving image. Meanwhile, in a case of causing the compression coder to generate the intra-coded data, the controller sets a code amount larger than the maximum code amount and equal to or smaller than N-times (N is an integer equal to or larger than two) the maximum code amount. | 12-06-2012 |
| 20120294361 | IMAGE CODING APPARATUS - An image coding technique for suppressing degradation in image quality, in which the time and space where intra macroblocks appear are dispersed. A block count determination part determines the number of intra macroblocks to be allocated in each frame. A position determination part arranges the intra macroblocks at random positions in each frame. A coding part performs coding on the basis of the number of intra macroblocks to be allocated in a time direction, which is determined by the block count determination part, and the arrangement of the intra macroblocks in a spatial direction, which is determined by the position determination part, to thereby output compressed image data. | 11-22-2012 |
| 20120287990 | IMAGE PROCESSOR - An image processor includes an encoder that performs encoding including quantization on an image signal and a controller that controls a quantization parameter for quantization. The controller determines a quantization parameter of a currently target macroblock as an increase or decrease from a reference value, and determines the increase or decrease based on a difference between a target amount of code for a predetermined number of macroblocks fewer than a total number of macroblocks within one frame and a generated amount of code of the predetermined number of macroblocks processed immediately before. The controller can further determine the increase or decrease, based on pixel information of the currently target macroblock such as an activity evaluation value. | 11-15-2012 |
| 20120281782 | COMMUNICATION SYSTEM, COMMUNICATION APPARATUS, AND COMMUNICATION INTEGRATED CIRCUIT - A communication system includes a first communication apparatus and a second communication apparatus. The first communication apparatus generates and transmits communication data in accordance with a predetermined protocol. The second communication apparatus includes a power circuit section having a switching regulator, and is configured to receive the communication data transmitted from the first communication apparatus. The predetermined protocol includes a protocol defining that at least one portion of a bit sequence constituting the communication data should be associated with an operation of the switching regulator. The second communication apparatus causes the switching regulator to operate in a time period in which the at least one portion of the communication data is received, in a state where the communication data is received. | 11-08-2012 |
| 20120147969 | TRANSCODER - If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate S | 06-14-2012 |
| 20120128315 | DISPLAY SYSTEM AND IMAGE REPRODUCTION DEVICE - Image reproduction devices ( | 05-24-2012 |
| 20120119977 | DISPLAY DEVICE - A display device has liquid crystal display panels aligned in a horizontal scan direction. The liquid crystal display panels constitute one virtual display area. A decoder decodes image data, to thereby generate pieces of pixel data having addressees corresponding to the virtual display area. A bridge circuit specifies a target (display destination) on which the pixel data is to be displayed on the basis of a parameter table indicating a correspondence between the virtual display area and each of display areas of the liquid crystal display panels. The pixel data are stored in line buffers corresponding to the specified display destinations and outputted to the liquid crystal display panels. Out of the pixel data, pixel data corresponding to a gap formed between two liquid crystal display panels are discarded. | 05-17-2012 |
| 20120093410 | IMAGE PROCESSING APPARATUS AND METHOD FOR OPERATING IMAGE PROCESSING APPARATUS - An image processing apparatus includes a first storage section and a second storage section, a storage control section, and a computation section. The storage control section sequentially acquires block images obtained as a result of dividing an input image, and stores the block image as a target block image in the first storage section, while storing, in the second storage section, image data of, in a region of the target block image, a region abutting un-inputted block images in the input image, as image data of an abuttal region. The computation section implements a resizing process for changing the size of the target block image by performing an interpolation calculation using image data of the target block image stored in the first storage section and the image data of the abuttal region stored in the second storage section. | 04-19-2012 |
| 20120081372 | IMAGE PROCESSOR - An image processing unit includes a computing unit, a data input unit that inputs image data to the computing unit, a data output unit that outputs the image data computed by the computing unit, and a setting unit. The computing unit includes computing cells including multiple types of computing cells, input domain selectors, and at least one of output domain selectors. The setting unit sets the input domain selectors and the output domain selectors so that image data inputted by the data input unit to the computing unit on which desired computing has been performed by at least one computing cell among the computing cells is outputted from the data output unit. | 04-05-2012 |
| 20120023338 | MEMORY CONTROL DEVICE, SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND MEMORY CONTROL METHOD - A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols. | 01-26-2012 |
| 20120008772 | MEMORY CONTROLLER, MEMORY CONTROL DEVICE MEMORY DEVICE, MEMORY INFORMATION PROTECTION SYSTEM, CONTROL METHOD FOR MEMORY CONTROL DEVICE, AND CONTROL METHOD FOR MEMORY DEVICE - A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information. | 01-12-2012 |
| 20110305402 | IMAGE PROCESSOR - The image processor | 12-15-2011 |
| 20110268366 | IMAGE PROCESSING APPARATUS AND IMAGE CONVERSION APPARATUS - It is an object of the present invention to provide a technique for eliminating the unnaturalness in a generated moving image while achieving high speed processing in an image processing apparatus comprising a deblocking filter. A transcoder ( | 11-03-2011 |
| 20110267509 | IMAGE PROCESSING METHOD AND IMAGE PROCESSING DEVICE - An imaging device made of a single-chip type including a RGB Bayer pattern color filter is where pixel signals outputted from the imaging device are inputted through a signal processing part to an image processing part. A correlation judgment part judges a correlation between the pixel signals, and an interpolation processing part performs a pixel interpolation process based on a correlation result. Thus, each pixel signal becomes a perfect signal having all R, G and B color components. Filter factors for a filter are determined based on the correlation result, and a filtering process is performed on the pixel signals subjected to the pixel interpolation. | 11-03-2011 |
| 20110267496 | IMAGING DEVICE, IMAGE STORING METHOD AND RECORDING MEDIUM - An imaging device for capturing an image of a subject to acquire captured-image information, comprises: a positioning element arranged to measure a location at which the image is captured, to acquire capturing location information indicating a capturing location when the captured-image is acquired; a creation element arranged to create image information based on the capturing location information acquired by the positioning element and the captured-image information; a memory element arranged to store the image information created by the creation element; a decision element arranged to, when the image information stored in the memory element is output to the outside, decide whether or not the capturing location information included in the image information is to be kept secret; and a fabricator element arranged to fabricate the capturing location information included in the image information in accordance with a result of the decision by the decision element. Thus, it is possible to prevent leaking of information on the capturing location that is a kind of private information, minimizing reduction of convenience and versatility of the image information including the information on the capturing location. | 11-03-2011 |
| 20110200102 | IMAGE CODING APPARATUS AND IMAGE CONVERSION APPARATUS - An image coding apparatus obtains a quantization parameter of a macroblock to be encoded. The quantization parameter is corrected by adding a correction value thereto. An encoding part encodes the macroblock by using the corrected quantization parameter. After the encoding, a quantization parameter correction part calculates the cumulative target amount of codes by accumulating the target amounts of codes set for the encoded macroblocks, respectively, and calculates the cumulative amount of generated codes by accumulating the respective amounts of generated codes of the encoded macroblocks. If the cumulative amount of generated codes is larger than the cumulative target amount of codes, the quantization parameter correction part increments the correction value. A new macroblock to be encoded is quantized more coarsely than the encoded macroblocks. | 08-18-2011 |
| 20110194765 | IMAGE PROCESSING APPARATUS - An image processing apparatus is provided which offers higher versatility than conventional image processing apparatuses. When an input signal to a spatial filtering block is a monochrome signal that contains Y component only, a selector selects its input terminal and a selector selects its input terminal. Then, a low-pass filter output signal of a programmable spatial filter is inputted to a spatial filter, and a low-pass filter output signal of the spatial filer is inputted to a spatial filter. That is, the programmable spatial filter and the spatial filters are connected in series (in cascade), and the cascade-connected three spatial filters perform filtering operation. In this example, low-pass filters with 5×5 taps are connected in cascade in three stages, which enables low-pass filtering with 13×13 taps. | 08-11-2011 |
| 20110182343 | ENCODER - An average quantization error value of each of I, P, and B pictures in an encoded unit of processing is calculated as an actually measured value having a large variation. An average quantization error value of each of I, P, and B pictures in an uncoded unit of processing is set as a target value having a small variation. In the encoding of the uncoded unit of processing, a result of the encoding of the encoded unit of processing is referenced and fed back thereto. By uniformly setting respective quantization errors of images and further by uniformly setting the respective qualities of the images, the image quality of a whole stream can be subjectively improved. Since the prefetch of the uncoded unit of processing is not needed, it is possible to perform real-time processing without any increase in the circuit scale. | 07-28-2011 |
| 20110161574 | SETTING CONTROL APPARATUS AND METHOD FOR OPERATING SETTING CONTROL APPARATUS - A setting control apparatus includes a setting control part, a special register, and a read-out control part. The setting control part makes stored in a temporary storage part a control value used in a processing circuit, in response to an input of the control value. The special register is electrically connected to the processing circuit and serving as a storage element capable of storing the control value. The read-out control part controls a read-out operation for reading out the control value from the temporary storage part into the special register. The read-out control part performs the read-out operation at a predetermined timing after storing of the control value in the temporary storage part is completed. | 06-30-2011 |
| 20110158325 | IMAGE CODING APPARATUS AND IMAGE CONVERSION APPARATUS - A statistical value calculation part specifies macroblocks positioned around an object macroblock and calculates a minimum average value of activities of the macroblocks. When images of the macroblocks are flat and the minimum average value is smaller than an activity of the object macroblock, the minimum average value is set as an adjustment value. A correction factor determination part determines a correction factor on the basis of the adjustment value and a factor determination table. By multiplying a reference quantization step value by the correction factor, a quantization step value of the object macroblock is determined. Since the quantization step value reflects a distribution of the activities of the macroblocks, it is possible to suppress a local change of the quantization step value. | 06-30-2011 |
| 20110122298 | IMAGE PROCESSING APPARATUS, AND METHOD OF OPERATING AN IMAGE PROCESSING APPARATUS - An image processing apparatus includes: a relative coordinate acquisition part acquiring a corresponding position on an input image with respect to a predetermined pixel on an output image; a first storage part storing position information of the corresponding position; a reading control part causing pixel values of input pixels on the input image to be sequentially read; an organization part organizing a set of grid points formed of input pixels among input pixels read by the reading control part; a judgment part judging, based on the position information, whether or not pixel values of pixels in the vicinity of the corresponding position used in calculating a pixel value of the predetermined pixel have been read; a local memory storing, in a case where judgment is made that pixels in the vicinity of the corresponding position have been read, pixel values of pixels forming the set of grid points as pixel values of surrounding pixels regarding the predetermined pixel; and a pixel value calculation part calculating a pixel value of the predetermined pixel by interpolation using the pixel values of the surrounding pixels. | 05-26-2011 |
| 20110075737 | TRANSCODER - A generated code amount accumulation part adds up the amounts of generated codes of pictures in 1 GOP which are encoded up to the current stage. An upper limit code amount accumulation part adds up the upper limit amounts of codes of the pictures in the 1 GOP which are encoded up to the current stage. A transmission load of an image transmission system is taken into consideration in the setting of the upper limit amount of codes. An update ratio setting part outputs an update instruction to lower a target rate when the accumulated amount of generated codes exceeds the accumulated upper limit amount of codes. The update ratio setting part does not output the update instruction for lowering the target rate when the accumulated amount of generated codes does not exceed the accumulated upper limit amount of codes. A transcoder can predict whether or not there is a possibility that the load of transmitting image data will increase while each picture in 1 GOP is encoded. | 03-31-2011 |
| 20110075731 | TRANSCODER - A transcoder that controls the amount of generated codes of an output stream toward a target bit rate without degradation of image quality. The transcoder decodes a first stream and encodes the decoded image again to thereby output a second stream. The transcoder calculates a distortion evaluation value from the image obtained by decoding the first stream and an image obtained by decoding the second stream. Assuming that a ratio between the distortion evaluation value and a total target distortion evaluation value is determined as a target distortion ratio, a target setting bit rate of a second stream in the period can be obtained by multiplying a total target bit rate of the second stream by the target distortion ratio. Alternatively, the target setting bit rate can be obtained by adjusting the target distortion ratio with an appropriate function and adding the target distortion ratio to the total target bit rate of the second stream. | 03-31-2011 |
| 20100293171 | IMAGE PROCESSOR - A first sorting unit includes a second sorting unit that sorts first frequency data for luminance based on a first table, a third sorting unit that sorts second frequency data for chrominance based on a second table, a fourth sorting unit that sorts third frequency data for chrominance based on a third table, and an updating unit that updates the second and third tables based on nonzero information on the first and second frequency data before the third and fourth sorting units start sorting. | 11-18-2010 |
| 20100278266 | METHOD OF GENERATING IMAGE DATA - Search is performed on Intra 16 to obtain a prediction mode leading to a minimum cost, and the minimum cost in Intra 16 and a corresponding prediction mode are stored. Search is performed on Intra 8 to obtain a prediction mode leading to a minimum cost, and then a relationship of magnitude between the stored minimum cost in Intra 16 and the minimum cost in Intra 8 is judged. After that, the minimum cost in Intra 8 and a corresponding prediction mode are stored, and search is performed on Intra 4 to obtain a prediction mode leading to a minimum cost. A relationship of magnitude between cost_intra and the minimum cost in Intra 4 is judged, and Intra 4 is determined as an optimum prediction mode in a case where Intra 4 is smaller. | 11-04-2010 |
| 20100268729 | MULTIMEDIA SYNTHETIC DATA GENERATING APPARATUS - A technique for drawing or managing multimedia data by desired groups. In a built-in memory of a cellular phone terminal, thirteen picked-up image data are stored. In tag information of each of the thirteen picked-up image data, information on date and time is recorded when an image of the data is picked up. When a user specifies the range of image pickup date and time, eight picked-up image data that match the specified range of image pickup date and time are selected and synthetic image data is generated from these eight picked-up image data. | 10-21-2010 |
| 20100162040 | MEMORY SYSTEM AND COMPUTER SYSTEM - A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks. | 06-24-2010 |
| 20100161937 | MEMORY SYSTEM AND COMPUTER SYSTEM - A memory system of the present invention comprises a plurality of first blocks provided for storing user information therein, to which first physical addresses which are not duplicate are assigned, respectively, a plurality of second blocks provided for individually storing therein the first physical addresses of initial defective blocks out of the plurality of first blocks, and a plurality of third blocks provided for individually storing therein the first physical addresses of late defective blocks out of the plurality of first blocks. The memory system further comprises a computing device for obtaining the first physical address corresponding to a logical address on the basis of the logical address, information stored in the second blocks, and information stored in the third blocks. | 06-24-2010 |
| 20100135589 | IMAGE PROCESSOR - An image processor includes a frequency transform unit performing frequency transform on a first pixel block as a target block, and a pre-filter performing prefiltering with a region which overlaps with plural unit regions for processing by the frequency transform unit as a unit region for processing, before frequency transform is performed. The pre-filter performs prefiltering on a second pixel block being a predetermined number of pixels each larger horizontally and vertically than the first pixel block as a target block. The pre-filter performs prefiltering sequentially on a plurality of second pixel blocks aligned horizontally. The number of pixel signals in a vertical direction within a group of pixel signals continuously inputted to the pre-filter for prefiltering is equal to the number of rows in the second pixel block. | 06-03-2010 |
| 20100128999 | IMAGE COMPRESSION APPARATUS - A symbol generation part serially inputs a data string of quantization data. If quantization data of non-zero coefficient is inputted, respective information on an absolute value, a zero run and a sign of the non-zero coefficient are stored in registers. When quantization data of the next non-zero coefficient is inputted, the respective information on the absolute value, the zero run and the sign stored in the registers are updated. At that time, the contents of the registers which have been stored immediately before the input are outputted as symbol data of the immediately preceding non-zero coefficient. | 05-27-2010 |
| 20100104206 | IMAGE COMPRESSION APPARATUS - An image compression apparatus performs quantization of DC component data, low-pass component data and high-pass component data which are generated by frequency conversion of still image data. An extracting part extracts additional data and coding object data which is to be entropy coded, from quantization data. An entropy coding part performs entropy coding of the coding object data stored in a coding object data memory. An additional data processing part generates a flex bit from the additional data. A pattern information generation part acquires the coding object data directly from the extracting part, to generate pattern information indicating whether the coding object data is zero or not. A bit stream generation part outputs the pattern information, the coding object data and the flex bit in a predetermined order, to output a bit stream. | 04-29-2010 |
| 20100104183 | IMAGE ENLARGEMENT METHOD - A correlation value calculation circuit calculates respective correlation values of each pixel for color image or for gray image in four directions. A selection circuit determines respective correlation values (Cv, Ch, Cd | 04-29-2010 |
| 20100086223 | IMAGE PROCESSOR - A decoding unit includes a first processing unit including ND decoding units and decoding a group of Normal Data, a second processing unit decoding a group of Flex Bits, and a selector. The ND decoding units perform decoding of the group of Normal Data, stepwise varying a start position of decoding in the data stream, concurrently with decoding of the group of Flex Bits by the second processing unit. The selector selects one ND decoding unit with a start position of decoding being set at a position immediately following an end position of the group of Flex Bits, from the ND decoding units, based on a result of decoding of the group of Flex Bits. | 04-08-2010 |
| 20100037013 | MEMORY ACCESS METHOD - A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive occurrences of access to allow for improved performance. Pieces of data are written into 0th, the first, the second, and the third banks, respectively. No idle time is caused between successive occurrences of access because different banks are successively accessed. Since a burst length of each of the pieces of data is eight, an interval of 16 cycles which is longer than 15 cycles is provided between a start of writing of first data and a start of second writing of data. Accordingly, no idle time is caused also between completion of writing of the first data and start of writing of the second data. | 02-11-2010 |
| 20090256932 | SINGLE-LENS REFLEX DIGITAL CAMERA - The single-lens reflex digital camera includes a CCD for imaging an image for storage and a CCD for imaging an image for live view. A pixel signal output from the CCD is processed in an image preprocessing unit, an image general processing unit, and a JPEG processing unit and stored in a memory card as JPEG data. A pixel signal output from the CCD is processed in a live image processing unit and stored in the memory card as YUV data for display. A display control unit reads the YUV data for display from the main memory and outputs the data to a LCD. The CPU adjusts frame rate of the live view image depending on the usage rate of the band of a main bus. | 10-15-2009 |
| 20090245674 | IMAGE PROCESSOR - An image processor includes a quantization unit receiving first data before quantization and outputting second data after quantization, a prediction unit obtaining a difference value between the second data and third data being prediction data and outputting the difference value as fourth data, and an encoding unit encoding the fourth data. The quantization unit includes a first processing unit dividing the first data by a quantization coefficient, so as to obtain fifth data including a fraction as a result of division and a second processing unit rounding up or rounding off the fraction such that a value of the fourth data becomes smaller based on comparison between the third data and the fifth data, so as to obtain the second data. | 10-01-2009 |
| 20090245669 | IMAGE PROCESSOR - An image processor includes an encoding unit encoding inputted data. The encoding unit includes a first processing unit splitting the data into a first partial data in a first digit range on an upper side and a second partial data in a second digit range on a lower side, a second processing unit encoding only the first partial data between the first partial data and the second partial data, and a third processing unit performing correction to set a value of the first partial data at “0”. | 10-01-2009 |
| 20090238477 | IMAGE PROCESSOR - An image processor includes an encoder and a decoder. The encoder includes a frequency transform unit, a pre-filter, and a color conversion unit that converts a pixel signal of a first color space inputted from outside into a pixel signal of a second color space including a luminance signal and chrominance signals. The decoder includes a frequency inverse transform unit, a post-filter, and a color inverse conversion unit that inversely converts a pixel signal of the second color space into a pixel signal of the first color space. The pre-filter performs prefiltering on one or plural specific signals among the luminance and chrominance signals. The post-filter does not perform postfiltering on the above specific signals. | 09-24-2009 |
| 20090238447 | IMAGE PROCESSOR - An image processor includes a frequency transform unit performing frequency transform independently on a luminance signal and plural chrominance signals and outputting an item of frequency data of the luminance signal and plural items of frequency data of the chrominance signals, and a quantization unit performing quantization independently on plural items of frequency data inputted from the frequency transform unit. The quantization unit performs quantization on one or plural specific items of frequency data corresponding to a signal with noise among the frequency data of the luminance signal and the chrominance signals, employing a quantization coefficient having a value greater than “1”, and performs quantization on frequency data apart from the specific items of frequency data, employing a quantization coefficient having a value “1”. | 09-24-2009 |
| 20090238266 | TRANSCODER - A category setting part sets a type of a decoded image based on characteristics of the decoded image which are fineness of the decoded image and an intensity of movement of the decoded image. A code amount setting part sets a target code amount of an output image based on the type of the decoded image. A quantization step value setting part sets a quantization step value of the output image based on the target code amount of the output image. A transcoder can set the target code amount of the output image depending on fineness of the decoded image. The transcoder can distribute the target code amount of the output image to a reference image and a predicted image depending on the intensity of movement of the decoded image. | 09-24-2009 |
| 20090237569 | TRANSCODER - A scene change detection part detects a scene change based on a characteristic amount of an input image. A target code amount setting part executes correction by a correction code amount on a target code amount previously set for suppressing variation of an output code amount around the time of scene change. A quantization step value setting part sets a quantization step value based on the target code amount. That is to say, a transcoder | 09-24-2009 |
| 20090237532 | NOISE REDUCTION DEVICE AND DIGITAL CAMERA - The first array register stores neighboring pixels of the same color as the pixel of interest, which are sorted according to the size of the pixel value. The maximum signal comparison circuit compares the value obtained by adding the threshold ThB to the pixel value maxC, which is the (b | 09-24-2009 |
| 20090232393 | IMAGE PROCESSOR - In a first input step from outside to an image processor, a signal input unit inputs to a pre-filter a first part of first luminance signals inputted from outside, which is a part to be processed by the pre-filter in the first input step, and stores a remaining second part of the first luminance signals in the memory unit. In a second input step following the first input step, the signal input unit inputs to the pre-filter the second part of the first luminance signals read from the memory unit and a first part of second luminance signals inputted from outside, which is a part to be processed by the pre-filter in the second input step, and stores a remaining second part of the second luminance signals in the memory unit. | 09-17-2009 |
| 20090213929 | TRANSCODER - In a transcoder, a decoder decodes a stream and an encoder encodes the stream again. The encoder calculates the quantization step value by using an average period bit rate (AS | 08-27-2009 |
| 20090213928 | TRANSCODER - If the number of frames in a GOP of an input stream is not less than 15, the GOP is determined as a control unit time. If the number of frames in the GOP is less than 15, the following GOP is connected thereto until the number of frames becomes not less than 15 and the connected GOPs are determined as a control unit time. After correcting the control unit time, the average input bit rate S | 08-27-2009 |
| 20090136153 | PIXEL INTERPOLATION METHOD - An image processing circuit inputs pixels of an RGB Bayer array therein. A chroma value calculation circuit calculates a chroma factor (K | 05-28-2009 |
| 20090103821 | FREQUENCY CONVERTER AND FREQUENCY INVERTER - On the first hierarchical layer, the input image adjuster selects an overlap processing area from a frequency-unconverted image. On the first hierarchical layer, the overlap processor performs overlap processing on the overlap processing area, and holds the image data of the remaining processing areas, which cannot be frequency-converted. The remaining processing area, which is a linear area, can have an image width reduced down to the displacement between the overlap processing area and the block areas. The processes on the second hierarchical layer are identical to those on the first hierarchical layer. As a result, the encoder maximizes the advantage of the high performance achieved by hardware implementation. | 04-23-2009 |
| 20090070501 | DATA PROCESSOR - A format converter includes a first input buffer for storing input data, an output buffer for storing output data, a converter connected between the first input buffer and the output buffer, and a register that the converter refers to. The register allows plural kinds of conversion patterns to be defined in conformity with a desired data format conversion. The converter generates the output data based on the input data, in accordance with the conversion pattern defined in the register. | 03-12-2009 |
| 20090067015 | BLOCK MATCHING CIRCUIT AND DATA UPDATE METHOD - Scanning image data and target image data are respectively stored in a first storage area and a second storage area. In one case, (J−M+1)×(K−N+1)×M×N pieces of pixel data are stored as comparison image data relating to all comparison areas, and M×N pieces of pixel data are stored as target image data. In contrast, the present invention requires the storage only of J×K pieces of pixel data as scanning image data, and M×N pieces of pixel data as target image data. This means the number of pieces of pixel data to be stored is reduced. In the case discussed above, one piece of target image data and (J−M+ | 03-12-2009 |
| 20090060389 | IMAGE PROCESSING APPARATUS - From an image pickup element, pixel signals of Bayer array are outputted. A correlation calculation part calculates correlation values with respect to a specified pixel in vertical and horizontal directions. A first interpolation part performs a pixel interpolation process while evaluating the correlation highly. A second interpolation part performs a pixel interpolation process while evaluating the correlation relatively low. A complete signal of RGB outputted from the first interpolation part is converted into a luminance signal in a first color space conversion part, and a complete signal of RGB outputted from the second interpolation part is converted into a color difference signal in a second color space conversion part. | 03-05-2009 |
| 20090044076 | MEMORY ACCESS SYSTEM - The ECC circuit generates the first syndrome of write data, which have not been written to the memory. The EDC circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced. | 02-12-2009 |
| 20090041371 | IMAGE PROCESSING APPARATUS - A correlation judgment part judges a correlation direction on each pixel. In a case where a correlation direction of a specified pixel is a vertical direction and the correlation thereof is small in any other direction, it is judged that the specified pixel is a pixel on an edge in the vertical direction. Then, a noise removal filtering operation is performed on the specified pixel by using pixels on a line in the vertical direction and an edge enhancement operation is performed by using pixels on a line in a horizontal direction. | 02-12-2009 |
| 20090040321 | DIGITAL CAMERA SYSTEM - The present invention provides a technique capable of generating an image having a portrait effect without complicating a configuration of a digital camera system. An image capturing apparatus has an optical system including a zoom lens, a correction lens, and a focus lens; and an image sensor for converting subject light which is incident via the optical system into an electric signal. The image capturing apparatus captures a blurred image in which a blurring is generally caused intentionally by changing a relative positional relation between any one of the zoom lens, the correction lens, and the focus lens and the image sensor, and also captures a normal image in which a blurring is not caused intentionally. An image processing apparatus combines the normal image and the blurred image, thereby generating a composite image having a no-blurring area in which a blurring is not intentionally caused and a blurred area in which a blurring is intentionally caused. | 02-12-2009 |
| 20090034620 | MOTION ESTIMATION METHOD - A motion estimation method capable of reducing the amount of calculation as compared to a full search method. In the method, a coarse search block and fine search blocks are defined. The fine search blocks are given by dividing the coarse search block into a plurality of blocks so that the fine search blocks are contained in the coarse search block. A sparsely interpolated image and a densely interpolated image are defined. A first search is performed using the defined coarse search block and the defined sparsely interpolated image. A second search is performed using the defined coarse search block and the defined densely interpolated image. With regard to search blocks belonging to the fine search blocks, only a surrounding region of an optimal point obtained in the first search is searched. | 02-05-2009 |
| 20080320342 | MEMORY CONTROLLER - A memory controller carries out error detection on a wide range of area of a memory cell array, which includes not only readout addresses but also non-readout addresses. Thus, by carrying out error detection at an address at which an error occurs without accessing the address for readout, it is possible to detect occurrence of an error at the address. Accordingly, it is possible to prevent a “read disturb phenomenon” in which repetition of access to a readout address for readout may probably cause an error at a non-readout address other than the readout address. | 12-25-2008 |
| 20080294949 | MEMORY ACCESS SYSTEM - When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts. | 11-27-2008 |
| 20080259708 | MEMORY CONTROLLER - A memory controller for controlling data access to a memory comprises a refresh controller. A read count memory part included in the refresh controller counts the number of read operations on each page of the memory and stores the read count therein. If the read count for any page exceeds a predetermined number, the refresh controller rewrites data stored in this page into the memory. | 10-23-2008 |
| 20080244175 | MEMORY SYSTEM AND COMPUTER SYSTEM - When a memory card is inserted into a computer, a memory controller sends command information stored in a memory array to the computer. Then, the computer stores the command information received from the memory card into a RAM. The computer generates a command as needed on the basis of the stored command information and sends the generated command to the memory card. When the memory card receives the command from the computer, the memory controller analyzes the received command and performs it while making reference to command analysis information. This makes it possible to reduce a load accompanying the change and addition of commands in a semiconductor memory. | 10-02-2008 |
| 20080229002 | SEMICONDUCTOR MEMORY AND INFORMATION PROCESSING SYSTEM - A semiconductor memory ( | 09-18-2008 |
| 20080215954 | BIT ERROR REPAIR METHOD AND INFORMATION PROCESSING APPARATUS - An information processing apparatus has an error correction function for checking an error of stored data read out from a flash memory. If an error is found, error information thereof is temporarily stored into a register and then stored in a nonvolatile memory at an appropriate timing. At an appropriate timing such as power-on, the information processing apparatus reads the stored data in which the error is found again on the basis of the error information stored in the nonvolatile memory, corrects the error and then rewrites the stored data into the flash memory. It is thereby possible to repair a recoverable bit error such as a read disturb. Therefore, a normal read operation can be performed without a hitch, and this can avoid giving any uncomfortable feeling to users. | 09-04-2008 |
| 20080211967 | IMAGING UNIT, PORTABLE TERMINAL DEVICE, AND PORTABLE TERMINAL SYSTEM - The present invention provides an imaging unit, a portable terminal device, and a portable terminal system capable of performing a satisfactory key synthesizing process. An imaging unit mainly includes an imaging section, a conversion section, and a key signal generating section. The conversion section converts the format of the imaged image data output from the imaging section from YUV format to RGB format. The key signal generating section generates a key signal based on each pixel data configuring the imaged image data and the reference data for the imaged image data input from the imaging section. The key signal generating section also outputs foreground image data having the generated key signal and the corresponding pixel data of RGB format as minimum configuring unit. An image synthesizing section of a main unit generates synthesized image data by overlapping the foreground image data from the imaging unit and the background image data stored in a RAM based on the key signal contained in the foreground image data. | 09-04-2008 |
| 20080201546 | MEMORY SYSTEM, COMPUTER SYSTEM AND MEMORY - The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with the physical addresses of defective blocks in a memory skipped. Then, the physical addresses of the defective blocks in ascending order are sequentially stored into the second blocks in ascending order of the physical addresses of the second blocks, respectively. To obtain a physical address from a logical address, a target block is retrieved out of a plurality of second blocks on the basis of the logical address, and the physical address of the target block is added to the logical address to obtain the physical address. Thus, it is possible to reduce the required capacity of a reserve storage region used for conversion of logical addresses into physical addresses without deteriorating the access speed. | 08-21-2008 |
| 20080201538 | MEMORY CONTROL METHOD AND MEMORY SYSTEM - Error-tolerant code conversion is carried out on original data including a large amount of binary data which is apt to be unintentionally rewritten, to produce converted data including a smaller amount of binary data which is apt to be unintentionally rewritten, and the converted data is written into a memory. While a host system is processing the original data, the memory reads out the converted data and the code inverse transformation part carries out inverse transformation of error-tolerant code conversion on the converted data, to output reproduced data which is identical to the original data, to the host system. As a result, it is possible to avoid or suppress the possibility that data is unintentionally rewritten due to repeated readout of the same data. | 08-21-2008 |
| 20080199005 | SIGNAL PROCESSOR - Original data to be a source for an encryption key is read from a memory cell array and stored in a buffer region. An encryption key generation unit generates a plurality of encryption keys by variously modifying the original data read from the buffer region based on a predetermined generation rule. The encryption unit generates an encrypted command by encrypting commands individually with an encryption key different for each command, out of the plurality of encryption keys generated by the encryption key generation unit. | 08-21-2008 |
