| MEDIATEK SINGAPORE PTE. LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120128067 | Apparatus and Method of Constrained Partition Size for High Efficiency Video Coding - An apparatus and method for video coding and decoding with constrained PU partition are disclosed. In the High Efficient Video Coding (HEVC) system, rate-distortion function or other performance criterion usually is evaluated for various CU partition and PU partition during the encoding process in order to select a configuration with best possible performance. The PU design in the current HEVC development results in some redundancy that causes rate-distortion function or other performance criterion repeatedly evaluated for same PU configuration. Accordingly, constrained PU partition is developed to eliminate or reduce the redundancy in processing. Furthermore, necessary syntax to convey the information related to constrained PU partition between an encoder and a decoder is developed. Systems embodying the present invention has been shown to result in sizeable reduction in encoding and decoding time while the performance in terms of RD-rate remains approximately the same or slightly higher than a conventional HEVC system. | 05-24-2012 |
| 20110239098 | Detecting Data Error - A method includes segmenting a first portion of a data block into a plurality of segments that includes a first segment. The data block includes a second portion, different from the first portion, which stores cyclic redundancy check data calculated from data stored in the first portion of the data block. The method also includes calculating cyclic redundancy check data from the first segment, and, translating the calculated cyclic redundancy check data to a location associated with the data block. The method also includes combining the cyclic redundancy check data associated with the first segment and cyclic redundancy check data associated with at least one other segment included in the plurality of segments. The method also includes using the combined cyclic redundancy check data for error detection. | 09-29-2011 |
| 20110105175 | Method and System for Managing Transmitting Power of Communications Devices Equipped with a Plurality of Antennas - A communications system and method for managing transmitting power of communications devices equipped with multiple antennas. A first communications device enables a first antenna configuration in accordance with a first pre-determined rule. A second communications device activates a second antenna configuration in accordance with a second predetermined rule. First and second messages are exchanged between the first and second communications devices. The first message includes the power management profile of the first communications device and the second message includes information pertinent to a power management profile of the second communications device, and signal integrity information determined by the second communications device from the received first message. The first communications device enables a third antenna configuration in accordance with the first pre-determined rule and the second communications device activates a fourth antenna in accordance with the second pre-determined rule configuration after the first and second messages have been exchanged. | 05-05-2011 |
| 20110007912 | DOUBLE INTEGRAL METHOD OF POWERING UP OR DOWN A SPEAKER - An audio subsystem having a waveform generation circuit that generates a power-up signal for controlling an electric signal used to drive a speaker during a power-up period in which the power-up signal has a positive second derivative during a first sub-period of the power-up period and has a negative second derivative during a second sub-period of the power-up period. The first sub-period spans at least one-fourth of the power-up period, and the second sub-period spans at least one-fourth of the power-up period. | 01-13-2011 |
| 20110002386 | VIDEO ENCODER AND METHOD FOR PERFORMING INTRA-PREDICTION AND VIDEO DATA COMPRESSION - The invention provides a method for performing intra-prediction. A target pixel is selected from a plurality of pixels of a current block. A first intra-prediction mode of a left block, a second intra-prediction mode of an up block, and a third intra-prediction mode of the current block are then determined. A first prediction value of the target pixel is calculated according to the first intra-prediction mode. A second prediction value of the target pixel is calculated according to the second intra-prediction mode. A third prediction value of the target pixel is calculated according to the third intra-prediction mode. The first prediction value, the second prediction value, and the third prediction value are then averaged to obtain a weighted-average prediction value as an intra-prediction value of the target pixel. | 01-06-2011 |
| 20100328124 | CURRENT STEERING DIGITAL-TO-ANALOG CONVERTER - A digital to analog converter (DAC) module receives an input digital signal having a first data rate and is associated with a first frequency, the DAC module also receiving a synchronization signal having a second frequency that is higher than the first frequency. The DAC module includes an up-sampling circuit to generate a first digital signal having bit values of the input digital signal alternating with zero values, the first digital signal having a data rate that is higher than the first data rate; a delay circuit to delay the first digital signal by a time period to generate a second digital signal; a first DAC cell to generate a first analog signal based on the first digital signal, the first DAC cell being synchronized by the synchronization signal; a second DAC cell to generate a second analog signal based on the second digital signal, the second DAC cell being synchronized by the synchronization signal; and an adder to sum the first and second analog signals and generate a third analog signal. | 12-30-2010 |
| 20100310065 | SYSTEM AND APPARATUS FOR INTEGRATED VIDEO/IMAGE ENCODING/DECODING AND ENCRYPTION/DECRYPTION - An encryption-enabled entropy coder for a multimedia codec is disclosed. The entropy coder implements a randomized Huffman coding scheme without storing multiple sets of Huffman tables in a ROM. The entropy coder includes a ROM storing a single set of code tables, a table lookup section coupled to the ROM which converts symbols to original codewords and vice versa by performing table lookup, and a table randomizer section for converting original Huffman codewords to randomized Huffman codewords and vice versa using an isomorphic code generator algorithm. The table randomizer section performs the conversion based on a key hopping sequence generated by a pseudorandom bit generator using an encryption/decryption key. | 12-09-2010 |
| 20100278338 | CODING DEVICE AND METHOD WITH RECONFIGURABLE AND SCALABLE ENCRYPTION/DECRYPTION MODULES - A reconfigurable and scalable cryptography (encryption/decryption) system architecture and related method are described. The system utilizes a multiple-pass approach, each pass applying one cryptography algorithm with its own cryptography keys. The encrypted data can only be fully and correctly decrypted with the correct algorithms in the correct sequence (as determined by one or more security level parameters) and the correct cryptography keys. The system includes a multiple cryptography algorithm set section which is reconfigurable to perform multiple cryptography algorithms sequentially, and a cryptography controller which receives an input key set and a security level parameter. The cryptography controller reconfigures the multiple cryptography algorithm set section based on the security level parameter to perform multiple selected cryptography algorithms in a selected sequence. The cryptography controller also generates cryptography keys based on the input key set and provide the cryptography keys to the multiple cryptography algorithm set section. | 11-04-2010 |
| 20100254466 | METHOD FOR BEAMFORMING TRAINING AND COMMUNICATIONS APPARATUSES UTILIZING THE SAME - A communication system includes a trainee communications device and one or more trainer communications devices. The trainee communications device announces a first period of time for beamforming training, switches a receiving antenna pattern to a sector and stays in the sector for a second period of time. The trainer communications devices transmit one or more predetermined bit sequences in the first period of time. The predetermined bit sequences are transmitted in at least one sector. Each of the predetermined bit sequences carries an identifier identifying the transmitting trainer communications device. The trainee communications device further estimates channel characteristics and computes receiving antenna weighting vectors of the trainer communications devices by using the received predetermined bit sequences, respectively, and the trainer communications devices obtain pertinent information including the estimated channel characteristics and receiving time of the predetermined bit sequences about beamforming training from the trainee communications device. | 10-07-2010 |
| 20100222997 | ROAD SELECTION METHOD - A road selection method is provided, whereby obstructed routes are avoided. First, an off road point is input on a map. Based on the off road point, an on road point is selected, having a shortest straight line distance from the off road point where no obstacle lies therebetween. Thereafter, route planning is performed based on the on road point. When defining the map, the obstacles may comprise rivers, buildings and un-traversable objects on the map. | 09-02-2010 |
| 20100052803 | VOLTAGE CONTROLLED OSCILLATOR - An integrated circuit and an apparatus are provided. The integrated circuit comprises a bias circuit, an LC resonator circuit, and a current mode logic (CML) frequency divider. The bias circuit generates first and second bias voltages. The LC resonator circuit generates an oscillation signal having an oscillation frequency. The CML frequency divider, coupled to the bias circuit and the LC resonator circuit, biased by the first and second bias voltages, receives the oscillation signal to generate an output signal having an output frequency with a fractional rate of the oscillation frequency. The oscillation signal comprises AC and DC components, the CML frequency divider receives the AC component to determine an injected frequency and reuses the DC component to provide tail currents to determine a natural frequency of the CML frequency divider. The output frequency is determined by the injected frequency and the natural frequency. | 03-04-2010 |
| 20090256635 | LINEAR-IN-DB VARIABLE GAIN AMPLIFIER - A variable gain amplifier (VGA) with a gain thereof exponential to a control voltage thereof. The variable gain amplifier (VGA) comprises an exponential DC converter, and a linear voltage multiplier. The exponential DC converter receives the control voltage and generates an exponential voltage which is exponential to the control voltage. The linear voltage multiplier is coupled to the exponential DC converter and has a gain proportional to the exponential voltage of the exponential DC converter. | 10-15-2009 |
| 20090033428 | VOLTAGE CONTROLLED OSCILLATOR - An integrated circuit is provided. The integrated circuit comprises a voltage controlled oscillator and a first compensation capacitor. The voltage controlled oscillator generates an oscillation signal. The first compensation capacitor, coupled in parallel to the voltage controlled oscillator, receives a control voltage to generate a negative temperature coefficient capacitance to compensate for frequency drift of the oscillation signal. The control voltage is temperature dependent. | 02-05-2009 |
| 20080303579 | MIXER WITH CARRIER LEAKAGE CALIBRATION - A mixer circuit. The mixer circuit comprises a double-balanced mixer and a carrier-leakage calibration cell. The double-balanced mixer has first and second input pairs whereby the first input pair receives the first differential input signal. The carrier-leakage calibration cell receives the second differential input signal and a differential calibration current and generates first and second output voltages to the second input pair of the double-balanced mixer. | 12-11-2008 |
| 20080284489 | TRANSCONDUCTOR AND MIXER WITH HIGH LINEARITY - A transconductor. The transconductor comprises first and second active device networks. The first active device network has a first node and a second node and comprises a first MOS transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. The second active device network has a first node and a second node respectively connected to the first and second nodes of the first active device network and comprises a second MOS transistor and a voltage drop generator. The second MOS transistor has a gate and a source respectively connected to the gate and the source of the first MOS transistor. The voltage drop generator is coupled between a drain of the second MOS transistor and the second nodes of the first and second active device networks and generates a voltage drop across the same. | 11-20-2008 |
