| MaxLinear, Inc. Patent applications |
| Patent application number | Title | Published |
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| 20120134451 | Method and System for a Low-Complexity Soft-Output MIMO Detection - An approach for Soft-output K-Best MIMO detection comprises computing an estimated symbol vector and Log-Likelihood Ratio (LLR) values for transmitted bits. The approach includes a relevant discarded paths selection process, a last-stage on-demand expansion process, and a relaxed LLR computation process. The relevant discarded paths selection process includes analyzing the K-Best paths and discarded paths at each intermediate tree level and selecting only those discarded paths for further processing that will help in LLR computation for at least one of the transmitted bits. The last-stage on-demand expansion process includes expanding K paths at the tree level 2N | 05-31-2012 |
| 20120105284 | GPS ANTENNA DIVERSITY AND NOISE MITIGATION - A system and method for improving acquisition sensitivity and tracking performance of a GPS receiver using multiple antennas is provided. In an embodiment, the acquisition sensitivity can be improved by determining the correlation weight of each received path signal path associated with one antenna form a plurality of antennas and then combining the path signals based on their respective correlation weight. In another embodiment, carrier offset correction information of each path signal is individually determined and then summed together to be used for tracking the code phase in a code phase tracking loop. The code phase tracking loop generates an early code and a late code that are used to determine the code phase error. The system includes notch and bandpass filters to mitigate narrowband and broadband noises of a received GPS signal, wherein the digital adaptive filters are switched on periodically or by external events. | 05-03-2012 |
| 20120105277 | TIME SYNCHRONIZATION WITH AMBIENT SOURCES - Systems and methods for extracting synchronization information from ambient signals, such as broadcast television signals, and using the synchronization information as a reference for correcting the local time base so that a GNSS positioning receiver system maintains relative time base accuracy with respect to a GNSS time. | 05-03-2012 |
| 20120079287 | Firmware Authentication and Deciphering for Secure TV Receiver - A method for authenticating and deciphering an encrypted program file for execution by a secure element includes receiving the program file and a digital certificate that is associated with the program file from an external device. The method stores the program file and the associated certificate in a secure random access memory disposed in the secure element and hashes the program file to obtain a hash. The method authenticates the program file by comparing the obtained hash with a checksum that is stored in the certificate. Additionally, the method writes runtime configuration information stored in the certificate to corresponding configuration registers disposed in the secure element. The method further generates an encryption key using a seed value stored in the certificate and a unique identifier disposed in the secure element and deciphers the program file using the generated encryption key. | 03-29-2012 |
| 20120079279 | Generation of SW Encryption Key During Silicon Manufacturing Process - A method of generating an encryption key during the manufacturing process of a device includes randomly generating a seed, encrypting a unique identifier disposed in the device to obtain a first encryption key, encrypting the first encryption key using a public key to obtain a second encryption key, and sending the second encryption key and the seed to a software provider. The method further includes receiving the second encryption key and the seed by the software provider and decrypting the second encryption key using a private key to recover the first encryption key. The manufacturer then encrypts a program code using the recovered first encryption key and installs the seed in a certificate that is associated with the encrypted program code. | 03-29-2012 |
| 20120079261 | Control Word Obfuscation in Secure TV Receiver - A device for descrambling encrypted data includes a descrambler, a secure link, and a secure element that securely transmits a control word to the descrambler in a normal operating mode. The secure element includes a first secure register, a read-only memory having a boot code, a random-access memory for storing a firmware image from an external memory, and a processor coupled to the first secure register, the read-only memory, and the random access memory. The processor executes the boot code to generate the control word, stores the control word in the first secure register, and send the stored control word to the descrambler through a secure communication link. The descrambler may include a second secure register that is connected to the first secure register through the secure link. The first and second secure registers are not scannable during a normal operation. The secure link contains buried signal traces. | 03-29-2012 |
| 20120060039 | Code Download and Firewall for Embedded Secure Application - A device includes a demodulator for receiving an encrypted content, an interface unit communicatively coupled to an external memory, and a hardware unit coupled to the demodulator and configured to enable the demodulator to decrypt the received content. The hardware unit includes a processing unit, a ROM having a boot code causing the device to fetch data from the external memory, a RAM for storing the fetched data, multiple non-volatile memory registers or fuse banks, and a mechanism configured to write the stored data to an external storage device in response to a backup event. The data may be encrypted using an encryption key prior to being written to the external storage device. The interface unit may include a wired or wireless communication link. The boot code includes executable instructions performing a series of validations. The device disables the executable instructions in the event of a validation failure. | 03-08-2012 |
| 20120057621 | Diversity Receiver - A diversity receiver includes a first receiving channel and a second receiving channel. The receiver also includes a baseband processor that computes a difference between the received signal strengths of the signals received from the first and second channels, wherein the processor disables the signal received from the second channel if the difference is greater than a first threshold value and a BER associated with the second receiving channel is greater than a BER threshold value, and disables the signal received from the first channel if the difference is less than the negative first threshold value and the bit error rate (BER) associated with the first channel is greater than the BER threshold value. The receiver further includes a bypass circuit coupled to an input of an amplifier and a RSSI circuit that provides a conduction path between the input and a ground when the RSSI circuit detects a blocker signal. | 03-08-2012 |
| 20120042157 | RAM Based Security Element for Embedded Applications - An integrated circuit includes a demodulator for receiving an encrypted message and a hardware unit coupled to the demodulator and configured to enable the demodulator to decrypt the received message. The hardware unit includes a processing unit, a read-only access memory (ROM) having a boot code causing the integrated circuit to fetch data from an external memory, a random access memory (RAM) for storing the fetched data, multiple non-volatile memory registers or fuses, and an interface unit configured to write the data stored in the RAM to an external storage in response to a backup event. The data may be encrypted using an encryption key prior to being written to the external storage. The interface unit may include a direct memory access controller. The external memory and the external storage can be a same non-volatile memory, namely a Flash device. | 02-16-2012 |
| 20120036372 | Conditional Access Integration in a SOC for Mobile TV Applications - An integrated circuit (IC) includes a demodulator for receiving encrypted information data and a hardware unit that enables conditional access to the information data. The hardware unit includes a processing unit, a RAM, a ROM, multiple non-volatile registers, and an interface unit for transferring an attribute to the demodulator. The non-volatile registers may include an IC identification and an encryption key. In an embodiment, the ROM includes a boot code that causes the processing unit to fetch a code from an external memory and store the fetched code in the RAM. The fetched code may include a certificate that ensures the authenticity of the code. The fetched code may be encrypted and decrypted by the ROM using the IC identification and the encryption key. The demodulator includes a descrambler for decrypting the received information data using the attribute. The information data may include digital radio or television content. | 02-09-2012 |
| 20120025904 | AREA-OPTIMIZED ANALOG FILTER WITH BANDWIDTH CONTROL BY A QUANTIZED SCALING FUNCTION - A programmable active frequency-selective circuit includes a first capacitor having a fixed value and a second capacitor having a value defined by a product of a parameter and a plurality of switchable capacitors, wherein the parameter is defined by a gain, a bandwidth mode, and a process resolution. The parameter may be stored in a form of a look-up table and enables a user or manufacturer to program the gain, select the bandwidth mode and tune the process. The frequency-selective circuit may include a differential input and a differential output having a first feedback path connected across a positive output terminal to a negative input terminal and a second feedback path connected across a negative output terminal and a positive input terminal. | 02-02-2012 |
| 20120002767 | FAST RESYNCHRONIZATION FOR RECEPTION IN TIME SLICING - A method and an apparatus for achieving fast resynchronization of received signals in a time slice in DVB-T/H systems. When the clock drift is low, the location of the symbol window can be decided based on a previous time slice. When the clock drift is high and when there are large delay spreads, the location of the symbol window can be decided based on the detected scattered pilot positions. The placement of the symbol window can further be enhanced through processing of the received TPS bits. | 01-05-2012 |
| 20120001797 | GNSS RECEPTION USING DISTRIBUTED TIME SYNCHRONIZATION - A GNSS receiver communicates with any connectivity device, such as a WiFi device that is, in turn, in communication with a wired network having access to the DTI timing. Such connectivity devices may set their timing and frame synchronization to the DTI and thus serve as Geopositiong beacons, thereby enabling the GNSS receiver to accurately determine its position. The GNSS receiver may also use the DTI timing supplied by such a network to perform relatively long integration time so as to achieve substantially improved sensitivity that is necessary for indoor Geopositioning applications. Furthermore, the GNSS data, such as satellite orbital information, may also be propagated by such devices at high speed. By providing this data to the GNSS receivers via such connectivity devices in a rapid fashion, the GNSS receivers are enabled to receive the transmitted data associated with the satellite without waiting for the GNSS transmission from the satellites. | 01-05-2012 |
| 20110310948 | LOW-COMPLEXITY DIVERSITY USING PREEQUALIZATION - A diversity receiver includes a first RF front end module for receiving a first RF signal, and frequency converting the first RF signal and outputting a first diversity signal, a second RF front end module for receiving a second RF signal, frequency converting the second RF signal and outputting a second diversity signal, a first converter for converting the first diversity signal to a first time-domain signal, a second converter for converting the second diversity signal to a second time-domain signal, a first transformer for translating the first time-domain signal to a first frequency-domain signal, a second transformer for translating the second time-domain signal to a second frequency-domain signal, a first pre-equalizer for equalizing the first frequency-domain signal, a second pre-equalizer for equalizing the second frequency-domain signal, and a combiner for combining the first and second pre-equalized frequency-domain signals. The diversity receiver further includes a channel estimator having a mirror window. | 12-22-2011 |
| 20110309976 | INTERMITTENT TRACKING FOR GNSS - A GNSS system operates intermittently and has adaptive activity and sleep time in order to reduce power consumption. The GNSS system provides an enhanced estimate of its position in the absence of GNSS signals of sufficient strength. The user's activity and behavior is modeled and used to improve performance, response time, and power consumption of the GNSS system. The user model is based, in part, on the received GNSS signals, a history of the user's positions, velocity, time, and inputs from other sensors disposed in the GNSS system, as well as data related to the network. During each activity time, the GNSS receiver performs either tracking, or acquisition followed by tracking. The GNSS receiver supports both normal acquisition as well as low-power acquisition. | 12-22-2011 |
| 20110294448 | ANALOG FRONT END CIRCUIT FOR CABLE AND WIRELESS SYSTEMS - A circuit includes, an attenuator responsive to an input signal and a feedback signal, a variable gain low-noise amplifier responsive to the attenuator and to the feedback signal, a tracking filter, a frequency converter, and an RSSI responsive to the variable gain amplifier to generate an output signal to which the feedback signal is responsive. The frequency converter may be a mixer having a single-ended input and a differential output. The circuit may further include an analog baseband block responsive to the mixer to filter out high frequency signals. The tracking tuner performs bandpass filtering operation on the output signals of the variable gain low-noise amplifier. | 12-01-2011 |
| 20110291882 | CO-OPERATIVE GEOLOCATION - A method and apparatus for extending the coverage of geolocation to indoor locations through cooperative geolocation. The method includes establishing an ad-hoc wireless network comprising a plurality of devices including a first device. The method includes receiving, at the first device, position information from the plurality of devices and determining a physical location of the first device based on the received position information. In an embodiment, the position information is transmitted in response to a request by the first device. In an embodiment, the position information may include a time of arrival of the request received by each of the plurality of devices; and the time of arrival may be associated with a GNSS time. In an embodiment, the ad-hoc wireless network may be a Wi-Fi network, which is associated with one of the IEEE 802.11 standards. | 12-01-2011 |
| 20110287725 | DIVERSITY BLOCKER PROTECTION - A transmitting/receiving circuit includes, in part, at least one transceiver, and at least two receiving channels forming a diversity receiver. One of the receiving channels includes, in part, a saw filter, an amplifier, and a frequency converter. The other receiving channel includes, in part, an amplifier, a frequency converter, and a received signal strength indicator (RSSI) adapted to detect signals transmitted by the transceiver. The RSSI is optionally coupled to an input terminal of its associated amplifier. The receiver further includes, in part, at least one processor operative to combine signals processed through the first and second receiving channels using a weight the processor assigns to the signal received by the second receiving channel in accordance with a strength of the blocker signal that the RSSI detects. The second receiving channel optionally includes an RSSI. | 11-24-2011 |
| 20110286561 | CLOCK-OUT AMPLITUDE CALIBRATION SCHEME TO ENSURE SINE-WAVE CLOCK-OUT SIGNAL - A clock generator includes, in part, a buffer, a peak detector and a control logic. The buffer generates a clock output signal in response to receiving a clock signal and a feedback signal that controls the gain of the buffer. If the peak detector detects that the amplitude of the output signal is higher than the upper bound of the predefined range, the gain value applied to the variable buffer is decreased. If the peak detector detects that the amplitude of the output signal is lower than the lower bound of the predefined range, the gain value applied to the variable buffer to increased. If the peak detector detects that the amplitude of the output signal is within the predefined range, no change is made to the gain value applied to the variable buffer. The control logic generates the feedback signal in response to the peak detector's output signal. | 11-24-2011 |
| 20110285912 | Integrated IF SAW Filter in Baseband Digital Design for Analog TV (or Hybrid) Tuner - A filter for processing a digital TV composite signal having a video component and an audio component includes a digital video filter and a digital audio filter. The digital video filter includes a lowpass finite impulse response (FIR) filter, an up-mixer, an asymmetric filter for compensating a Nyquist slope of the video component, and a down-mixer connected in this order. The digital audio filter includes an audio down-mixer, a decimated FIR filter, an enhancing FIR filter, an interpolated FIR filter, and an audio up-mixer. These components are connected in series. Optionally, the decimating FIR filter is decimated by an integer decimation factor M, and the interpolated FIR filter is interpolated by an integer factor N. The integer M and N may have the same value. | 11-24-2011 |
| 20110281542 | CRYSTAL CONTROL SCHEME TO IMPROVE PERFORMANCE OF A RECEIVER - A circuit includes, in part, a receiver, a received signal strength indicator (RSSI), and an oscillator. The receiver receives an incoming signal and an oscillating signal. The RSSI is responsive to the receiver and generates an output signal representative of the strength of the incoming signal. The oscillator receives different biasing conditions in response to different outputs of the RSSI. The oscillator generates the oscillating signal received by the receiver. The oscillator receives a first biasing condition when the incoming signal is detected as having a strength lower than or equal to a predetermined threshold value and a second biasing condition when the incoming signal is detected as having a strength higher than the predetermined threshold value. The first biasing condition may be defined by a first current, and the second biasing condition may be defined by a sum of the first current and a second current. | 11-17-2011 |
| 20110280344 | DYNAMIC BANDWIDTH CONTROL SCHEME OF A FRAC-N PLL IN A RECEIVER - A receiver, in accordance with one embodiment of the present invention, includes a mixer, a filter, a received signal strength indicator, and a control loop. The mixer is adapted to convert the frequency of a received signal. The filter is adapted to filter out undesired noise that may be present in the output signal of the mixer. The received signal strength indicator is adapted to detect blocker (also known as jammer) signals that may be present in the output signal of the low-pass filter and generate a feedback signal in response. The control loop is adapted to vary its bandwidth in response to an output signal of the received signal strength indicator. The control loop supplies an oscillating signal to the mixer. | 11-17-2011 |
| 20110264721 | SIGNAL PROCESSING BLOCK FOR A RECEIVER IN WIRELESS COMMUNICATION - A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented ( | 10-27-2011 |
| 20110227614 | TCXO Replacement for GPS - To determine the level of frequency drift of a crystal oscillator as a result of a change in the its temperature, the temperature of the crystal oscillator is sensed and used together with previously stored data that includes a multitude of drift values of the frequency of the crystal oscillator each associated with a temperature of the crystal oscillator. Optionally, upon initialization of a GPS receiver in which the crystal oscillator is disposed, an initial temperature of the crystal oscillator is measured and a PLL is set to an initial frequency in association with the initial temperature. When acquisition fails in a region, the ppm region is changed. The temperature of the crystal oscillator is periodically measured and compared with the initial temperature, and the acquisition process is reset if there is a significant change in temperature. The GPS processor enters the tracking phase when acquisition is successful. | 09-22-2011 |
| 20110222633 | HIGH DYNAMIC RANGE RADIO ARCHITECTURE WITH ENHANCED IMAGE REJECTION - A circuit for down-converting an RF signal to a baseband signal includes a trans-admittance amplifier adapted to receive the RF signal and generate in response a pair of differential current signals. The circuit further includes a trans-impedance amplifier having at least four mixers and at least four linear amplifiers. The four mixers frequency down-convert the pair of differential current signals to generate four pairs of differential baseband current signals, wherein each pair of the differential baseband current signals has a different phase and is associated with each of the linear amplifiers. Additionally, the circuit includes a summing block that generates an in-phase signal using a first weighted sum of the four different baseband current signals and a quadrature signal using a second weighted sum of the four different baseband current signals. The circuit further includes an analog-to-digital converter for converting the in-phase and quadrature signals to respective digital representations. | 09-15-2011 |
| 20110170587 | EDGE EQUALIZER - To compensate for roll-off while estimating a communication channel, an estimate of the channel is provided using a signal transmitted via the communication channel. The pilot tones positioned along the edges of the estimated channel are divided by the corresponding pilot tones of the received signal to generate a first number of ratios. An algorithm is thereafter applied to the first number of ratios to generate a second number of ratios associated with the non-pilot tones positioned along the edges of the estimated channel. Next, numbers that are inverse of the first and second number of ratios are applied to the pilot and non-pilot tones positioned along the edges of the estimated channel to compensate for the roll-offs in the estimated channel. | 07-14-2011 |
| 20110169697 | GPS-ASSISTED SOURCE AND RECEIVER LOCATION ESTIMATION - A mobile communication device includes, in part, a first wireless receiver adapted to determine, as it travels along a path, a multitude of positions of the mobile communication device using signals received from a primary positioning source, a second wireless receiver adapted to receive signals from one or more ambient wireless sources as the mobile communication device travels along the path, and a positioning module. An internal or external memory stores estimated positions and corresponding time references of the signals of the one or more ambient sources. The positioning module uses the data stored in the database to estimate the position of the mobile communication device when no primary positioning source signal is available. The positioning module optionally uses the data stored in the database to improve estimates of the position of the mobile communication device when primary positioning signal is available. | 07-14-2011 |
| 20110164690 | METHODS AND SYSTEMS FOR LOCATION ESTIMATION - A receiver system and method for determining the location of a device in a wireless network having a plurality of transmitters is provided. The method includes receiving a signal at the device, transforming the received signal into a time-domain signal having a characteristic, and computing a range of the device from each of the plurality of transmitters based on the characteristic. Additionally, the method includes determining the location of the device based on the computed ranges. In certain embodiments, the characteristic may be a time of arrival, time difference of arrival, or a signal strength, and the wireless network is a DTV broadcasting network. | 07-07-2011 |
| 20110105068 | WIDEBAND TUNER ARCHITECTURE - A wideband receiver system is provided to concurrently receive multiple RF channels including a number of desired channels that are located in non-contiguous portions of a radio frequency spectrum and to group the number of desired channels into a contiguous frequency band. The system includes a wideband receiver having a complex mixer for down-shifting the multiple RF channels and transforming them to an in-phase signal and a quadrature signal in the baseband. The system further includes a wideband analog-to-digital converter module that digitizes the in-phase and quadrature signals and a digital frontend module that transforms the digital in-phase and quadrature signals to baseband signals that contains only the number of desired RF channels. that are now located in a contiguous frequency band. An up-converter module up-shifts the baseband signals to a contiguous band in an IF spectrum so that the system can directly interface with commercially available demodulators. | 05-05-2011 |
| 20110102257 | GPS BASEBAND CONTROLLER ARCHITECTURE - A GPS receiver includes an RF front end for acquiring and tracking a satellite signal and a baseband processor configured to preserve power. The baseband processor includes a GPS engine configured to process the satellite signal and generate a PVT fix, a power supervisory module for receiving the PVT fix, and a user state module that determines an environmental state, wherein the power supervisory module may power down the GPS receiver for a period of time based on a result of the determined environment state. The baseband processor also includes a time-based management module that adjusts the TCXO in response to the determined environmental state. The GPS receiver includes a plurality of operation modes, each of which is associated with a plurality of tracking profiles. | 05-05-2011 |
| 20110096874 | WIDEBAND PERSONAL-RADIO RECORDER - Methods and apparatuses for concurrently recording multiple radio channels. A recorder includes a wideband tuner having a complex mixer for converting a received wideband RF signal to a complex signal that is then digitized. A digital front end module applies a number of complex down-mixers to the digital complex signal to generate the multiple radio channels in the baseband. Each one of the multiple radio channels in the baseband is further filtered, decimated and demodulated. A digital signal processing unit encodes each demodulated channel according to an audio compression format and stores the then encoded audio content to a storage unit. An RBDS decoder parses radio data service information associated with the stored audio content. The radio data service information is stored in a first section of the storage unit while the encoded audio content is stored in a second section of the storage unit. | 04-28-2011 |
| 20110096864 | PROGRAMMABLE DIGITAL CLOCK CONTROL SCHEME TO MINIMIZE SPUR EFFECT ON A RECEIVER - A device includes an analog front end for receiving a radio frequency (RF) signal. The analog front end contains a local oscillator that is tuned to a local oscillation frequency for down-converting the received RF signal to a first intermediate frequency (IF) signal. An analog-to-digital converter module converts the first IF signal to a digital baseband signal. The device also includes a digital processing unit for processing the baseband signal. The digital processing unit generates multiple clock signals from a reference oscillator having digitally adjustable reference frequency. The reference frequency and the multiple clock signals may interfere with the local oscillator and generate several frequency spurs that may fall within the bandwidth of the received RF signal. In a preferred embodiment, the digital processing unit adjusts the reference frequency by a certain amount so that the spurs do not fall within the RF signal bandwidth. | 04-28-2011 |
| 20110090971 | DOPPLER ESTIMATOR FOR OFDM SYSTEMS - A method of estimating the Doppler spread of a communication channel includes computing a first sum defined by a difference between the pilot tones of a first group of N symbols and a corresponding pilot tones of a second group of N symbols preceding the first group of N symbols, computing a second sum defined by the pilot tones of the second group of N symbols, and computing a ratio of the first sum and the second sum for each of the N symbols of the first and second group of symbols to generate N ratios representative of the Doppler spread of the channel. The first sum is further defined by the square of the difference between the pilot tones of the first group of N symbols and the corresponding pilot tones of the second group of N symbols. | 04-21-2011 |
| 20110081877 | DUAL CONVERSION RECEIVER WITH PROGRAMMABLE INTERMEDIATE FREQUENCY AND CHANNEL SELECTION - A dual conversion receiver architecture that converts a radio frequency signal to produce a programmable intermediate frequency whose channel bandwidth and frequency can be changed using variable low-pass filtering to accommodate multiple standards for television and other wireless standards. The dual conversion receiver uses a two stage frequency translation and continual DC offset removal. The dual conversion receiver can be completely implemented on an integrated circuit with no external adjustments. | 04-07-2011 |
| 20110009080 | RECEIVER ARCHITECTURE WITH DIGITALLY GENERATED INTERMEDIATE FREQUENCY - A receiver can be configured to include an RF front end that is configured to downconvert a received signal to a baseband signal or a low Intermediate Frequency (IF) signal. The receiver can downconvert the desired signal from an RF frequency in the presence of numerous interference sources to a baseband or low IF signal for filtering and channel selection. The filtered baseband or low IF signal can be converted to a digital representation. The digital representation of the signal can be upconverted in the digital domain to a programmable IF frequency. The digital IF signal can be converted to an analog IF signal that can be processed by legacy hardware. | 01-13-2011 |
| 20100271558 | HYBRID RECEIVER ARCHITECTURE USING UPCONVERSION FOLLOWED BY DIRECT DOWNCONVERSION - A receiver configured to selectively receive an RF signal from an operating band having a plurality of RF channels. The receiver is configured to upconvert the desired RF channel to an intermediate frequency (IF) greater than the RF channel frequencies. The upconverted RF channel is downconverted to baseband or a low IF. The receiver can perform channel selection by filtering the baseband or low IF signal. The baseband or low IF signal can be upconverted to a programmable output IF. | 10-28-2010 |
| 20100003943 | Harmonic Reject Receiver Architecture and Mixer - Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection. | 01-07-2010 |
| 20090258625 | GAIN PARTITIONING IN A RECEIVER - An automatic gain control loop disposed in a receiver is adapted to compensate for varying levels of out of band interference sources by adaptively controlling the gain distribution throughout the receive signal path. One or more intermediate received signal strength indicator (RSSI) detectors are used to determine a corresponding intermediate signal level. The output of each RSSI detector is coupled to an associated comparator that compares the intermediate RSSI value against a corresponding threshold. The take over point (TOP) for gain stages is adjusted based in part on the comparator output values. The TOP for each of a plurality of gain stages may be adjusted in discrete steps or continuously. | 10-15-2009 |
| 20090252264 | LOW-COMPLEXITY DIGITAL RADIO INTERFACE - A radio integrated circuit includes, in part, an analog front end block, an analog-to-digital converter responsive to the analog-front end block, a digital signal processor responsive to the analog-to-digital converter and adapted to generate in-phase and quadrature signals, and a serial communication interface configured to receive and transmit the in-phase and quadrature signals. The serial communication interface supplies a gain control signal to the analog front end block when a switch disposed in the radio integrated circuit is in a first position. When the switch is in a second position, a gain control block disposed in the radio integrated circuit receives a gain control signal from the analog-to-digital converter and supplies the gain control signal to the analog front end block. The digital signal processor may be configured to interleave the in-phase and quadrature signals. | 10-08-2009 |
| 20090098845 | METHOD AND APPARATUS FOR EFFICIENT DC CALIBRATION IN A DIRECT-CONVERSION SYSTEM WITH VARIABLE DC GAIN - A wireless communication receiver includes a multitude of look-up tables each storing a multitude of DC offset values associated with the gains of an amplification stage disposed in the wireless communication receiver. The entries for each look-up table are estimated during a stage of the calibration phase. During such a calibration stage, for each selected gain of an amplification stage, a search logic estimates a current DC offset number and compares it to a previous DC offset estimate that is fed back to the search logic. If the difference between the current and previous estimates is less than a predefined threshold value, the current estimate is treated as being associated with the DC offset of the selected gain of the amplification stage and is stored in the look-up table. This process is repeated for each selected gain of each amplification stage of interest until the look-up tables are populated. | 04-16-2009 |
| 20090098844 | LOW-COMPLEXITY DIVERSITY USING COARSE FFT AND SUBBAND-WISE COMBINING - A wireless diversity receiver includes, in part, N signal processing paths, a bin-wise combiner, and an inverse transformation module. Each signal processing path includes, in part, a mixer adapted to downconvert a frequency of an RF signal received by that path, an analog-to-digital converter adapted to convert the downconverted signal from an analog signal to a digital signal, and a transformation block adapted to transform the digital signal represented in time domain to an associated frequency domain signal having M subband signals. The bin-wise combiner is configured to combine the corresponding subband signals of the N paths. The inverse transformation block is configured to transform the output of the bin-wise combiner to an associated time-domain signal. | 04-16-2009 |
| 20090088120 | I/Q Calibration Techniques - A receiver includes a static I/Q calibration block and a correlation/integration block. The static I/Q calibration block is configured to substantially eliminate mismatches between in-phase and quadrature components of a portion of the spectrum having associated I/Q mismatches that are relatively frequency-independent. The correlation/integration block is configured to substantially eliminate mismatches between the in-phase and quadrature components of portions of the spectrum having associated I/Q mismatches that are relatively frequency-dependent in accordance with a pair of signals generated by the static I/C calibration block. | 04-02-2009 |
| 20090052541 | METHOD AND APPARATUS FOR PRESERVING DEINTERLEAVING ERASURE INFORMATION OF BLOCK INTERLEAVED CODED SIGNAL - Erasure information associated with a received group of encoded and interleaved data in a digital video broadcasting system is stored in a much compacted form. An erasure flag and an address of a last byte associated with the received group of encoded and interleaved data (a record) encapsulated in an MPE-FEC column will be stored in an erasure table. All bytes in the column preceding the last byte of the record will have the same erasure flag as the last byte. Erasure information deinterleaver | 02-26-2009 |
| 20090041115 | TS Packet Grooming - Received data packets are groomed to improve performance of MPEG-2 transport stream packet in a digital video broadcasting system. Multitude of crosschecking techniques are applied to ensure that crucial pieces of information such as the packet identifier (PID) field, the continuity counter (CC) field, table ID, section length, IP header checksum, table and frame boundaries, application data table size are corrected if necessary. | 02-12-2009 |
| 20090040391 | TUNER FOR CABLE, SATELLITE AND BROADCAST APPLICATIONS - A tuner includes, in part, one or mixers, one or more filters, one or more variable gain stages, one or more analog to digital converters, and a baseband processor. Each filter is responsive to an associated mixer's output signal. Each variable gain stage is responsive to an associated filter's output. Each analog-to-digital converter is adapted to convert the output signal of an associated variable gain stage to a digital signal. The baseband processor is responsive to the digital signal supplied by the analog-to-digital converter(s). The baseband processor is further configured to supply a signal to be demodulated by a processing unit external to the integrated circuit. The baseband processor performs no or a fraction of the required demodulation functions. The processing unit may be a central processing unit or a graphical processing unit. | 02-12-2009 |
| 20080209499 | CHANNEL CHANGE LATENCY REDUCTION - A wireless communication system is enhanced to allow for low-latency channel surfing and to enable a user to quickly see the content carried over a selected channel while searching channels for desired content. The techniques for reducing the channel change latency may be implemented in a transmitter, receiver, or in a combination of transmitter and receiver. The wireless communication system is optionally a DVB-H communication system. The transmitter may generate and transmit one or more auxiliary channels, where each auxiliary channel contains reduced resolution content corresponding to one or more channels. The receiver may process the one or more auxiliary channels to present the reduced resolution content while processing the full resolution channel for display. The receiver caches portions of content from one or more non-selected channels and presents the cached content when the channel is selected while concurrently searching and processing the full resolution channel content. | 08-28-2008 |
| 20080204143 | WIDE DYNAMIC RANGE AMPLIFIER GAIN CONTROL - Linear wide dynamic range variable gain amplifiers can be configured using a variable gain amplifier having an abbreviated gain control range in combination with a discrete attenuator controlled to select an attenuation from a predetermined set of attenuation values. The variable gain amplifier is configured to provide substantially linear gain control over the abbreviated gain control range, where the abbreviated gain control range is less than a total desired gain control range. The difference between adjacent attenuation values in the set of attenuation values is configured to be approximately less than or equal to the abbreviated gain control range. | 08-28-2008 |
| 20080198942 | LONG ECHO DETECTION AND CHANNEL ESTIMATION FOR OFDM SYSTEMS - A method and an apparatus are provided in an OFDM receiver for detecting and compensating for long echo. The method comprises a first pilot tone interpolation mechanism and a first window placement to filter a received OFDM symbol, a long echo channel detection coupled with a second pilot tone interpolation mechanism, a pre-echo and post-echo detection wherein the pre-echo condition is associated with a second new window placement, and both pre-echo and post-echo conditions place two time windows around a first peak channel response and a second peak channel response for channel estimation. The long echo is estimated by obtaining power spectra of a subset of subcarriers in one OFDM symbol, performing an inverse Fourier transform on the power spectra and determining the long echo by measuring the time between two peaks in the power profile. | 08-21-2008 |
