| MAXIM INTEGRATED PRODUCTS, INC. Patent applications |
| Patent application number | Title | Published |
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| 20120114033 | USING MULTI-LEVEL PULSE WIDTH MODULATED SIGNAL FOR REAL TIME NOISE CANCELLATION - A mixed signal processing circuit includes an analog to PWM converting circuit and a finite impulse response (FIR) filter having a multiple output tapped delay line and a summing and integration circuit. The mixed signal processing circuit converts an input analog signal to a PWM signal, forms a multi-level PWM signal from the PWM signal and one or more delayed versions of the PWM signal, and converts the multi-level PWM signal to an output analog signal. The analog to PWM converting circuit is implemented using a triangle waveform generator and a comparator. The FIR filter is implement using a resistive network to apply scaling coefficients of the FIR filter. The mixed signal processing circuit can be implemented within a noise cancellation headphone to generate a noise cancelling signal or generally in applications that would be benefitted from the combination of analog input/output and digital filter techniques. | 05-10-2012 |
| 20120106953 | Dual Laser-Power-Level Control and Calibration System for Burst-Mode and Continuous-Mode Transmitter - Dual laser-power-level control and calibration system for burst-mode and continuous-mode transmitter. A first signal path receives a transmit signal that also drives the transmit laser, and a second signal path receives the output of a monitor diode. The first and second signal paths include filtering so that the two signal paths have a similar frequency response. The upper and lower excursions in both signal paths are compared, and the power levels of the optical transmitter are adjusted based on those comparisons. Embodiments with one control loop and two control loops are disclosed. | 05-03-2012 |
| 20120081125 | Integrated MOSFET Current Sensing for Fuel-Gauging - Integrated MOSFET current sensing for fuel-gauging. A | 04-05-2012 |
| 20120081095 | SYSTEMS AND METHODS FOR CONTROLLING INDUCTIVE ENERGY IN DC-DC CONVERTERS - A DC-DC converter comprises a high-side switch, a low-side switch connected to the high-side switch, and an output capacitance. An inductance has one end connected to the high-side switch and the low-side switch and another end connected to the output capacitance. A shunting device circulates current flowing through the inductance back to the inductance during a load reduction transition to control a voltage across the output capacitance. | 04-05-2012 |
| 20120078546 | LOAD-SIDE VOLTAGE DETECTION VIA ELECTRIC METERING PROCESSING - Load-side voltage detection via electric metering processing is disclosed. In one aspect, load-side voltage is provided as an input to a metering processing unit. The metering processing unit determines a voltage level of the load-side voltage. An application processing unit uses the voltage level to control operation of a service disconnect relay. | 03-29-2012 |
| 20120039376 | Systems And Methods For Digital Control Utilizing Oversampling - Methods and systems for digital control utilizing oversampling. | 02-16-2012 |
| 20120032352 | SIDE WETTABLE PLATING FOR SEMICONDUCTOR CHIP PACKAGE - A method for providing a semiconductor chip package with side wettable plating includes singulating a semiconductor chip package from an array of packages formed in a block format, immersing the semiconductor chip package in a bath of plating solution, contacting a lead land of the semiconductor chip package with conductive contact material within the bath of plating solution, connecting the conductive contact material to a cathode electrical potential, connecting an anode within the bath of plating solution to an anode electrical potential, and plating the lead land of the semiconductor chip package. | 02-09-2012 |
| 20120018827 | MULTI-SENSOR INTEGRATED CIRCUIT DEVICE - A multiple sensor-types integrated circuit device includes a semiconductor die including a first sensor type and a second sensor type formed thereon, an electrically insulating package enclosing the semiconductor die and a plurality of electrically conductive leads coupled to the semiconductor die and extending from the package. By way of example and not limitation, a multiple sensor-types integrated circuit die includes a semiconductor substrate of a first polarity, a plurality of regions of the first polarity formed in the substrate, where the plurality of regions are relatively more heavily doped than the substrate, multiple wells formed in the substrate, and a covering layer formed over the substrate. | 01-26-2012 |
| 20120018288 | KEYPAD HAVING TAMPER-RESISTANT KEYS - A tamper resistant keypad includes one or more key assemblies having a resilient key member and a contact. The resilient key member is configured to flex when the key assembly is depressed to allow the contact to close a key press detection circuit on a circuit board to register a key press. A tamper detection switch assembly at least partially surrounds the resilient key member. The tamper detection switch assembly is configured to detect attempts to access the key assembly. | 01-26-2012 |
| 20110320157 | SELF-CORRECTING ELECTRONIC SENSOR - A temperature sensing circuit is described providing a low power temperature sensing system. The temperature sensing circuit provides a digital method for determining the temperature by analyzing the change in electrical response characteristics of a circuit device. | 12-29-2011 |
| 20110317385 | WAFER LEVEL PACKAGE (WLP) DEVICE HAVING BUMP ASSEMBLIES INCLUDING A BARRIER METAL - WLP semiconductor devices include bump assemblies that have a barrier layer for inhibiting electromigration within the bump assemblies. In an implementation, the bump assemblies include copper posts formed on the integrated circuit chips of the WLP devices. Barrier layers formed of a metal such as nickel (Ni) are provided on the outer surface of the copper posts to inhibit electromigration in the bump assembly. Oxidation prevention caps formed of a metal such as tin (Sn) are provided over the barrier layer. Solder bumps are formed over the oxidation prevention caps. The oxidation prevention caps inhibit oxidation of the barrier layer during fabrication of the bump assemblies. | 12-29-2011 |
| 20110300668 | USE OF DEVICE ASSEMBLY FOR A GENERALIZATION OF THREE-DIMENSIONAL METAL INTERCONNECT TECHNOLOGIES - An assembly process properly positions and align a plurality of first die within a carrier substrate. The first die are positioned within cavities formed in the carrier substrate. The carrier substrate is then aligned with a second substrate having a plurality of second die fabricated therein. The first die and the second die are fabricated using different technologies. Aligning the carrier substrate and the second substrate aligns the first die with the second die. One or more first die can be aligned with each second die. Once aligned, a wafer bonding process is performed to bond the first die to the second die. In some cases, the carrier substrate is removed, leaving behind the first die bonded to the second die of the second substrate. In other cases, the carrier substrate is left in place as a cap. The second substrate is then cut to form die stacks. | 12-08-2011 |
| 20110299688 | HIGH SPEED DIGITAL TO ANALOG CONVERTER WITH REDUCED SPURIOUS OUTPUTS - A system includes a first circuit including a scrambling module that receives N digital data streams and that scrambles the N digital data streams using a scrambling sequence. A data bus receives the N scrambled digital data streams and the scrambling sequence. A second circuit communicates with the data bus and includes a first processing module that processes the N scrambled digital data streams and that outputs M digital data streams, where M and N are integers greater than one. The second circuit includes one or more descrambling and processing modules that receive the M digital data streams, that descramble the M digital data streams based on the scrambling sequence, and that further process the M digital data streams. The second circuit includes a digital to analog converter (DAC) module that receives an output of the one or more descrambling and processing modules. | 12-08-2011 |
| 20110299207 | HIGH SPEED DIGITAL-TO-ANALOG CONVERTER WITH LOW VOLTAGE DEVICE PROTECTION - A digital-to-analog converter (DAC) includes a first DAC core, a second DAC core, and a butterfly switch. The first DAC core generates a first output. The second DAC core generates a second output. The butterfly switch includes at least one of switch transistors and cascode transistors. The butterfly switch selectively connects the first output and the second output to an output stage of the DAC. | 12-08-2011 |
| 20110298645 | Shared Operational Transconductance Amplifier Pipelined ADC Incorporating a Sample/Hold Amplifier and Multiple MDAC Stages - A single operational transconductance pipelined ADC incorporating a sample/hold amplifier and multiple MDAC stages. An input signal is sampled on input signal sampling capacitors, and then coupled around an operational transconductance amplifier (OTA) so that the output of the OTA is equal to the sampled voltage. There is no net charge transfer in this operation, so the noise and power dissipation normally associated with an input sample and hold circuitry (SHA) in a pipelined ADC is substantially eliminated. A pipelined ADC using a shared OTA for sample/hold and two MDACs is disclosed. | 12-08-2011 |
| 20110298508 | DATA INTERFACE WITH DELAY LOCKED LOOP FOR HIGH SPEED DIGITAL TO ANALOG CONVERTERS AND ANALOG TO DIGITAL CONVERTERS - A system comprises a first circuit includes a data transmitter circuit that transmits digital data based on a first clock signal. A sync generator outputs a sync signal based on the first clock signal. A digital to analog converter circuit includes a data receiver circuit that latches the digital data based on a second clock signal. A digital to analog converter core receives an output of the data receiver circuit. A delay locked loop circuit determines a delay based on the second clock signal and the sync signal and outputs the first clock signal to the first circuit based on the second clock signal and the delay. | 12-08-2011 |
| 20110280109 | SYNCHRONIZATION OF A GENERATED CLOCK - A real time clock circuit is provided that has an onboard oscillator continuously providing an internal clock frequency, which is digitally synchronized to a more accurate reference clock frequency. An exemplary real time clock inhibits synchronization of the internal clock frequency when the reference clock is unavailable or if the reference clock's frequency is outside of a defined accuracy range. | 11-17-2011 |
| 20110261008 | USE OF RANDOM SAMPLING TECHNIQUE TO REDUCE FINGER-COUPLED NOISE - Random sampling techniques include techniques for reducing or eliminating errors in the output of capacitive sensor arrays such as touch panels. The channels of the touch panel are periodically sampled to determine the presence of one or more touch events. Each channel is individually sampled in a round robin fashion, referred to as a sampling cycle. During each sampling cycle, all channels are sampled once. Multiple sampling cycles are performed such that each channel is sampled multiple times. Random sampling techniques are used to sample each of the channels. One random sampling technique randomizes a starting channel in each sampling cycle. Another random sampling technique randomizes the selection of all channels in each sampling cycle. Yet another random sampling technique randomizes the sampling cycle delay period between each sampling cycle. Still another random sampling technique randomizes the channel delay period between sampling each channel. | 10-27-2011 |
| 20110261007 | NOISE CANCELLATION TECHNIQUE FOR CAPACITIVE TOUCHSCREEN CONTROLLER USING DIFFERENTIAL SENSING - A differential sensing scheme provides a means for detecting one or more touch events on a touch sensitive device in the presence of incident noise. Instead of sensing one touch sensitive channel, such as a row, column, or single touch sensor, multiple touch sensitive channels are sampled at a time. By sampling two nearby channels simultaneously and doing the measurement differentially, noise common to both channels is cancelled. The differential sensing scheme is implemented using simple switch-capacitor AFE circuitry. The originally sensed data on each individual channel is recovered free of common-mode noise. The recovered sensed data is used to determine the presence of one or more touch events and if present the location of each touch event on the touch sensitive device. | 10-27-2011 |
| 20110261006 | SYSTEM FOR AND METHOD OF TRANSFERRING CHARGE TO CONVERT CAPACITANCE TO VOLTAGE FOR TOUCHSCREEN CONTROLLERS - A touchscreen controller system determines the actual locations of multiple simultaneous touches by eliminating mutual capacitance between adjacent rows and columns during self-capacitance measurements and selectively enabling mutual capacitance during mutual capacitance measurements. During the self-capacitance measurements, the controller system generates a set of candidate touch locations, which includes the locations of real and ghost touches. During the mutual capacitance measurements, only the locations in the candidate set are measured and, from these measurements, the actual touch locations are determined. By limiting the mutual capacitive measurements to only a small subset of the locations over the entire touch panel, real touch locations are determined on a linear order. Also, by using on-chip integration capacitors, embodiments of the invention are able to perform each measurement in a single cycle. | 10-27-2011 |
| 20110261005 | METHOD AND APPARATUS FOR IMPROVING DYNAMIC RANGE OF A TOUCHSCREEN CONTROLLER - A touchscreen system for increasing the dynamic range of the system comprising a touchscreen coupled to an offset cancellation element and a capacitance measuring element. The offset cancellation element is configured to be dynamically changed in capacitance such that it offsets parasitic and sensor capacitances of the touchscreen sensors thereby leaving only touch event capacitance to be measured by the measuring element. The offset cancellation element is able to adjust to the initial unwanted capacitances of each sensor as well as dynamically adjust to changes in the unwanted capacitance due to the environment. In some embodiments, the offset cancellation element is a capacitance digital-to-analog converter that is controlled by a controller for offsetting the unwanted capacitance. As a result, the touchscreen system is able to utilize a small integrating capacitor thereby lowering cost and improving the dynamic range of the system. | 10-27-2011 |
| 20110260990 | SYSTEM INTEGRATION OF TACTILE FEEDBACK AND TOUCHSCREEN CONTROLLER FOR NEAR-ZERO LATENCY HAPTICS PLAYOUT - A haptic feedback system includes a user interface device, such as a touchscreen that includes a touch panel and one or more haptic drive elements coupled to the touch panel, a touch controller, and an actuator controller. The touch controller receives sensed data from the touch panel, and in response generates and sends a haptic signal to an actuator controller. Generation and transmission of the haptic signal bypasses any system host controller. A dedicated signal path couples the touch controller and the actuator controller, over which the haptic signal is transmitted. Alternatively, the haptic signal is transmitted from the touch controller to the actuator controller over a serial bus interface. In response to the received haptic signal, the actuator controller implements an appropriate drive signal in the form of a haptic waveform to the one or more haptic drive elements of the touchscreen. | 10-27-2011 |
| 20110248398 | WAFER-LEVEL CHIP-SCALE PACKAGE DEVICE HAVING BUMP ASSEMBLIES CONFIGURED TO MITIGATE FAILURES DUE TO STRESS - Wafer-level chip-scale package semiconductor devices are described that have bump assemblies configured to mitigate solder bump failures due to stresses, particularly stresses caused by CTE mismatch during thermal cycling tests, dynamic deformation during drop tests or cyclic bending tests, and so on. In an implementation, the wafer-level chip-scale package devices include an integrated circuit chip having two or more arrays of bump assemblies for mounting the device to a printed circuit board. At least one of the arrays includes bump assemblies that are configured to withstand higher levels of stress than the bump assemblies of the remaining arrays. | 10-13-2011 |
| 20110241646 | Low Noise Bandgap References - Low noise bandgap voltage references using a cascaded sum of bipolar transistor cross coupled loops. These loops are designed to provide the total PTAT voltage necessary for one and two bandgap voltage references. The PTAT voltage noise is the square root of the sum of the squares of the noise voltage of each transistor in the loops. The total noise of the reference can be much lower than approaches using two or 4 bipolar devices to get a PTAT voltage and then gaining this PTAT voltage to the required total PTAT voltage. The cross coupled loops also reject noise in the current that bias them. Alternate embodiments are disclosed. | 10-06-2011 |
| 20110241625 | CIRCUIT TOPOLOGY FOR PULSED POWER ENERGY HARVESTING - An energy harvesting circuit harvests energy from a voltage source and charges a storage element with the harvested energy. The energy harvesting circuit includes an energy source, a storage capacitor to store energy output from the energy source, a power converter circuit, an energy storage element, and an enabling circuit. The enabling circuit turns the boost converter circuit on and off according to a monitored capacitance voltage of the storage capacitor. When the boost converter circuit is turned off, the storage capacitor accumulates energy output from the energy source until a reference voltage is reached, whereupon the boost converter circuit is turned on, enabling current flow from the storage capacitor to the storage element. When the storage capacitor discharges to a minimum voltage level, the boost converter circuit is turned off. The enabling circuit and a reference voltage supply are powered by the energy source. | 10-06-2011 |
| 20110233756 | WAFER LEVEL PACKAGING WITH HEAT DISSIPATION - A heat dissipating wafer level package and method for manufacturing a heat dissipating wafer level package is provided. The heat dissipating wafer level package has a thermally conductive coating integrated thereon which facilitates the dissipation of heat from a device into the surrounding air and/or the thermal transfer of heat away from the device toward a heat spreader or heat sink. Additionally, the coating enhances the structural integrity and strength of the wafer during the manufacturing process as well as the resulting WLP. | 09-29-2011 |
| 20110227219 | ENHANCED WLP FOR SUPERIOR TEMP CYCLING, DROP TEST AND HIGH CURRENT APPLICATIONS - A WLP device is provided with a flange shaped UBM or an embedded partial solder ball UBM on top of a copper post style circuit connection. | 09-22-2011 |
| 20110227153 | Vertical Mosfet with Through-Body Via for Gate - In an embodiment, set forth by way of example and not limitation, a MOSFET power chip includes a first vertical MOSFET and a second vertical MOSFET. The first vertical MOSFET includes a semiconductor body having a first surface defining a source and a second surface defining a drain and a gate structure formed in the semiconductor body near the second surface. A via is formed within the semiconductor body and is substantially perpendicular to the first surface and the second surface. The via has a first end electrically coupled to the first surface and a second end electrically coupled to the gate structure. The second vertical MOSFET includes a semiconductor body having a first surface defining a source, a second surface defining a drain and a gate structure formed in the semiconductor body near the first surface. The first surface of the first vertical MOSFET and the second surface of the second vertical MOSFET are substantially co-planar and an electrically conductive can substantially surrounds the MOSFETS and shorts the first surface of the first vertical MOSFET to the second surface of the second vertical MOSFET. | 09-22-2011 |
| 20110221520 | SWITCHED CAPACITOR AMPLIFIER CIRCUIT WITH CLAMPING - A system comprises a switched capacitor amplifier including an operational amplifier (opamp). A switching circuit comprises a first switch connected across inputs of the opamp. A second switch is connected across outputs of the opamp. An overdrive detect circuit communicates with the first and second switches and selectively shorts the inputs and the outputs of the opamp when the input voltage is greater than a first predetermined overdrive voltage or when the input voltage is less than a second predetermined overdrive voltage. | 09-15-2011 |
| 20110204855 | CIRCUIT TOPOLOGY FOR REGULATING POWER FROM LOW CAPACITY BATTERY CELLS - A power circuit includes a voltage limited charge circuit and a linear regulator to supply high current pulses to a load while maintaining a regulated output and not discharging the battery below a predetermined level. The voltage limited charge circuit includes a low impedance transistor and an operational amplifier that are together configured as an active loop. The transistor functions as a switch, and the operational amplifier provides an adjustable control voltage that adjusts the impedance of the transistor according to current battery voltage and a minimum threshold voltage. Adjusting the impedance of the transistor enables the storage capacitor to charge very fast when the battery impedance is low, or very slow when the battery impedance is high. | 08-25-2011 |
| 20110198745 | WAFER-LEVEL PACKAGED DEVICE HAVING SELF-ASSEMBLED RESILIENT LEADS - A wafer-level packaged semiconductor device is described. In an implementation, the device includes one or more self-assembled resilient leads disposed on an integrated circuit chip. Each of the resilient leads are configured to move from a first position wherein the resilient lead is held adjacent to the chip and a second position wherein the resilient lead is extended away from the chip to interconnect the chip to a printed circuit board. A guard is provided to protect the resilient leads when the resilient leads are in the first position. One or more attachment bumps may also be furnished to facilitate attachment of the device to the printed circuit board. | 08-18-2011 |
| 20110181306 | ISOLATION MONITORING SYSTEM AND METHOD UTILIZING A VARIABLE EMULATED INDUCTANCE - A system for measuring leakage resistance between a high voltage (HV) system of a vehicle and a vehicle chassis includes an emulated inductance that is connected between the HV system and the vehicle chassis and that has an inductive reactance that substantially cancels a capacitive reactance between the HV system and the vehicle chassis. A signal source outputs one of an AC current signal and an AC voltage signal between the HV system and the vehicle chassis. A sensor measures one of an AC current response to the AC voltage signal between the HV system and the vehicle chassis and an AC voltage response to the AC current signal between the HV system and the vehicle chassis. | 07-28-2011 |
| 20110169509 | ELECTROSTATIC MEMS DRIVER WITH ON-CHIP CAPACITANCE MEASUREMENT FOR AUTOFOCUS APPLICATIONS - A driver and capacitance measuring circuit includes a voltage source that selectively generates an output voltage at a first node during a driver mode to alter a capacitance of a device that is connected to the first node and that has a variable capacitance. A current source selectively provides one of a charging and discharging current at the first node during a measurement mode. A capacitance calculating circuit samples a voltage at the first node during the measurement node, determines a voltage change rate of the first node during the measurement mode and calculates the capacitance of the device based on the voltage change rate and a value of the one of the charging and discharging current. | 07-14-2011 |
| 20110156809 | LOW DISTORTION MOS ATTENUATOR - An attenuation circuit uses a voltage controlled variable resistance transistor as a signal attenuator for receivers operating in the zero Hz to about 30 MHz range. The transistor functions in the linear region to linearize the transistor resistance characteristics used for signal attenuation. In an exemplary application, the attenuation circuit is used as an RF attenuator for AM radio broadcast receivers and amplifiers with automatic gain control. Multiple attenuation circuits can be coupled in parallel, each attenuation circuit having a different sized variable resistance transistor, to form sequentially activated stages that increase the range of attenuation while minimizing distortion. | 06-30-2011 |
| 20110149623 | ACTIVE PARASITE POWER CIRCUIT - A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal. | 06-23-2011 |
| 20110115019 | CMOS COMPATIBLE LOW GATE CHARGE LATERAL MOSFET - A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a switching gate positioned over a first portion of a channel region of the substrate, and a second portion forming a static gate formed over a second portion of the channel region and a transition region of the substrate. The static plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. A switching voltage is applied to the switching gate and a constant voltage is applied to the static gate. | 05-19-2011 |
| 20110115018 | MOS POWER TRANSISTOR - A split gate power transistor includes a laterally configured power MOSFET including a doped silicon substrate, a gate oxide layer formed on a surface of the substrate, and a split polysilicon layer formed over the gate oxide layer. The polysilicon layer is cut into two electrically isolated portions, a first portion forming a polysilicon gate positioned over a channel region of the substrate, and a second portion forming a polysilicon field plate formed over a portion of a transition region of the substrate. The field plate also extends over a drift region of the substrate, where the drift region is under a field oxide filled trench formed in the substrate. The field plate is electrically coupled to a source of the split gate power transistor. | 05-19-2011 |
| 20110109294 | METHOD FOR DETERMINING PRE-BIAS IN A SWITCH-MODE CONTROLLER - A switch-mode controller, buck converter or DC to DC step-down regulated voltage converter that senses an initial pre-bias voltage at initialization and adjust a duty cycle of the switching frequency to help minimize an output voltage transient at initialization or power-on reset. | 05-12-2011 |
| 20110108981 | REDISTRIBUTION LAYER ENHANCEMENT TO IMPROVE RELIABILITY OF WAFER LEVEL PACKAGING - An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP. | 05-12-2011 |
| 20110103427 | SYSTEM AND METHOD OF CONTROLLING MODULATION FREQUENCY OF SPREAD-SPECTRUM SIGNAL - An apparatus for generating a spread-spectrum signal based on an input signal whose frequency may vary substantially. The apparatus is particularly suited for controlling the frequency of the modulation in response to wide variations of the frequency of the input signal. This prevents the modulation frequency from deviating into an undesired frequency range which could cause adverse operational effects. The apparatus includes a detector adapted to generate a first signal related to the frequency of the input signal, a controller adapted to generate a second signal for controlling a frequency of a modulation signal based on the first signal, a modulation signal generator adapted to generate the modulation signal based on the second signal, and a spread-spectrum signal generator adapted to generate the spread-spectrum signal based on the modulation signal. | 05-05-2011 |
| 20110103404 | SYSTEM AND METHOD FOR TRANSMITTING AUDIO DATA OVER SERIAL LINK - System and method for transmitting video and audio data words via a serial data link. A transmitting device includes a first module for generating an audio data frame comprising an audio data word and a frame separation code; and a second module for generating high speed data frames each comprising at least a portion of a video data word and only a portion of the audio data frame, and for transmitting the high speed data frames via the serial data link. A receiving device includes a first module for forming the video data word from one or more high speed data frames, and a second module for forming the audio data frame from portions of high speed data frames. The second module may extract the audio data word from the audio data frame, and generate an audio clock based on a rate in which audio data words are received. | 05-05-2011 |
| 20110095395 | Inductors and Methods for Integrated Circuits - Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed. | 04-28-2011 |
| 20110090364 | Integrated Camera Image Signal Processor and Video Encoder - An apparatus including a first circuit and a second circuit. The first circuit may be configured to perform image signal processing using encoding related information. The second circuit may be configured to encode image data using image signal processing related information, wherein said first circuit is further configured to pass said image signal processing related information to said second circuit and said second circuit is further configured to pass said encoding related information to said first circuit. | 04-21-2011 |
| 20110084763 | DB-LINEAR PROCESS-INDEPENDENT VARIABLE GAIN AMPLIFIER - An amplifier is provided with continuously-variable analog control that exhibits a highly linear gain control curve in db/volts, while preserving high dynamic range, low third order distortion, and low noise. This amplifier has a control mechanism that preserves a varied linear or log linear curve over a wide range and is inherently insensitive to process variations thereby allowing more accurate gain control and higher signal fidelity for amplifying high dynamic range signals. | 04-14-2011 |
| 20110082955 | I2C/SMBus Ladders and Ladder Enabled ICs - I2C/SMBus ladders and ladder enabled ICs (devices) to enable daisy-chained I2C/SMBus communication. The devices are particularly useful in monitoring and/or servicing high-voltage battery stacks and other voltage stacks. The devices are powered from a respective voltage increment in the voltage stack, and include level shifting circuitry so as to be operative with an input voltage up to the breakdown voltage of the level shifting circuitry. Various features are disclosed, including but not limited to a unique data line drive, capacitive coupling between devices in a daisy chain with line clamps for circuitry protection and capacitive coupling charge wiping, and clock stretching to accommodate chain latency. | 04-07-2011 |
| 20110050278 | SYSTEM FOR AND METHOD OF VIRTUAL SIMULTANEOUS SAMPLING WITH A SINGLE ADC CORE - Voltage balancing in multi-cell battery packs is improved by estimating instantaneous voltages on the cells. In accordance with one embodiment, an apparatus for reading voltages from multiple voltage sources includes a first multiplexer coupled to multiple voltage sources and a controller. The controller is programmed to output from the first multiplexer a sequential pair of voltages read from each of the multiple voltage sources. The multiple sequential pairs of voltages all have a common midpoint in time. The multiple sequential pairs of voltages are all read within a small time window, such as 100 microseconds. In one embodiment, the multiple voltage sources are Li-ion or other high-voltage cells, though other types of cells can also be used. | 03-03-2011 |
| 20110044217 | SYSTEM AND METHOD FOR TRANSFERRING DATA OVER FULL-DUPLEX DIFFERENTIAL SERIAL LINK - A data transmission technique where high speed data is transmitted differentially in a forward channel by way of a serial link, and relatively low speed data is differentially modulated onto the forward channel signal for transmission in a reverse channel via the link. By utilizing differential modulation in both forward and reverse channels, the resulting signal has a common mode voltage that is substantially constant, resulting in low EMI. The spectral content of the signal associated with the high speed data may be substantially non-overlapping with the spectral content of the signal associated with the low speed data. This facilitates the recovery of the high speed data and low speed data with minimal interference. The differential signaling lends itself for communicating data via an inexpensive medium, such as twisted wire pair or parallel PCB traces. The data transmission technique applies to various communication network topologies: point-to-point, daisy-chain, and point-to-multiple points. | 02-24-2011 |
| 20110033977 | METHOD OF FORMING SOLDERABLE SIDE-SURFACE TERMINALS OF QUAD NO-LEAD FRAME (QFN) INTEGRATED CIRCUIT PACKAGES - A method of forming an integrated circuit (IC) package is disclosed comprising: (a) removing oxides from side surfaces of terminals of the IC package; (b) substantially covering an underside of the terminals of the IC package; and (c) forming a solder coating on the side surfaces of terminals of the IC packages while covering the underside of the terminals of the IC package. The solder coating on the side surfaces of the terminals protects the terminals from oxidation due to aging and subsequent processes. Additionally, the solder coating on the side surfaces of the terminals substantially improves the solderability of the IC package to printed circuit boards (PCBs) or other mountings. This further facilitates the inspection of the solder attachment using less expensive and complicated methods. | 02-10-2011 |
| 20110025395 | SYSTEM AND METHOD FOR COMPENSATING PULSE GENERATOR FOR PROCESS AND TEMPERATURE VARIATIONS - An apparatus for generating a pulse having a pulse width substantially independent of process variation in resistive and capacitive values. The apparatus includes a PTAT current source to generate a first current to charge a capacitor to produce a first voltage; a ΔVGS current source to generate a second current through a resistor to produce a second voltage V | 02-03-2011 |
| 20110012618 | METHOD AND APPARATUS FOR SENSING CAPACITANCE VALUE AND CONVERTING IT INTO DIGITAL FORMAT - A capacitive sensing system are configured to sense a capacitance value and convert the sensed capacitance value to a digital format. The capacitive sensing system provides good selectivity and immunity to noise and interference, which can be further enhanced by enabling spread spectrum excitation. In some embodiments, the capacitive sensing system utilizes a sinusoidal excitation signal that results in low electromagnetic emissions, limited to narrow frequency band. In some embodiments, the capacitive sensing system is configured to operate in a spread spectrum mode, in which the majority of the excitation signal power is carried in the assigned bandwidth. The excitation frequency and the bandwidth of the spread spectrum excitation signal are programmable in a wide range, which allows for avoiding frequency conflicts in the operating environment. | 01-20-2011 |
| 20100315572 | CIRCUIT TOPOLOGY FOR DRIVING HIGH-VOLTAGE LED SERIES CONNECTED STRINGS - A system for backlighting a display uses an open or closed loop and small components that are well suited to high-frequency applications. The system includes multiple LED strings, a high-voltage source, and a low-voltage regulator that has a polarity opposite to that of the high-voltage source. The high-voltage source and the low-voltage regulator provide voltage differences across the LED strings to illuminate them. In one embodiment, the high-voltage source is about 200 VDC, and the low-voltage regulator produces voltages between −2 VDC and −30 VDC. Many types of displays, such as those used on LCD televisions and LCD personal computers, can be backlit in accordance with the embodiments. | 12-16-2010 |
| 20100253310 | EFFICIENT POWER REGULATION FOR CLASS-E AMPLIFIERS - A power converter device and method are provided. The power converter device includes an input power source and an input inductor configured for coupling a power of the input power source to the device. A switch is configured to regulate a power of the input power source through the input inductor. A shunting diode is coupled between the switch and the input inductor. A resonant load is coupled with the input inductor. A switching element is coupled with the input inductor and the resonant load and configured to operate at a fixed frequency. The power converter device also includes a control circuit for modulating a frequency of the switch and a driving module for driving the switching element at the fixed frequency. In an exemplary embodiment, the power converter device is a Class-E amplifier. The fixed frequency is a frequency equal to a resonant frequency of the resonant load. In one embodiment, the power converter device is configured as an integrated circuit device. | 10-07-2010 |
| 20100225290 | CRITICAL CONDUCTION RESONANT TRANSITION BOOST POWER CIRCUIT - A boost regulator is provided that has increased efficiency. The increased efficiency is provided by incorporating a sensing circuit that senses when the current in the boost regulator's inductor is near zero or when the voltage at its switching node is near zero or virtual ground. A switching signal is provided to the boost regulator's switching transistor when the near zero current or voltage is sensed. Switching at the near zero current or voltage moment (the “critical conduction moment”) helps to eliminate or minimize the power loss associated with switching the transistor at a time other than during the critical conduction moment. | 09-09-2010 |
| 20100207635 | FAULT DETECTION METHOD FOR DETECTING LEAKAGE PATHS BETWEEN POWER SOURCES AND CHASSIS - A method of detecting a ground fault condition between a direct current power system and the chassis ground of an electric or hybrid-electric vehicle is provided. The method includes sequentially opening and closing a first switch connected between a positive node of the direct current power system and the chassis ground of the vehicle and a second switch connected between a negative node of direct current power system and the chassis ground. The sequential opening and closing of the first and second switches charges and discharges an inherent capacitance present between the metal components of the direct current power system and the chassis. First and second currents are created as the inherent capacitance is charged and discharged. Measurements of the created first and second currents are then used to determine whether a ground fault condition exists between the direct current power system and the vehicle chassis ground. | 08-19-2010 |
| 20100178747 | Minimum Cost Method for Forming High Density Passive Capacitors for Replacement of Discrete Board Capacitors Using a Minimum Cost 3D Wafer-to-Wafer Modular Integration Scheme - Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed. | 07-15-2010 |
| 20100149121 | SYSTEM AND METHOD FOR INTERFACING APPLICATIONS PROCESSOR TO TOUCHSCREEN DISPLAY FOR REDUCED DATA TRANSFER - System and method for substantially reducing an involvement of an applications processor in receiving data from a touchscreen display. In one aspect, the system includes a controller may be configured in an autonomous mode where it automatically measures the touchscreen display based configuration information received from the applications processor, determines notable events based on the measurement data, stores data and event identifiers related to the notable events in a memory, and sends a notification to the applications processor when event data is available In another aspect, the system includes a controller that filters user interactions events and transmits data related to only notable events to the applications processor. Because of the autonomous and event filtering operations of the touchscreen controller, there are substantially less communications between the controller and the applications processor. This improves the speed and efficiency of the applications processor. | 06-17-2010 |
| 20100123948 | Bragg Mirror and Method for Making Same - In an embodiment, set forth by way of example and not limitation, a Bragg mirror includes a first bi-layer of a first thickness and a second bi-layer of a second thickness which is different from the first thickness. In this exemplary embodiment, the first bi-layer consists essentially of a first high impedance layer and a first low impedance layer, and the second bi-layer of a second thickness which is different from the first thickness, the second bi-layer consisting essentially of a second high impedance layer and a second low impedance layer. Preferably, the first bi-layer is configured to substantially reflect a first wavelength and the second bi-layer is configured to substantially reflect a second wavelength different from the first wavelength. | 05-20-2010 |
| 20100102416 | Integrated Circuit Packages Incorporating an Inductor and Methods - Integrated circuit packages incorporating an inductor and methods for their fabrication. The lead frame used in packaging the integrated circuit includes a first area for receiving the integrated circuit, and a second area having a plurality of connections from one side to the other side of the lead frame, thereby forming coil segments. After mounting the integrated circuit and wire bonding its connections, the lead frame is placed on a ferrite plate, the assembly is encapsulated in resin, and the leads trimmed and bent. Mounting of the packaged integrated circuit on a properly prepared printed circuit interconnects the coil segments in the package to coil segments on the printed circuit, thereby forming a single, multi-turn coil around the ferrite plate. Various embodiments are disclosed. | 04-29-2010 |
| 20100090766 | SELF CONFIGURING OUTPUT STAGES OF PRECISION AMPLIFIERS - Self configuring output stages of precision amplifiers that remain linear when operating into a load that may have a ground reference below the amplifier ground reference, that maintain full amplifier gain while approaching zero output, and that can provide a zero output even when operating into a load that may have a ground reference below the amplifier ground reference, that has a self configuring output stage operable with either a mid-rail or ground reference below amplifier ground, and which maintain a high output impedance when not selected even when the output is above the amplifier supply voltage, or when not powered, thereby allowing amplifier outputs from un-powered amplifiers or amplifiers operating at lower supply voltages to be connected in common for multiplexing to a common load. | 04-15-2010 |
| 20100073485 | System and Method for Video Transmission Line Fault Detection - A video circuit including a video amplifier adapted to generate an amplified output video signal from an input video signal; a short detection circuit adapted to generate a first signal indicative of whether there is a short present at an output of the video amplifier; and a load detection circuit adapted to generate a second signal indicative of whether there is a load coupled to the output of the video amplifier. The video circuit may further include an input signal detection circuit adapted to generate a third signal indicative of whether an input video signal is present. The third signal generated by the input signal detection circuit may be used to enable the outputting of the first and second signals in order to prevent the false indication of faults at the output of the video amplifier in the absence of an input video signal. | 03-25-2010 |
| 20100073106 | BAW Resonator Filter Bandwidth and Out-of-Band Frequency Rejection - Embodiments of the present invention provide systems, devices and methods for improving both the bandwidth of a BAW resonator bandpass filter and the suppression of out-of-band frequencies above the passband. In various embodiments of the invention, blocker inductors are located in series between the filter input and the filter output to realize both bandwidth enhancement and improved out-of-band frequency rejection. For example, a first blocker inductor may be located at the input and a second blocker inductor may be located at the output of a BAW resonator bandpass filter. | 03-25-2010 |
| 20100072615 | High-Electrical-Current Wafer Level Packaging, High-Electrical-Current WLP Electronic Devices, and Methods of Manufacture Thereof - The present invention has various aspects relating to the maximization of current carrying capacity of wafer level packaged chip scale solder pad mounted integrated circuits. In one aspect, the solder pad areas are maximized by using rectangular solder pads spaced as close together as reliable mounting to a circuit board will allow. In another aspect, multiple contact pads may be used for increasing the current capacity without using contact pads of different areas. In still another aspect, vias are used to directly connect one lead of high current component or components to a contact pad directly above that component, and to route a second lead of the high current component to an adjacent contact pad by way of a thick metal interconnect layer. | 03-25-2010 |
| 20100060425 | Battery Assisted RFID Command Set and Interference Control - Specialized battery assisted command set design methods are disclosed that provide for interference rejection using highly sensitive but relatively broadband RFID tags. The command set design also supports RFID system RF power control for further interference control. The command set design also allows for convenient expansion to active transmitters and receivers in tags operating within the same system. Embodiments of the present invention provide RFID systems having battery-assisted, Semi-Passive RFID tags that operate with sensitive transistor based square law tag receivers utilizing a plurality of tag receiver dynamic range states. Additional enhancement attained via power leveling methods that optimize the amount of transmitted power and interference from a reader in relation to the sensitivity of the RFID tags, their ranges from the reader, and the unique physics of the backscatter RFID radio link. | 03-11-2010 |
| 20100040091 | BLIND CHANNEL QUALITY ESTIMATOR - An embodiment is a method and apparatus to perform symbol synchronization. A sign element obtains signs of samples in a sample vector. A correlation estimator computes a correlation of the sample vector. A synchronization detector detects symbol synchronization. | 02-18-2010 |
| 20100005654 | Planarization Methods - Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film. | 01-14-2010 |
| 20100002811 | SOFT REPETITION CODE COMBINER USING CHANNEL STATE INFORMATION - An embodiment is a method and apparatus to decode a signal using channel information. A channel state estimator generates a tone value representing channel information. A quantizer quantizes the tone value. A combiner combines de-interleaved symbols weighed by the quantized tone value. A comparator compares the combined de-interleaved symbols with a threshold to generate a decoding decision. | 01-07-2010 |
| 20090307541 | BLOCK INTERLEAVING SCHEME WITH CONFIGURABLE SIZE TO ACHIEVE TIME AND FREQUENCY DIVERSITY - An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet. | 12-10-2009 |
| 20090307540 | SYSTEM AND METHOD FOR APPLYING MULTI-TONE OFDM BASED COMMUNICATIONS WITHIN A PRESCRIBED FREQUENCY RANGE - According to one embodiment of the invention, an integrated circuit comprises an encoding module, a modulation module and a spectral shaped module. The encoding module includes an interleaver that adapted to operate in a plurality of modes including a first mode and a second mode. The interleaver performs repetitive encoding when placed in the second mode. The modulation module is adapted to compensate for attenuations that are to be realized during propagation of a transmitted signal over the power line. The spectral shaped module is adapted to compensate for amplitude distortion and further compensates for attenuations that will be realized during propagation of the transmitted signal over the power line. | 12-10-2009 |
| 20090304133 | JAMMER CANCELLER FOR POWER-LINE COMMUNICATION - An embodiment is a method and apparatus to cancel signal interference. A jammer remover removes an interfering signal from an input signal to generate a jammer-canceled signal using an adaptive filtering procedure. A jammer detector detects interference caused by the interfering signal. | 12-10-2009 |
| 20090304130 | COMBINED DUAL FEED-FORWARD AND FEEDBACK ANALOG AND DIGITAL AUTOMATIC GAIN CONTROL FOR BROADBAND COMMUNICATION - An embodiment is a method and apparatus to process an input signal. An analog automatic gain control (AGC) processor controls an analog adjustable gain of the input signal using a feedback mechanism. The analog AGC processor generates a first signal. A processing circuit transforms the first signal into a second signal. A digital AGC processor controls a digital adjustable gain of the second signal using a feed-forward mechanism. | 12-10-2009 |
| 20090304061 | BLIND CHANNEL QUALITY ESTIMATOR - An embodiment is a method and apparatus to estimate channel quality. An absolute processor computes absolute real and imaginary values of real and imaginary parts, respectively, of output of a demodulator. A phase count unit generates first and second phase counts representing deviations from zero phase noise using the absolute real and imaginary values. An amplitude count unit generates first and second amplitude counts representing attenuation of a received signal using the absolute real and imaginary values. An integrator integrates the first and second phase counts and first and second amplitude counts into a signal quality indicator that represents a measure of quality of channel with respect to noise and fading. | 12-10-2009 |
| 20090303869 | ROBUST NARROWBAND SYMBOL AND FRAME SYNCHRONIZER FOR POWER-LINE COMMUNICATION - An embodiment is a method and apparatus to perform symbol synchronization. A correlation estimator computes a correlation of a sample vector representative of a narrowband signal. A synchronization detector detects symbol synchronization. | 12-10-2009 |
| 20090302973 | Bulk Acoustic Resonators with Multi-Layer Electrodes - Bulk acoustic resonators with multi-layer electrodes for Bulk Acoustic Wave (BAW) resonator devices. Various electrode combinations are disclosed. The invention provides a better compromise at resonant frequencies from 1800 MHz to 4 GHz in terms of keff2 and resistance than state of the art solutions using either Mo, or a bilayer of Al and W. | 12-10-2009 |
| 20090289722 | Bonded Wafer Package Module - Bonded wafer packages having first and second wafers bonded together forming a matrix of sealed devices, at least one of the wafers having a plurality of passive devices formed thereon, including at least one BAW resonator within each of the sealed devices, the first wafer having conductor filled through-holes forming electrical connections between the passive devices and connections assessable from outside the sealed devices, the bonded wafers being diced to form individual sealed devices. The devices may be duplexers, interstage filters or other circuits such as VCOs and RF circuits. Various embodiments are disclosed. | 11-26-2009 |
| 20090142480 | Optimal Acoustic Impedance Materials for Polished Substrate Coating to Suppress Passband Ripple in BAW Resonators and Filters - Methods of reducing phase and amplitude ripples in a BAW resonator frequency response by providing a substrate, fabricating a Bragg mirror having alternate layers of a high acoustic material and a low acoustic material on a first surface of the substrate, fabricating a BAW on the Bragg mirror, and coating a second side of the substrate opposite the first side with a lossy material having an acoustic impedance in the range of 0.01x to 1.0x the acoustic impedance of the layers of high impedance material, the second surface of the substrate being a polished surface. Various embodiments are disclosed. | 06-04-2009 |
| 20090092387 | Adaptive Current Limiting for Any Power Source with Output Equivalent Series Resistance - Adaptive current limiting for any power source to limit power drain of one load on the power source to maintain a minimum power source voltage for proper operation of other loads on the power source. For battery applications, such as for flash systems, the invention allows the maximum output current of a boost converter to be utilized without having to calculate the system equivalent series resistance first. The invention also adjusts the current load up or down during a high load event to compensate for changes in other loads. The changes in current load are made in increments, with a hysteresis region avoiding constant up and down incrementing. Various embodiments are disclosed. | 04-09-2009 |
| 20090079302 | Methods of Contacting the Top Layer of a BAW Resonator - Methods of contacting the top layer in a BAW device by depositing a metal layer over the BAW device, patterning the metal layer so that the metal layer extends over and contacts the top electrode layer of the BAW device only at a plurality of spaced apart locations adjacent the periphery of the active resonator area, and has a common region laterally displaced from the top and bottom electrodes and electrically interconnecting the parts of the metal layer extending over and contacting the top electrode of the BAW device at the plurality of spaced apart locations. | 03-26-2009 |
| 20090014772 | EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 01-15-2009 |
| 20080296143 | Plasma Systems with Magnetic Filter Devices to Alter Film Deposition/Etching Characteristics - Plasma systems with magnetic filter devices to alter film deposition/etching characteristics by altering the effective magnetic field distribution. The magnetic filter devices are placed between the magnet or magnets and a target, typically a semiconductor wafer, and selected and configured to alter the magnetic field to obtain the desired processing results. For deposition, the magnetic filter may be chosen to provide more uniform deposition, to provide increased deposition rates at or adjacent the edges of a wafer to compensate for increased etching rates at the edges of a wafer in a subsequent etching or polishing process. For annealing and doping, the magnetic field may be altered to provide more uniform equivalent annealing or doping across the wafer. Various applications are disclosed. | 12-04-2008 |
| 20080273401 | METHOD OF ERASING A BLOCK OF MEMORY CELLS - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
| 20080273392 | METHOD OF PROGRAMMING A SELECTED MEMORY CELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 11-06-2008 |
| 20080225601 | EEPROM MEMORY DEVICE WITH CELL HAVING NMOS IN A P POCKET AS A CONTROL GATE, PMOS PROGRAM/ERASE TRANSISTOR, AND PMOS ACCESS TRANSISTOR IN A COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell. | 09-18-2008 |
| 20080204857 | Bragg mirror optimized for shear waves - In an embodiment, set forth by way of example and not limitation, a Bragg mirror includes a first bi-layer of a first thickness and a second bi-layer of a second thickness which is different from the first thickness. In this exemplary embodiment, the first bi-layer consists essentially of a first high impedance layer and a first low impedance layer, and the second bi-layer of a second thickness which is different from the first thickness, the second bi-layer consisting essentially of a second high impedance layer and a second low impedance layer. Preferably, the first bi-layer is configured to substantially reflect a first wavelength and the second bi-layer is configured to substantially reflect a second wavelength different from the first wavelength. | 08-28-2008 |
| 20080197504 | SINGLE-SIDED, FLAT, NO LEAD, INTEGRATED CIRCUIT PACKAGE - An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge). | 08-21-2008 |
