|MathStar, Inc. Patent applications|
|Patent application number||Title||Published|
|20100020880||FIELD PROGRAMMABLE OBJECT ARRAY HAVING IMAGE PROCESSING CIRCUITRY - A field programmable object array integrated circuit has video data compression capability. The integrated circuit comprises an array of programmable objects and a video compression co-processor communicatively coupled to the array of objects. The video compression co-processor comprises a set of search engines and a subpixel engine. The subpixel engine can interpolate subpixels from integer pixels and shift the integer pixels by a predetermined number of subpixels. The search engines can perform a plurality of sum of absolute differences (SAD) computations between search window pixels and macroblock pixels to locate the best SAD value using either integer pixels and/or the interpolated subpixels.||01-28-2010|
|20090206889||Method and Apparatus for Controlling Power Surge in an Integrated Circuit - A method for ramping a high-speed clock to control power surge in an integrated circuit when transitioning from a low power holdstate to an operational state where the integrated circuit includes selected logic circuits adapted to be maintained in the holdstate. A core clock signal including a plurality of core clock pulses is gated with a ramping signal. The ramping signal includes a series of staged signals having gating pulses. Each staged signal is separated by a ramp interval, where the series of staged signals successively enables increasing numbers of clocking pulses from the core clock signal to be transmitted to a holdstate output until a predetermined operational core clock frequency is transmitted to the holdstate output bringing the integrated circuit to the operational state.||08-20-2009|
|20090144595||BUILT-IN SELF-TESTING (BIST) OF FIELD PROGRAMMABLE OBJECT ARRAYS - A field programmable object array integrated circuit has built-in self-testing capability. The integrated circuit comprises an array of programmable objects, a plurality of interfaces, and a controller. The array of objects is designed to operate at an operational clock speed during non-testing operation, wherein the design of the objects is not constrained to require within an object extra circuitry not essential to non-testing operation to facilitate built-in self-testing. The interfaces are connected to the objects to enable communication with the objects and to thereby facilitate built-in self-testing of the objects. The controller causes a selected subset of the objects to be activated and configured for testing, to stimulate the selected subset for some time with an input test pattern delivered via the interfaces while the selected subset of objects operates at the operational clock speed, and to observe a response of the selected subset of objects.||06-04-2009|
Patent applications by MathStar, Inc.