| Marvell World Trade Ltd. Patent applications |
| Patent application number | Title | Published |
|---|
| 20130124918 | SELF-REPARABLE SEMICONDUCTOR AND METHOD THEREOF - A semiconductor device includes a plurality of processors and a spare processor configured to perform respective processing functions. A plurality of first switches is located at respective inputs of the plurality of processors. Each of the plurality of first switches is configured to selectively provide an input signal to a respective one of the plurality of processors and the spare processor. A first multiplexer is located at an input of the spare processor. The first multiplexer is configured to receive the input signals from each of the plurality of first switches and route, to the spare processor, a selected one of the input signals corresponding to a failed one of the plurality of processors. The spare processor is further configured to perform a processing function associated with the failed one of the plurality of processors in response to receiving the selected one of the input signals. | 05-16-2013 |
| 20130124844 | Dynamic Boot Image Streaming - The present disclosure describes apparatuses and techniques for dynamic boot image streaming. In some aspects a memory controller that is streaming multiple boot images from a first memory to a second memory is stalled, a descriptor for streaming one of the multiple boot images from the first memory to a non-contiguous memory location is generated while the memory controller is stalled, and the memory controller is resumed effective to cause the memory controller to stream, based on the descriptor generated while the memory controller is stalled, the second boot image to the non-contiguous memory location. | 05-16-2013 |
| 20130122953 | DIFFERENTIAL CQI ENCODING FOR COOPERATIVE MULTIPOINT FEEDBACK - A method includes receiving in a mobile communication terminal signals from multiple cells that coordinate transmission of the signals with one another in a Cooperative Multipoint (CoMP) scheme. At least first and second Channel Quality Indicators (CQIs), for respective communication channels over which the signals are received, are calculated in the terminal based on the received signals. The second CQI is differentially encoded relative to the first CQI. Feedback information, including the first CQI and the differentially-encoded second CQI, is transmitted from the terminal. | 05-16-2013 |
| 20130121348 | Frequency Duplication Mode for Use in Wireless Local Area Networks (WLANs) - In generating a physical layer (PHY) frequency duplication mode data unit for transmission via a communication channel, a preamble of the PHY frequency duplication mode data unit is generated. The preamble includes a signal field, and the preamble is configured so that a receiver can determine that the data unit is a frequency duplication mode-type data unit prior to decoding the signal field of the preamble. A payload of the PHY frequency duplication mode data unit is generated, and the PHY frequency duplication mode data unit is transmitted. | 05-16-2013 |
| 20130121089 | SYSTEMS AND METHODS FOR REDUCING PEAK POWER CONSUMPTION IN A SOLID STATE DRIVE CONTROLLER - In accordance with an embodiment of the disclosure, systems and methods are provided for reducing an amount of peak power consumption in a device. In certain implementations, a first signal and a second signal are received, wherein the first signal and the second signal are indicative of amounts of power consumption in a device. The first signal is combined with the second signal to generate a combined signal, and at least a portion of the second signal is shifted in time to cause a combination of the first signal and the shifted portion to have a peak amplitude less than a peak amplitude of the combined signal. | 05-16-2013 |
| 20130117637 | ADAPTIVE SYSTEMS AND METHODS FOR STORING AND RETRIEVING DATA TO AND FROM MEMORY CELLS - Adaptive systems include a memory device including a plurality of memory cells, a data quality monitoring block, and an adaptive data encoding block, the data quality monitoring block and the adaptive data encoding block both being operatively coupled to the memory device. The data quality monitoring block is configured to determine a quality value of a group of one or more memory cells included in the memory device, the determined quality value being indicative of a quality of the group of one or more memory cells. The adaptive data encoding block is configured to select a coding scheme from a plurality of coding schemes to encode data to be written to the group of one or more memory cells in the memory device, the selection of the coding scheme being based at least in part on the determined quality value of the group of one or more memory cells. | 05-09-2013 |
| 20130117408 | Method and Apparatus for Arbitration of Time-Sensitive Data Transmissions - The present disclosure describes techniques and apparatuses for arbitration of time-sensitive data transmissions. In some aspects a start of the first scheduled data transmission may be advanced effective to increase the duration of time between an end of the first scheduled data transmission and a start of a second scheduled data transmission. A non-scheduled data transmission can then be performed during the increased duration of time between the end of the advanced first scheduled data transmission and the start of the second scheduled data transmission. | 05-09-2013 |
| 20130115988 | METHODS AND APPARATUS FOR MITIGATING KNOWN INTERFERENCE - Systems and methods for mitigating known interference at a receiving device are provided. A signal from a transmission source is received by a receiving device that is affected by an interference source. At least one of a first pilot signal associated with the transmission source and a second pilot signal associated with the interfering source is determined. The first pilot signal includes information broadcast from the transmission source and the second pilot signal includes information broadcast from the interference source. Interference caused by the interference source is mitigated from the received signal using at least one of the first pilot signal and the second pilot signal. | 05-09-2013 |
| 20130114764 | Physical Layer Frame Format Design for Wideband Wireless Communications Systems - Systems and methods are provided for processing a payload portion of a received signal in a single carrier mode or a multiple carrier mode using a wireless channel receiver based on a portion of the received signal, where a signaling portion of the received signal is a single carrier signal. A single carrier signaling portion is received, and whether the payload portion of the signal is a single carrier signal or a multiple carrier signal is detected from the received single carrier signaling portion. The payload portion of the received signal is demodulated in a single carrier mode if the detecting determines that the payload portion of the received signal is a single carrier signal, and the payload portion of the received signal is demodulated in a multiple carrier mode if the detecting determines that the payload portion of the received signal is a multiple carrier signal. Data from the demodulated payload portion of the received signal is stored in a computer-readable memory. | 05-09-2013 |
| 20130114655 | CODEBOOK SUB-SAMPLING FOR FREQUENCY-SELECTIVE PRECODING FEEDBACK - A method includes, in a mobile communication terminal, holding a definition of a sub-sampled codebook identifying precoding matrices, which are selected from a master codebook that is made-up of a wideband codebook and a frequency-selective codebook. The definition defines a first subset of the wideband codebook and a second subset of the frequency-selective codebook. The second subset of the frequency-selective codebook is represented using no more than two bits. A Multiple-Input Multiple-Output (MIMO) signal is received in the terminal. Based on the received MIMO signal, one or more precoding matrices are selected from the sub-sampled codebook for precoding subsequent MIMO signals transmitted to the terminal, and precoding feedback indicating the selected precoding matrices is calculated. The precoding feedback is transmitted from the terminal. | 05-09-2013 |
| 20130114654 | PRECODING FEEDBACK FOR CROSS-POLARIZED ANTENNAS WITH MAGNITUDE INFORMATION - A method includes receiving in a mobile communication terminal a precoded Multiple-Input Multiple-Output (MIMO) signal, which includes first and second signal components transmitted at respective different first and second polarizations. A difference between respective signal magnitudes of the first and second signal components received in the terminal is estimated in the terminal. Feedback information, which includes at least an indication of the difference between the signal magnitudes, is calculated and transmitted from the terminal. | 05-09-2013 |
| 20130114452 | NETWORK ACCESS MECHANISM BASED ON POWER - Systems and methods for accessing a contention-based communications network are provided. In systems and methods for accessing a contention-based communications network, an access point in the network is created. The access point is a first node connected to the network configured to receive a request from a second node to gain access to the network. A power of a signal transmitted between the access point and the second node is measured. A probability that the second node will access the network is determined based on the measured power of the signal transmitted between the access point and the second node. A determination of whether to permit the second node to gain access to the network is made based on the determined probability. | 05-09-2013 |
| 20130113645 | DETECTION AND ESTIMATION OF RADIO FREQUENCY VARIATIONS - A system including a sampling module that generates samples of RF signals on a first channel during first, second, and third periods, which do not overlap. A difference module determines a first difference between i) a first count of polarity reversals during the first period and ii) a second count of polarity reversals during the second period; a second difference between i) the second count and ii) a third count of polarity reversals during the third period; and a third difference between the first and second differences. A third module determines a frequency of the RF signals based on at least one of the first and second counts, determines a frequency variation of the RF signals based on the first and second counts, and identifies a radar type of the RF signals based on at least one of the third difference and the frequency variation. | 05-09-2013 |
| 20130113568 | PUSH-PULL LOW-NOISE AMPLIFIER WITH AREA-EFFICIENT IMPLEMENTATION - An amplifier integrated circuit (IC) includes a push-pull configuration including a push stage and a pull stage. A first loop of wire is configured to form a first degeneration inductance of the push stage. A second loop of wire is configured to form a first degeneration inductance of the pull stage. The first and second loops are concentric. | 05-09-2013 |
| 20130113451 | INTELLIGENT SWITCHING CONTROLLER AND POWER CONVERSION CIRCUITS AND METHODS - A power conversion circuit comprising a voltage estimation circuit, a current estimation circuit, and a pulse width modulation circuit. The voltage estimation circuit is configured to receive a voltage corresponding to an input of an inductor of the power conversion circuit and generate an estimate of an output voltage of the power conversion circuit based on the voltage. The current estimation circuit is configured to receive a current corresponding to a switch connected in series with the inductor and generate an estimate of an output current of the power conversion circuit based on the current. The pulse width modulation circuit is configured to produce a pulse width modulated signal based on the estimate of the output voltage and the estimate of the output current. | 05-09-2013 |
| 20130102256 | SYSTEMS AND METHODS FOR SUPPRESSING INTERFERENCE IN A SIGNAL RECEIVED BY A DEVICE HAVING TWO OR MORE ANTENNAS - Systems and methods for suppressing interference from a data signal received at a receiving device, where the receiving device has two or more receive antennas, are provided. Characteristics of a channel are estimated, the channel being a channel through which the data signal was transmitted by a transmitting device to the receiving device. A spatial correlation of interference and noise received at the two or more receive antennas of the receiving device is determined based on the estimated characteristics of the channel. The spatial correlation indicates how the interference and noise received at a particular one of the receive antennas is related to the interference and noise received at another one of the receive antennas. The spatial correlation of the interference and noise is used to suppress interference and noise from the data signal received at the receiving device. | 04-25-2013 |
| 20130101060 | SYSTEMS AND METHODS FOR SUPPRESSING INTERFERENCE IN A WIRELESS COMMUNICATION SYSTEM - Systems and methods are provided for suppressing interference from a received data signal. A characteristic of a channel is estimated, the channel being configured for transmission of data between a transmitting device and a receiving device having two or more receive antennas. A spatial correlation of interference is determined for the two or more receive antennas based on the channel characteristic. The received data signal is filtered based on the spatial correlation. | 04-25-2013 |
| 20130099865 | LOW-STRESS CASCODE STRUCTURE - An amplifier system comprises a cascode common-source (CS) amplifier including a plurality of transistors connected in a common-source configuration. A stress reducing circuit is connected to at least one of the plurality of transistors to equalize a voltage drop across the plurality of transistors. The stress reducing circuit includes a first transistor including a control terminal, a first terminal and a second terminal. The second terminal of the first transistor is connected to a first terminal of a first one of the plurality of transistors. A capacitance has a first terminal connected to the control terminal of the first transistor and a second terminal connected to a control terminal of a second one of the plurality of transistors. | 04-25-2013 |
| 20130097344 | Circuit with memory and support for host accesses of storage drive memory - A circuit including a first memory and a processor. The processor is configured to receive data from a host device and transfer the data from the circuit to a storage drive. The processor is configured to receive the data back from the storage drive when a second memory in the storage drive does not have available space for the data, and prior to the data being transferred from the second memory to a third memory in the storage drive. The processor is configured to: store the data received from the storage drive in the first memory or transfer the data received from the storage drive back to the host device; and based on a request received from the storage drive, transfer the data from the first memory or the host device back to the storage drive. The request indicates that space is available in the second memory for the data. | 04-18-2013 |
| 20130094973 | SYSTEMS AND METHODS FOR PROGRAMMING OF A COOLING FAN ARRANGEMENT - Embodiments of the present disclosure provide a method that comprises, based upon receipt of a mode command, changing an operating mode of a fan motor controller of a fan to a serial port communication protocol, programming a memory of the fan motor controller with an operating parameter of the fan, and based upon receipt of a serial port command, changing the operating mode of the fan motor controller from the serial port communication protocol to another protocol. | 04-18-2013 |
| 20130094390 | LOCATION AWARE BACKGROUND ACCESS POINT SCANNING FOR WLAN - Respective distances between a communication device and a plurality of wireless local area network (WLAN) access points are determined. One of the plurality of WLAN access points with which the communication device is to associate is selected based on the determined distances. | 04-18-2013 |
| 20130093568 | ANTENNA INTERFACE FOR RADIO FREQUENCY IDENTIFICATION CIRCUIT - Systems, methods, and other embodiments associated with radio frequency identification (RFID) circuits are described. According to one embodiment, a radio frequency identification circuit includes an antenna network, including an antenna and an antenna interface coupled to the antenna, wherein the antenna interface includes first and second capacitors, which are coupled in series with the antenna. An integrated circuit includes a first pin and a second pin coupled respectively to a first node and a second node of the second capacitor and configured to operate as a reader and a tag in combination with the antenna network, and an amplifier embedded in the integrated circuit and configured to provide an output admittance determined by a ratio of current and voltage negative feedback signals such that a frequency response of the combined integrated circuit and antenna network is adjustable without increasing power consumption of the RFID when operating as a reader. | 04-18-2013 |
| 20130091579 | INTELLIGENT CONNECTORS INTEGRATING MAGNETIC MODULAR JACKS AND INTELLIGENT PHYSICAL LAYER DEVICES - An apparatus comprises a connector, wherein the connector comprises i) a jack, wherein the jack comprises a) a plurality of electrical terminals, and b) a magnetic component electrically coupled to the plurality of electrical terminals; and ii) a physical layer device, wherein the physical layer device comprises a) a physical layer module, wherein the physical layer module comprises an interface configured to receive packets from the jack, and an interface bus configured to inspect the packets, and b) a network interface configured to, based on the inspection of the packets by the interface bus, provide the packets to a device separate from the physical layer device. | 04-11-2013 |
| 20130091307 | METHOD AND APPARATUS FOR EFFECTIVELY INCREASING A COMMAND QUEUE LENGTH FOR ACCESSING STORAGE - The present disclosure includes systems and techniques relating to effectively increasing a command queue length for accessing storage, such as by increasing the Queuing Depth (Q-Depth) of Native Command Queuing (NCQ) Commands. In some implementations, a method can comprise receiving a first command to access a first memory location of a storage device; receiving a second command to access a second memory location of a storage device; constructing a consolidated command including a memory address and a data transfer count associated with each of the first command and the second command; constructing an information command having consolidation information about the consolidated command; and communicating the information command and the consolidated command to the storage device for processing by the storage device. | 04-11-2013 |
| 20130088965 | BUFFER MANAGER AND METHODS FOR MANAGING MEMORY - Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed. | 04-11-2013 |
| 20130088727 | POSITIONAL DATA ERROR CORRECTION - Systems, apparatuses, and methods for correcting systematic errors in positional data of electronic devices configured to navigate across a surface. An apparatus configured to correct positional errors may comprise one or more navigation sensors, and a position module configured to control the one or more navigation sensors to capture a plurality of navigational measurements and adjust the navigational measurements by one or more scaling factors to determine a translation path of the apparatus over a medium. The one or more scaling factors may be constructed by capturing a plurality of navigational measurements to determine a detected translation path of an apparatus, comparing an actual translation path of the apparatus to the detected translation path of the apparatus, and generating the one or more scaling factors based at least in part on a difference between the actual translation path and the detected translation path. Other embodiments also are described. | 04-11-2013 |
| 20130083836 | CONCATENTATION-ASSISTED SYMBOL-LEVEL COMBINING FOR MIMO SYSTEMS WITH HARQ AND/OR REPETITION CODING - Systems and methods are provided for decoding signal vectors in multiple-input multiple-output (MIMO) systems, where the receiver has received one or more signal vectors from the same transmitted vector. The receiver combines the received vectors by vector concatenation The concatenated vector may then be decoded using, for example, maximum-likelihood decoding. In some embodiments, the combined signal vector is equalized before decoding. | 04-04-2013 |
| 20130080729 | PILOT PLACEMENT FOR NON-VOLATILE MEMORY - A memory control module includes a format module that communicates with a memory array that includes B memory blocks each including P physical pages and Q logical pages. The format module selects X predetermined locations to write pilot data and read-back pilot signals in each of the B memory blocks. B, P, Q and X are integers greater than or equal to 1. The memory control module also includes a signal processing module that compares the written pilot data to the read-back pilot signals and that determines variations between the written pilot data and the read-back pilot signals based on the comparison. | 03-28-2013 |
| 20130080666 | HARD DISK DRIVE INTEGRATED CIRCUIT WITH INTEGRATED GIGABIT ETHERNET INTERFACE MODULE - An integrated circuit of a hard disk drive includes an Ethernet network interface module configured to transmit and receive data packets via an Ethernet connection. The data packets respectively include packet headers and at least one of small computer system interface (SCSI) commands and SCSI data requests. A processor is configured to process the data packets transmitted and received by the Ethernet network interface module. A hard disk control module is configured to control, based on the at least one of the SCSI commands and the SCSI data requests, writing of data to a hard disk and reading of the data from the hard disk. Each of the hard disk control module, the processor, and the network interface module is located in the integrated circuit. | 03-28-2013 |
| 20130077549 | INTEGRATED CIRCUIT AND METHOD WITH PRE-BEACON ACTIVATION TIME ADJUSTMENT - An integrated circuit including a transceiver module that receives beacons from an access point (AP), and transition a wireless network device to an active mode based on: a predetermined beacon interval; and a first predetermined period prior to one of multiple beacons. A timestamp module calculates a first correction value based on a first timestamp received from the AP. An adjustment module adjusts the first predetermined period based on the first correction value. A beacon module detects a beacon missed during an inactive mode by the transceiver module. The timestamp module transmits a probe request signal to the AP a second predetermined period after detection of the missed beacon, receives a second timestamp from the AP in response to the probe request signal, and recalculates the first correction value based on the second timestamp. The adjustment module adjusts the first predetermined period based on the recalculated first correction value. | 03-28-2013 |
| 20130077538 | CONFERENCE MIXING USING TURBO-VAD - A conference mixer includes a unit configured to receive a plurality of input streams, a spectral voice activity detection (VAD) unit configured to, for each of the input streams, generate and output a spectral VAD decision indicating whether a frame including data packets is voice, a turbo VAD unit configured to generate and output a turbo VAD decision that indicates for a frame including data packets which input stream is active, the turbo VAD decision being based on the spectral VAD decisions and a power-based decision indicating whether an estimated instantaneous power level of a frame including data packets is greater than a power threshold, and a finite state machine (FSM) unit configured to select which of the input streams to output as an active stream based on a plurality of the turbo VAD decisions, the turbo VAD decision being based in part on feedback provided by the FSM. | 03-28-2013 |
| 20130064060 | METHOD AND APPARATUS FOR DETERMINING A LOCATION OF A FEATURE ON A STORAGE MEDIUM - A change in a property of a signal is detected, the signal having been sensed from a storage medium by a disk drive. A count is determined, the count corresponding to a first location on the storage medium at which the change in the property of the signal sensed from the storage medium is detected. The count is used to predict a second location on the storage medium corresponding to the change in the property of the signal sensed from the storage medium. Relative to the first location on the storage medium, the second location on the storage medium is closer to an actual location of a feature on the storage medium that causes the change in the property of the signal sensed from the storage medium. | 03-14-2013 |
| 20130059596 | ASYMMETRICAL FEEDBACK FOR COORDINATED TRANSMISSION SYSTEMS - A method includes, in a mobile communication terminal, receiving from at least first and second base stations, which cooperate in a coordinated transmission scheme, signals that are transmitted over respective first and second communication channels. Respective channel measures are calculated for the communication channels based on the received signals. First and second feedback data, which are indicative of the respective channel measures of the first and second communication channels, are formulated such that the first feedback data has a first data size and the second feedback data has a second data size, different from the first data size. The first and second feedback data are transmitted from the mobile communication terminal to at least one of the base stations. | 03-07-2013 |
| 20130058504 | MULTI-MODE AUDIO AMPLIFIERS - A multimode audio amplifier comprises: a mode controller adapted to provide a control signal; and at least one multimode module, wherein each of the multimode modules has a plurality of operating modes, wherein the operating modes are selected in accordance with the control signal, wherein changing the operating modes results in a measurable change in at least one characteristic of the multimode audio amplifier; wherein the characteristics of the multimode audio amplifier consist of signal to noise ratio (SNR); total harmonic distortion and noise (THD+N); input to output delay; power consumption; and efficiency. | 03-07-2013 |
| 20130058300 | Uplink Power Control in Aggregated Spectrum Systems - A method for communication includes modulating data in a wireless communication terminal to produce an aggregated-spectrum signal, which includes at least first and second signals in respective first and second spectral bands. The modulated data is transmitted in the first and second signals at respective first and second power levels. The second power level is adjusted separately from the first power level. In some embodiments, one or more instructions to set the first power level are received at the wireless communication terminal, and the first power level is set separately from setting the second power level based on the instructions. | 03-07-2013 |
| 20130052966 | System and Transceiver Clocking to Minimize Required Number of Reference Sources in Multi-Function Cellular Applications Including GPS - A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals. | 02-28-2013 |
| 20130046966 | Preloader - This disclosure describes techniques and/or apparatuses for reducing the total time used to boot up a computer and load applications onto the computer. | 02-21-2013 |
| 20130045688 | Short-Range Wireless Communication - The present specification describes techniques and apparatus that enable wireless devices to communicate effectively at short ranges. In one implementation, the transmit power of a transmitting device is reduced to permit a receiving device to demodulate a signal. | 02-21-2013 |
| 20130045687 | Short-Range Wireless Communication - The present specification describes techniques and apparatus that enable wireless devices to communicate effectively at short ranges. In one implementation, the transmit power of a transmitting device is reduced to permit a receiving device to demodulate a signal. | 02-21-2013 |
| 20130045573 | CHIP ON LEADS - Described herein are microelectronic packages including a plurality of bonding fingers and multiple integrated circuit chips, at least one integrated circuit chip being mounted onto the bonding fingers. According to various embodiments of the present invention, mounting the integrated circuit chip onto the bonding fingers may reduce the pin-out count by allowing multiple integrated circuit chips to be interconnected within the same microelectronic package. Other embodiments may be described and claimed. | 02-21-2013 |
| 20130044555 | PROCESSOR WITH MEMORY DELAYED BIT LINE PRECHARGING - A processor includes an array of memory cells, a control module, a precharge circuit, and an amplifier module. The control module generates a clock signal at a first rate, reduces the first rate to a second rate for a predetermined period, and adjusts the second rate back to the first rate at an end of the predetermined period. The precharge circuit: based on the first rate, precharges first bit lines connected to memory cells in a first row of the array of memory cells; based on the second rate, refrains from precharging the first bit lines; and precharges the first bit lines subsequent to the end of the predetermined period. The amplifier module: based on the first rate, access first instructions stored in the first row; and based on the second rate, accesses second instructions stored in the first row or a second row of the array. | 02-21-2013 |
| 20130039427 | Method and Apparatus for Periodic Structure Handling for Motion Compensation - A motion compensated picture rate converter for determining a dominant motion vector for a block appearing in two images includes a high-pass filter and a low-pass filter, transform calculators responsive to the filters for performing transforms on at least two images to produce a frequency-domain representation of the images, estimating calculators for estimating a plurality of motion vectors based on the frequency-domain representations, and a periodic structure detection and elimination module responsive to the transform calculators and the estimating calculators for identifying a period based on the frequency-domain representation of the images and for selecting a dominant motion vector based on the estimated motion vectors and the identified period. A method of operation is also disclosed. | 02-14-2013 |
| 20130031432 | FULLY-BUFFERED DUAL IN-LINE MEMORY MODULE WITH FAULT CORRECTION - A memory circuit including a logic circuit, content addressable memory, and a multiplexer. The logic circuit is configured to output a first address. The content addressable memory is configured to i) receive the first address and ii) output a substitute address and a match signal if the first address matches a second address stored in the content addressable memory. The multiplexer is configured to i) receive the first address and the substitute address and ii) selectively output one of the first address and the substitute address based on the match signal. | 01-31-2013 |
| 20130026609 | PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE WITH STRESS RELIEF STRUCTURE - An apparatus configured to be coupled onto a substrate, wherein the apparatus comprises a semiconductor substrate and the semiconductor substrate includes a plurality of trenches defined within a side of the semiconductor substrate. The apparatus further comprises an interconnect layer over portions of the side of the semiconductor substrate, wherein the portions of the side of the semiconductor substrate include the plurality of trenches defined within the side of the semiconductor substrate. Each trench is configured to respectively receive a solder ball to provide an interface between i) the interconnect layer and ii) the substrate to which the apparatus is to be coupled. | 01-31-2013 |
| 20120320723 | Method and Apparatus for Offset and Gain Correction - Aspects of the disclosure provide a signal processing circuit that includes a signal processing circuit includes a processing path configured to process an electrical signal to produce input data samples, and a feed-forward correction module configured to delay the input data samples to produce delayed data samples, to apply the delayed data samples to a timing loop during periods when a profile variation of the data samples is not detected, and to apply the input data sample to the timing loop during periods when a profile variation of the data samples is detected. | 12-20-2012 |
| 20120278686 | SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING - The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information. | 11-01-2012 |
| 20120266049 | Parallel Reed-Solomon RAID (RS-RAID) Architecture, Device, and Method - The parallel RS-RAID data storage architecture can aggregate that data and checksums within each cluster into intermediate or partial sums that are transferred or distributed to other clusters. The use of intermediate data symbols, intermediate checksum symbols, cluster configuration information on the assignment of data storage devices to clusters and the operational status of data storage devices, and the like, can reduce the computational burden and latency for the error correction calculations while increasing the scalability and throughput of the parallel RS-RAID distributed data storage architecture. | 10-18-2012 |
| 20100050163 | CACHING RUN-TIME VARIABLES IN OPTIMIZED CODE - In one embodiment, the present invention includes a method for emitting a live range statement into a program for a memory variable to be cached during run-time that has at least one simulation state variable if the memory variable is dynamically mapped, and defining the simulation state variable at a first execution path of the program. In such manner, the program may be optimized using the live range statement and the simulation state variable. Also, a debugger may use the simulation state variables in obtaining and displaying the memory variable from a cache. | 02-25-2010 |
| 20090307437 | Multiport Memory Architecture, Devices and Systems Including the Same, and Methods of Using the Same - A multiport memory architecture, systems including the same and methods for using the same. The architecture generally includes (a) a memory array; (b) a plurality of ports configured to receive and/or transmit data; and (c) a plurality of port buffers, each of which is configured to transmit the data to and/or receive the data from one or more of the ports, and all of which are configured to (i) transmit the data to the memory array on a first common bus and (ii) receive the data from the memory array on a second common bus. The systems generally include those that embody one or more of the inventive concepts disclosed herein. The methods generally relate to writing blocks of data to, reading blocks of data from, and/or transferring blocks of data across a memory. The present invention advantageously reduces latency in data communications, particularly in network switches, by tightly coupling port buffers to the main memory and advantageously using point-to-point communications over long segments of the memory read and write paths, thereby reducing routing congestion and enabling the elimination of a FIFO. The invention advantageously shrinks chip size and provides increased data transmission rates and throughput, and in preferred embodiments, reduced resistance and/or capacitance in the memory read and write busses. | 12-10-2009 |
| 20090265408 | METHODS AND APPARATUS FOR PERFORMING CALCULATIONS USING REDUCED-WIDTH DATA - Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from instruction memory during a runtime phase. | 10-22-2009 |
| 20090052502 | RAKE RECEIVER INTERFACE - In some embodiments of the present invention, a method and apparatus to generate interrupts in a transfer of information between a rake receiver and a processor, said interrupts having a rate of generation per unit time independent of a rate of the transfer of information per unit time. | 02-26-2009 |
