| Marvell International Ltd. Patent applications |
| Patent application number | Title | Published |
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| 20120045140 | IMAGE PROCESSING APPARATUS HAVING CONTEXT MEMORY CONTROLLER - An apparatus for use in image processing is set forth that comprises a pixel processor, context memory, and a context memory controller. The pixel processor is adapted to execute a pixel processing operation on a target pixel using a context of the target pixel. The context memory is adapted to store context values associated with the target pixel. The context memory controller may be adapted to control communication of context values between the pixel processor and the context memory. Further, the context memory controller may be responsive to a context initialization signal or the like provided by the pixel processor to initialize the content of the context memory to a known state, even before the pixel processor has completed its image processing operations and/or immediately after completion of its image processing operations. In one embodiment, the pixel processor executes a JBIG coding operation on the target pixel. | 02-23-2012 |
| 20110298862 | DEVICE AND METHOD FOR SERVICING AN INKJET PRINT HEAD ON A HAND HELD PRINTER - A hand-held printer that includes an inkjet array having a plurality of inkjets is disclosed. The hand-held printer may include an inkjet cap sized to cooperatively engage the inkjet array, wherein the inkjet cap is movable between and open position and a closed position, and a plurality of wipers carried by the inkjet cap, wherein each of the plurality of wipers is configured to engage one of the plurality of inkjets as the inkjet cap moves from the open position to the closed position; and wherein each of the plurality of wipers includes a gasket configured to form a seal adjacent to one of the plurality of inkjets. | 12-08-2011 |
| 20110293024 | METHOD FOR INCREASING THE PERFORMANCE OF A COMMUNICATIONS SYSTEM ON A MEDIUM FORMED BY MULTIPLE CONDUCTORS - Method for increasing the performance of a communications system on a medium formed by multiple conductors which increases the performance of a communications system by means of the creation of numerous communication channels with a high degree of isolation between each other on the same physical medium formed by multiple conductors. The method can be extended to be used in various applications, such as the reuse of frequencies on the same channel, the increase of the capacity of the point-to-point links in a network and the improvement of performance and reliability when used with digital processing of signals for transmission or reception, among others. | 12-01-2011 |
| 20110131347 | DIRECT MEMORY ACCESS CONTROLLER WITH MULTIPLE TRANSACTION FUNCTIONALITY - A direct memory access controller is set forth. The direct memory access controller includes first and second registers storing various values that are used to set the parameters of DMA transfers that take place during a single data transaction. The first register stores a start address location value used to define a start address at which direct memory access transfers for the transaction are to begin. The second register stores a value used to end data transfers of the data transaction. The DMA controller also includes transfer control circuitry for executing the data transaction. The transfer control circuitry is adapted to automatically execute multiple, consecutive data transactions using the values stored in the first and second registers. | 06-02-2011 |
| 20110010593 | SCAN ARCHITECTURE FOR FULL CUSTOM BLOCKS - A output storage latch within a combinational logic circuit may be adapted to form a scan flip-flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit. A described master/slave clock approach allows the scan flip-flop latch to support receiving into a scan chain a sequence of test input data, execution of combinational logic matrix testing based on the test input data, and sequentially outputting test results to a test result register for comparison with expected results. The described scan flip-flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit. Use of the described dual-use scan flip-flop latch results in a less complex circuit design, reduced circuit area requirements and improved reliability. | 01-13-2011 |
| 20100277823 | MAGNETIC DISC CONTROLLER AND METHOD - A magnetic disk controller includes a first buffer that includes a first storage area that stores former portions of pieces of writing data, and a second storage area that stores latter portions of pieces of writing data; an encoding unit that encodes a former portion of the first piece of writing data; a second buffer that stores the encoded former portion of the first piece of writing data; and a buffer control unit that writes the encoded former portion of the first piece of writing data into a first sector of the magnetic disk. The encoding unit encodes the latter portion of the first piece of writing data. The second buffer stores the encoded latter portion of the first piece of writing data. The buffer control unit, writes the encoded latter portion of the first piece of writing data into the first sector of the magnetic disk. | 11-04-2010 |
| 20100277200 | SELF-CALIBRATING WRITER - In accordance with the invention, a method, system and apparatus are presented that matches the output impedance of a driver to the impedance of a transmission line. A method for matching the impedance between a driver and a transmission line, wherein the transmission line is between the driver and a load can include transmitting a first pulse from the driver to the load through the transmission line, wherein a first reflection from the transmitted first pulse occurs after a first time, measuring a second reflection from the transmitted first pulse after a second time, and adjusting the calibration of the driver in response to the measured second reflection. | 11-04-2010 |
| 20100264955 | METAL PROGRAMMABLE LOGIC AND MULTIPLE FUNCTION PIN INTERFACE - Some of the embodiments of the present invention provide an integrated circuit device including a first metal interconnect, an end of which is coupled to a core of the integrated circuit device, a second metal interconnect, an end of which is coupled to a first input/output (I/O) pin, and a third metal interconnect configured to be coupled to the first metal interconnect and to the second metal interconnect. Other embodiments are also described and claimed. | 10-21-2010 |
| 20100250821 | INTER-PROCESSOR COMMUNICATION LINK WITH MANAGEABILITY PORT - Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided. | 09-30-2010 |
| 20100250165 | Control of Delivery of Current Through One or More Discharge Lamps - Control of delivery of current through one or more discharge lamps. Methods include alternately switching on and off switching elements that control a fluorescent lamp, in response to receiving input, until the brightness of the lamp decreases to a threshold. Further, methods include providing control signals at complementary duty cycles to further decrease the brightness and alternating the duty cycles of the signals applied to the filaments of the fluorescent lamp. Methods include digitally comparing voltage signals supplied to a fluorescent lamp and the current drawn by the fluorescent lamp. | 09-30-2010 |
| 20100220243 | SYSTEMS AND METHODS FOR CALIBRATING POWER REGULATED COMMUNICATION CIRCUITRY - Systems and methods are provided for calibrating the control mechanism in a communication circuit to allow the communication circuit to maintain a desired output power level. The communication circuit includes a variable gain adjustment circuit and a power amplifier, which operate together to provide an output power level. A control circuit controls the variable gain adjustment circuit based on a default gain parameter, a high power threshold, and a low power threshold. A calibration circuit in the control circuit calibrates a default gain parameter to provide a desired output power. A power detector can detect the desired output power level to provide an output power measurement. The calibration circuit calibrates upper and lower power thresholds to provide an acceptable range of power variation around the output power measurement. | 09-02-2010 |
| 20090300325 | DATA PROCESSING SYSTEM, APPARATUS AND METHOD FOR PERFORMING FRACTIONAL MULTIPLY OPERATIONS - A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for the fractional multiply operations. A coprocessor included in the processing core performs the fractional multiply operations on the operands and stores the result in a destination register that is also included in the processing core. | 12-03-2009 |
| 20090292976 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR IDENTIFICATION AND EVALUATION - Systems and methods are provided for implementing error identification and evaluation for a Reed-Solomon (RS) error-correction code (ECC) system. The BMA algorithm and/or list decoding may produce one or more error locator polynomials that are related to a decision-codeword. An accelerated Chien search can be used to more quickly evaluate the one or more error locator polynomial. If the accelerated Chien search identifies a valid error locator polynomial, a normal Chien search can be used to identify error locations, and Forney's algorithm or an equivalent technique can be used to evaluate the error values. A RS ECC decoder can include a computation circuit that evaluates an error locator polynomial or an error evaluator polynomial. The computation circuit can include computation components that receive the coefficients of the polynomials. | 11-26-2009 |
| 20090219096 | OPEN LOOP DC CONTROL FOR A TRANSIMPEDANCE FEEDBACK AMPLIFIER - A transimpedance amplifier having open-loop DC control is provided. The open-loop feedback control may provide a DC bias that is configurable based on the characteristics of an input device, such as, a photodiode or a magnetoresistor. The open-loop feedback control may provide quick recovery from voltage level variations and may provide stability for the amplifier. | 09-03-2009 |
| 20090083608 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-26-2009 |
| 20090063937 | ARCHITECTURE AND CONTROL OF REED-SOLOMON ERROR-CORRECTION DECODING - Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed. | 03-05-2009 |
| 20090055717 | ARCHITECTURE AND CONTROL OF REED-SOLOMON LIST DECODING - Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes. | 02-26-2009 |
| 20090049273 | PHYSICALLY-TAGGED CACHE WITH VIRTUAL FILL BUFFERS - A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers. | 02-19-2009 |
| 20090037753 | Methods and apparatus to selectively power functional units - A processing engine fetches one or more lines of software instructions into an instruction cache. Based on the contents of the cache, potentially needed functional units are identified as functional units that are operable to execute at least one software instruction stored within the instruction cache. Unneeded functional units are identified as functional units that are not operable to execute a software instruction stored within the instruction cache. A power increase is initiated for selected ones of the potentially needed functional units that are determined to be in a low power state. A power decrease is initiated for selected ones of the unneeded functional units that are determined to be in an operable power state. | 02-05-2009 |
| 20090013131 | LOW POWER SEMI-TRACE INSTRUCTION CACHE - A semi-trace cache combines elements and features of an instruction cache and a trace cache. An ICache portion of the semi-trace cache is filled with instructions fetched from the next level of the memory hierarchy while a TCache portion is filled with traces gleaned either from the actual stream of retired instructions or predicted before execution. | 01-08-2009 |
| 20080282008 | System and Apparatus for Early Fixed Latency Subtractive Decoding - Systems and methods for early fixed latency subtractive decoding are disclosed. The subtractive decoding device speculatively acknowledges a bus transaction within a fixed time period that is the same as the time period for positive decoding. Pipelining of a new bus transaction may therefore be accomplished each new time period. A bus transaction may be retried if no acknowledgement occurs within the fixed time period. | 11-13-2008 |
| 20080279024 | PROGRAMMABLE BOOSTING AND CHARGE NEUTRALIZATION - A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a circuit path between the input node and the output node. Each of the capacitance stages includes a capacitor, and a control transistor having a gate capacitance in series with the capacitor, wherein the gate capacitance is configured to be added to the capacitance of the capacitor between the input node and the output node. | 11-13-2008 |
| 20080270768 | Method and apparatus for SIMD complex Arithmetic - Methods and apparatus for calculating Single-Instruction-Multiple-Data (SIMD) complex arithmetic. A coprocessor instruction has a format identifying a multiply and subtract instruction to generate real components for complex multiplication of first operand complex data and corresponding second operand complex data, a cross multiply and add instruction to generate imaginary components for complex multiplication of the first operand complex data and the corresponding second operand complex data, an add-subtract instruction to add real components of the first operand to imaginary components of the second operand and to subtract real components of the second operand from imaginary components of the first operand, and a subtract-add instruction to subtract the real components of the second operand from the imaginary components of the first operand and to add the real components of the first operand to the imaginary components of the second operand. | 10-30-2008 |
| 20080209187 | Storing and processing SIMD saturation history flags and data size - A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturation operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated. A second coprocessor instruction has a second format identifying a saturation history processing operation and a saturation data size. An operand for the processing operation is determined based on the saturation data size, and the processing operation is executed on the saturation flags and the operand for the saturation data size. Condition code flags are stored in a status register to indicate the result of processing operation. | 08-28-2008 |
