| MAO BANG ELECTRONIC CO., LTD. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120091595 | Layered Integrated Circuit Apparatus - A device having layered integrated circuit (IC) chips is provided. The chip comprises notches, conductive area, apertures, and routing pool. A conductive material is set in the apertures. The second chip is layered on the first chip. The notches of the second chip are corresponding to the first conducting area of the first chip. A conductive material is also set in the notch between the conductive area of the first chip and the notches of the second chip. Thus, a system is integrated by layering the first chip and the second chip for enhancing flexibility and reliability of circuit layout. | 04-19-2012 |
| 20120074558 | Circuit Board Packaged with Die through Surface Mount Technology - A package of a circuit board and a die are packed through surface mount technology (SMT). The shortest circuit is formed with at a low cost. Thus, the package can work in high speed and high frequency applications. | 03-29-2012 |
| 20110291291 | Silicon Chip Having Penetrative Connection Holes - Two circuit layout areas on two surfaces of a chip are connected. Holes in the chip are coordinated with a conductive paste to connect the two surfaces. Thus, fabrication is made easy and cost is reduced. | 12-01-2011 |
| 20110260300 | Wafer-Bump Structure - A wafer-bump structure includes a wafer-state semiconductor die, a pre-treatment layer, a first ENIG laminate and at least one pillar bump. The wafer-state semiconductor die includes at least one die pad embedded therein and a passivation layer formed on the wafer-state semiconductor die and the die pad. The passivation layer includes an aperture for allowing access to a portion of the die pad. The pre-treatment layer is formed on the un-covered portion of the die pad. The first ENIG laminate is formed on the pre-treatment layer and an annular portion of the passivation layer around the pre-treatment layer. The pillar bump includes a conductive metal layer and a second ENIG laminate. The conductive metal layer is formed on the first ENIG laminate and another annular portion of the passivation layer around the first ENIG laminate. The second ENIG laminate is formed on the conductive metal layer and another annular portion of the passivation layer around the conductive metal layer. | 10-27-2011 |
| 20110228487 | Integrated Circuit Card - An integrated circuit card includes a laminate, solder bumps, a die and a package. The laminate includes a core board sandwiched between two conductive layers. The conductive layers are connected to each other with solder bumps filled in apertures defined in the core board. The die is provided on one of the conductive layers. The package is provided on the die and an area of the conductive layer around the die. | 09-22-2011 |
| 20110176021 | Image-Processing Integrated Circuit - An image-processing integrated circuit includes an image-processing die, a conductive layer, first optical units and a second optical unit. The conductive layer is provided on a face of the image-processing die. The first optical units are provided on an opposite face of the image-processing die. The second optical unit is provided on the first optical units. | 07-21-2011 |
| 20110143536 | Method for Making an Aperture in a Carrier and Electrically Connecting Two Opposite Faces of the Carrier - Disclosed is a method for making an aperture in a carrier and electrically connecting two opposite faces of the carrier. At first, a carrier is provided. Secondly, a heater is provided for heating a portion of the carrier in an environment rich in oxygen, thus making an aperture in the carrier and forming an isolative layer on the wall of the aperture synchronously. Finally, the aperture is filled with a conductive material. | 06-16-2011 |
| 20110108983 | Integrated Circuit - An integrated circuit includes a die including contacts formed thereon. A first dielectric layer is formed on the die. The first dielectric layer includes apertures defined therein corresponding to the contacts. A second dielectric layer is formed on the second dielectric layer. The second dielectric layer includes apertures defined therein corresponding to the apertures of the first dielectric layer. Redistribution layers are located in the apertures of the first and second dielectric layers and connected to the contacts. A passivation layer is located on the second dielectric layer and the redistribution layers. The passivation layer includes apertures corresponding to the redistribution layers. A solder ball is located in each of the apertures of the passivation layer and connected to a related one of the redistribution layers. | 05-12-2011 |
| 20110062590 | Chip Stacking Device Having Re-Distribution Layer - A chip stacking device uses nano particle silver paste for re-distribution interconnection to form a structure having low resistance through trench filling or printing. Thus, due to its low resistance, it can effectively reduce the electrical instability due to voltage drop after current flows. Furthermore, power consumption is reduced too, with energy saved. With its stable electrical signal, its utilization scope can be further expanded to high frequency product. | 03-17-2011 |
| 20110062586 | Chip for Reliable Stacking on another Chip - A chip includes a device, a passivation layer, two dielectric layers, at least one upper redistribution layer, at least one lower redistribution layer, at least one tunnel, at least one conductor, a redistribution passivation layer and at least one solder ball. The device includes at least one pad. The tunnel is defined in the upper redistribution layer, the first dielectric layer, the passivation layer, the pad, the device, the chip, the second dielectric layer and the lower redistribution layer. The conductor is located in the tunnel and connected to the upper and lower redistribution layers. The redistribution passivation layer is located on the second dielectric layer, the lower redistribution layer and the conductor. The solder ball is located on a portion of the lower redistribution layer through an aperture defined in the redistribution passivation layer. The chip can be connected to a printed circuit board by the solder ball. | 03-17-2011 |
| 20110057318 | Die Package - A die is packaged. The package of the die has a line groove filled with a conductive material. A metal pad is exposed out of a solder mask. And the metal pad is connected with a die pad on the die through the line groove in a deflective way. In this way, a wiring space of a wafer is efficiently used; and a manufacturing yield of the wafer is enhanced. | 03-10-2011 |
| 20110031635 | Stacked Integrated Circuit Device - A device having stacked integrated circuit (IC) chips is provided. The chips and other wires are connected through circuit contacts and notches or apertures. The notches or apertures are filled with a conductive material. Thus, flexibility of circuit layout is achieved with easy fabrication and enhanced reliability. | 02-10-2011 |
| 20110019457 | Flash memory - A flash memory includes a controller unit and dies. The dies are connected to a controller unit. Each of the dies includes an upper face and a lower face. Each of the dies includes at least one power supply pad, at least one grounding pad, at least one input/output pad, selection pads and standby/busy pads on each of the upper and lower faces. The power supply pad is connected to the controller unit. The grounding pad is connected to the power supply pad in parallel. The input/output pad is connected to the grounding pad in parallel. The selection pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. The standby/busy pads are connected to the controller unit and connected to one another with a wire that can be cut if so desired. | 01-27-2011 |
