MAGSIL CORPORATION Patent applications |
Patent application number | Title | Published |
20150055410 | MEMORY CIRCUIT AND METHOD FOR DISSIPATING EXTERNAL MAGNETIC FIELD - Memory circuit and method for at least partially dissipating an external magnetic field before the magnetic field affects operation of an array of addressable magnetic storage element stacks in the memory circuit. Multiple dummy magnetic storage element stacks are provided around the periphery of the array. Each of the dummy stacks is substantially circular for orienting along the external magnetic field, thereby causing the dissipation. Each of the addressable and the dummy stacks may be formed with a magnetic tunnel junction (MTJ). | 02-26-2015 |
20150031146 | TOOL FOR ANNEALING OF MAGNETIC STACKS - In one embodiment of the invention, there is provided a tool for annealing a magnetic stack. The tool includes a housing defining a heating chamber; a holding mechanism to hold at least one wafer in a single line within the heating chamber, a heating mechanism to heat the at least one wafer; and a magnetic field generator to generate a magnetic field whose field lines pass through the single line of wafers during a magnetic annealing process; wherein the holding mechanism comprises a wafer support of holding the single line of wafers between the heating mechanism and the magnetic field generator. The tool may be a rapid thermal processor retrofitted with the magnetic field generator. | 01-29-2015 |
20150023096 | COUNTERBALANCED-SWITCH MRAM - A magnetic memory cell is provided. The cell comprises first and second free layers; and an intermediate layer separating the first and second free layers, wherein the first and second free layers are magnetostatically coupled. | 01-22-2015 |
20150021724 | SELF CONTACTING BIT LINE TO MRAM CELL - Embodiments of the invention disclose magnetic memory cell configurations in which a magnetic storage structure is coupled to an upper metal layer with minimal overlay margin. This greatly reduces a size of the memory cell. | 01-22-2015 |
20140301138 | MEMORY CELL WITH SCHOTTKY DIODE - Memory cell comprising two conductors, with a serially connected magnetic storage element and a Schottky diode between the two conductors. The Schottky diode provides a unidirectional conductive path between the two conductors and through the element. The Schottky diode is formed between a metal layer in one of the two conductors and a processed junction layer. Methods for process and for operation of the memory cell are also disclosed. The memory cell using the Schottky diode can be designed for high speed operation and with high density of integration. Advantageously, the junction layer can also be used as a hard mask for defining the individual magnetic storage element in the memory cell. The memory cell is particularly useful for magnetic random access memory (MRAM) circuits. | 10-09-2014 |
20140256061 | Method of Etching MTJ Using CO Process Chemistries - A method for fabricating a magnetic film structure is provided. The method comprises forming a magnetic structure on a bottom electrode layer, the magnetic structure comprising at least one pinned bottom magnetic film layer having a fixed magnetic orientation; at least one top magnetic film layer whose magnetic orientation can be manipulated by a current; and a tunneling layer between the bottom magnetic film layer and the top magnetic film layer; forming a metallic hard mask atop the magnetic structure; patterning and etching the metallic hard mask to define exposed areas of the magnetic structure; selectively etching the exposed areas of the magnetic structure by a chemical etch process based on a CO etch chemistry to form discrete magnetic bits. | 09-11-2014 |
20140254250 | MAGNETIC MEMORY CIRCUIT WITH STRESS INDUCING LAYER - Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed. | 09-11-2014 |
20140091412 | Magnetic Sidewalls for Write Lines in Field-Induced MRAM and Methods of Manufacturing Them - In one embodiment, there is provided a non-volatile magnetic memory cell. The non-volatile magnetic memory cell comprises a switchable magnetic element; and a word line and a bit line to energize the switchable magnetic element; wherein at least one of the word line and the bit line comprises a magnetic sidewall that is discontinuous. | 04-03-2014 |
20140042569 | Magnetic Enhancement Layer in Memory Cell - Magnetic memory cell comprising two conductors and a magnetic storage element between the two conductors, wherein a magnetic enhancement layer (MEL) is provided in the proximity of at least along a partial length of at least one of the two conductors. The MEL is for enhancing a magnetic field in the element when the two conductors are energized. Methods for operation and fabrication process for the memory cell are also disclosed. The memory cell is particularly for use in magnetic random access memory (MRAM) circuits, when using magnetic tunnel junction (MTJ) stacks as the magnetic storage elements. | 02-13-2014 |
20130308375 | Semiconductor Integrated Circuit for Low and High Voltage Operations - A semiconductor integrated circuit comprising a first circuit area for a low voltage operation and a second circuit area for a high voltage operation. The circuit areas comprise two vertically stacked backend patterned metal layers that are separated by an inter-metallic dielectric (IMD). The two metal layers and the IMD form a combination that is operable at the low voltage. The first circuit area uses a first portion of the combination for operating at the low voltage and the second circuit area uses a second portion of the combination for routing at the high voltage, the two metal layers in the second portion being interconnected through the IMD by via hole, for withstanding the high voltage. The first portion may comprise an array of magnetic random access memory (MRAM) devices and the second circuit area may comprise a display drive circuit. | 11-21-2013 |
20110032755 | VOLTAGE BOOSTING IN MRAM CURRENT DRIVERS - Disclosed is a current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor M | 02-10-2011 |
20100208514 | Magnetic Memory Cell and Method of Fabricating Same - A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media. | 08-19-2010 |
20080212364 | Magnetic Memory Cell and Method of Fabricating Same - A magnetic memory cell in which a sensor is magnetically coupled to a magnetic media wherein the separation of the magnetic media from the sensor permits each to be magnetically optimized separate from the other, thus improving defect tolerance and minimizing the magnetic influence of neighboring cells in an array on one another. In an embodiment, the read circuitry is positioned so that no read current passes through the media during a read operation. In an alternative embodiment, processing is simplified but the read current is allowed to pass through the media. | 09-04-2008 |