| MagIC Technologies, Inc. Patent applications |
| Patent application number | Title | Published |
|---|
| 20120085728 | Novel process for MEMS scanning mirror with mass remove from mirror backside - Two methods of fabricating a MEMS scanning mirror having a tunable resonance frequency are described. The resonance frequency of the mirror is set to a particular value by mass removal from the backside of the mirror during fabrication. | 04-12-2012 |
| 20110317479 | Shared bit line SMT MRAM array with shunting transistors between the bit lines - An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells. | 12-29-2011 |
| 20110096443 | MTJ incorporating CoFe/Ni multilayer film with perpendicular magnetic anisotropy for MRAM application - A MTJ for a spintronic device is disclosed and includes a thin composite seed layer made of at least Ta and a metal layer having fcc(111) or hcp(001) texture as in Ta/Ti/Cu to enhance perpendicular magnetic anisotropy (PMA) in an overlying laminated layer with a (CoFe/Ni) | 04-28-2011 |
| 20090086531 | Method and implementation of stress test for MRAM - Voltage and current stress for magnetic random access memory (MRAM) cells can weed out potential early failure cells. Method and circuit implementation of such a stress test for a MRAM comprise coupling a stress test circuit to the read bus of the MRAM and stressing the Magnetic Tunnel Junctions (MTJS) by tying them to ground by activating isolation transistors associated with them. Read word lines control which MTJs are stressed Both the method and implementation can be used for any memory cells based on resistance differences, such as Phase RAM or Spin Valve MRAM. | 04-02-2009 |
| 20080266943 | Spin-torque MRAM: spin-RAM, array - A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing. | 10-30-2008 |
