| MACRONIX INTERNATIONAL CO., LTD. Patent applications |
| Patent application number | Title | Published |
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| 20120131227 | SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION - A serial peripheral interface of an integrated circuit including multiple pins is provided. The pins are coupled to the integrated circuit. The integrated circuit receives an instruction through only one of the plurality of pins. The integrated circuit receives an address through the plurality of pins. The integrated circuit sends a read out data through the plurality of pins. | 05-24-2012 |
| 20120129350 | METHOD FOR REDUCING WORDLINE BRIDGE RATE - The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) etching a metal-silicide layer and a POLY layer via a hard mask, wherein the metal-silicide layer is disposed on the POLY layer; (b) forming a POLY recess in the POLY layer; and (c) forming a liner film covering the metal-silicide layer. | 05-24-2012 |
| 20120127797 | SYSTEM AND METHOD FOR TESTING FOR DEFECTS IN A SEMICONDUCTOR MEMORY ARRAY - A system and method for testing semiconductor memory devices includes a variable voltage input to a memory cell control gate. The voltage to the control gate can be varied from a voltage level used for normal memory cell operation, such as a read operation, to a voltage level that can be used to detect a defect in the memory device. During testing, the voltage level applied to the control gate is lower than the voltage level applied to a second terminal, such as a drain terminal, of the memory cell. In some embodiments, testing for defects can include applying a negative voltage to the control gate, while a positive voltage is applied to the drain terminal, which can reveal the presence of a gate-to-drain leakage defect. | 05-24-2012 |
| 20120127795 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF AND OPERATING METHOD OF MEMORY CELL - A non-volatile memory and a manufacturing method thereof and a method for operating a memory cell are provided. The non-volatile memory includes a substrate, first and second doped regions, a charged-trapping structure, first and second gates and an inter-gate insulation layer. The first and second doped regions are disposed in the substrate and extend along a first direction. The first and second doped regions are arranged alternately. The charged-trapping structure is disposed on the substrate. The first and second gates are disposed on the charged-trapping structure. Each first gate is located above one of the first doped regions. The second gates extend along a second direction and are located above the second doped regions. The inter-gate insulation layer is disposed between the first gates and the second gates. Adjacent first and second doped regions and the first gate, the second gate and the charged-trapping structure therebetween define a memory cell. | 05-24-2012 |
| 20120126323 | SEMICONDUCTOR DEVICE HAVING A SPLIT GATE AND A SUPER-JUNCTION STRUCTURE - A semiconductor device comprises a source region, a drain region, and a drift region between the source and drain regions. A split gate is disposed over a portion of the drift region, and between the source and drain regions. The split gate includes first and second gate electrodes separated by a gate oxide layer. A super-junction structure is disposed within the drift region between the gate and the drain region. | 05-24-2012 |
| 20120126307 | NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF - A non-volatile memory and a manufacturing method thereof are provided. The non-volatile memory includes a substrate, a gate structure, a first doped region, a second doped region and a pair of isolation structures. The gate structure is disposed on the substrate. The gate structure includes a charge storage structure, a gate and spacers. | 05-24-2012 |
| 20120122296 | METHODOLOGY FOR WORDLINE SHORT REDUCTION - The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) providing a plurality of SASTIs with a plurality of first POLY cells deposited thereon; and (b) depositing a first fill-in material having a relatively high etching rate oxide-like material in the plurality of SASTIs and on each side wall of the plurality of first POLY cells. | 05-17-2012 |
| 20120120723 | Dynamic Pulse Operation for Phase Change Memory - The control circuit performs a reset operation and a set operation that change the resistance states of phase change memory cells of the array. The control circuit changes at least one parameter, of at least one of the reset operation and the set operation for future operations. This change is responsive to an indicator of degraded memory state retention of the array. | 05-17-2012 |
| 20120119282 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSi | 05-17-2012 |
| 20120115304 | ISOLATION STRUCTURE AND FORMATION METHOD THEREOF - An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers. | 05-10-2012 |
| 20120112788 | Phase Change Device for Interconnection of Programmable Logic Device - A programmable logic device has a configurable interconnection coupling logic blocks, where the configurable interconnection has a phase change element with an amorphous region having a variable size to determine the phase change element is open or short. This isolates the programming path from the logic path. | 05-10-2012 |
| 20120108031 | RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR MANUFACTURING THE SAME - A resistive random access memory including, an insulating layer, a hard mask layer, a bottom electrode, a memory cell and a top electrode is provided. The insulating layer is disposed on the bottom electrode. The insulating layer has a contact hole having a first width. The hard mask layer has an opening. A portion of the memory cell is exposed from the opening and has a second width smaller than the first width. The top electrode is disposed on the insulating layer and is coupled with the memory cell. | 05-03-2012 |
| 20120104542 | Semiconductor Structure With Contact Structure and Manufacturing Method of the Same - The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface. | 05-03-2012 |
| 20120104516 | METAL SILICIDE FORMATION - Techniques for forming metal silicide contact pads on semiconductor devices are disclosed, and in one exemplary embodiment, a method may comprise depositing a metal layer on and between a plurality of raised silicon-based features formed on a semiconductor substrate, the metal layer comprising metal capable of reacting with external silicon-based portions of the features to form a metal silicide. In addition, such a method may also include depositing a cap layer on the metal layer deposited on and between the plurality of raised silicon-based features, wherein a thickness of the cap layer on the metal layer between the raised features is greater than or equal to a thickness of the cap layer on the metal layer on the raised features. Furthermore, such a method may also include annealing the structure to cause portions of the metal layer to react with portions of the external silicon-based portions of the features to form metal silicide pads on and between the raised features. | 05-03-2012 |
| 20120104492 | LOW ON-RESISTANCE RESURF MOS TRANSISTOR - The present invention relates to a low on-resistance RESURF MOS transistor, comprising: a drift region; two isolation regions formed on the drift region; a first-doping-type layer disposed between the two isolation regions; and a second-doping-type layer disposed below the first-doping-type layer. | 05-03-2012 |
| 20120094494 | METHODS FOR ETCHING MULTI-LAYER HARDMASKS - A method to further adjust the final CD of a material to be etched during an etching process, and after a photolithographic patterning process can include patterning a semiconductor substrate using a mask layer. The mask layer can comprise a hardmask material having a protruding feature with an initial width. A first plasma comprising carbon and fluorine can be introduced into a chamber, where residual carbon and fluorine is deposited on at least the chamber wall. A portion of the mask layer can then be removed with a second plasma incorporating the residual carbon and fluorine, whereby remaining hardmask material forms a feature pattern where the protruding feature has a final width different from the initial width. The feature pattern can then be transferred to the semiconductor substrate using the final width of the at least one protruding feature provided by the remaining hardmask material. | 04-19-2012 |
| 20120092940 | Memory Device and Read Operation Method Thereof - A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current. | 04-19-2012 |
| 20120092937 | Method and System for A Serial Peripheral Interface - A method for dual I/O data read in an integrated circuit which includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently. | 04-19-2012 |
| 20120091980 | SYSTEM AND METHOD FOR CONTROLLING VOLTAGE RAMPING FOR AN OUTPUT OPERATION IN A SEMICONDUCTOR MEMORY DEVICE - A voltage driving circuit comprises a current bias generating unit and a voltage driving unit. The current bias generating unit is configured to receive a mode signal and to generate a mode selection current in response to the mode signal. The voltage driving unit is coupled to the current bias generating unit, and is configured to receive the mode selection current and to drive an output voltage at a slew rate that is set according to the mode selection current. The voltage driving unit can include a plurality of stages, where each stage is configured to drive the output voltage at a respective different slew rate according to the mode signal. | 04-19-2012 |
| 20120081962 | LOW VOLTAGE PROGRAMMING IN NAND FLASH - A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection. The program operation is based on metering a flow of carriers between a first semiconductor body region on a first side of the selected cell in the NAND string and a second semiconductor body region on a second side of the selected cell. A program potential higher than a hot carrier injection barrier level is applied to the selected cell, and then the drain to source voltage across the selected cell and the flow of carriers in the selected cell reach a level sufficient to support hot carrier injection, which is controlled by a switch cell adjacent the selected cell. | 04-05-2012 |
| 20120080657 | LOW OPERATIONAL CURRENT PHASE CHANGE MEMORY STRUCTURES - Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced. | 04-05-2012 |
| 20120077309 | THERMALLY STABILIZED ELECTRODE STRUCTURE - Memory devices and methods for manufacturing are described herein. A memory device as described herein includes a first electrode layer, a second electrode layer, and a thermal isolation structure including a layer of thermal isolation material between the first and second electrode layers. The first and second electrode layers and the thermal isolation structure define a multi-layer stack having a sidewall. A sidewall conductor layer including a sidewall conductor material is on the sidewall of the multi-layer stack. The sidewall conductor material has an electrical conductivity greater than that of the thermal isolation material. A memory element including memory material is on and in contact with the second electrode layer. | 03-29-2012 |
| 20120075943 | Method and Apparatus for Memory Repair With Redundant Columns - A first redundant column is used to repair multiple defects in an array of memory cells. The defects include at least a first defect and a second defect in different main columns of a plurality of main columns in the array. However, all of the multiple defects repaired by the first redundant column are not required to be in different main columns. The array is arranged into a plurality of rows accessed by row addresses and the plurality of main columns accessed by column addresses. | 03-29-2012 |
| 20120075925 | PCRAM With Current Flowing Laterally Relative to Axis Defined By Electrodes - An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode. | 03-29-2012 |
| 20120074486 | MULTI-GATE BANDGAP ENGINEERED MEMORY - Memory cells comprising: a semiconductor substrate having a source region and a drain region disposed below a surface of the substrate and separated by a channel region; a tunnel dielectric structure disposed above the channel region, the tunnel dielectric structure comprising at least one layer having a hole-tunneling barrier height; a charge storage layer disposed above the tunnel dielectric structure; an insulating layer disposed above the charge storage layer; and a gate electrode disposed above the insulating layer are described along with arrays and methods of operation. | 03-29-2012 |
| 20120069671 | MEMORY AND OPERATION METHOD THEREFOR - An operation method for a memory device having a plurality of memory cells includes: reading the plurality of memory cells by a first word line voltage to get a first number of a first logic state; reading the plurality of memory cells by a second word line voltage to get a second number of the first logic state, the second word line voltage different from the first word line voltage; and using the second word line voltage as a target word line voltage if the first number of the first logic state is equal to the second number of the first logic state. | 03-22-2012 |
| 20120063250 | NON-VOLATILE MEMORY DEVICE AND CHARGE PUMP CIRCUIT FOR THE SAME - A charge pump apparatus comprises a plurality of charge pump stages. The charge pump stages each include a respective output node. Output nodes are connected to charge boosting circuitry and to precharge circuitry. The charge boosting circuit receives one or more clock signals. The precharge circuits have a first state allowing the respective pump-stage output node to fluctuate at a level above a standby wordline voltage, and a second state coupling the respective pump-stage output node to the standby wordline voltage. | 03-15-2012 |
| 20120063236 | Method and Apparatus for Reducing Read Disturb in Memory - Various aspects of a NAND memory include a control circuit that applies a read bias arrangement to a plurality of word lines to read a selected data value stored on a plurality of memory cells by measuring current flowing between the first end and the second end of the series of memory cells. The read bias arrangement is applied to word lines of the plurality of word lines applies only word line voltages less than a second maximum of a second threshold voltage distribution. | 03-15-2012 |
| 20120063232 | METHOD AND APPARATUS FOR REDUCING READ DISTURB IN MEMORY - Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage. | 03-15-2012 |
| 20120063228 | DATA SENSING ARRANGEMENT USING FIRST AND SECOND BIT LINES - Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into reference data lines and cancelled in the differential sensing amplifiers. | 03-15-2012 |
| 20120057410 | Method and Apparatus for the Erase Suspend Operation - Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector. | 03-08-2012 |
| 20120057258 | ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND METHOD THEREOF - An electrostatic discharge protection device for protecting an inner circuit, which is operated in a source voltage, is provided and includes a protection unit and a control unit. The protection unit provides a discharge path for transmitting an electrostatic signal from a pad to a ground line. According to a voltage level at a control end, the protection unit adjusts a holding voltage and a triggering voltage determining whether to conduct the discharge path. When the source voltage is supplied, the control unit transmits the input voltage to the control end of the protection unit, so as to raise the holding and the triggering voltages of the discharge path. When the source voltage is not supplied, the control unit switches the control end of the protection unit to a floating condition by the electrostatic signal, so as to lower the holding and the triggering voltages of the discharge path. | 03-08-2012 |
| 20120056259 | MEMORY CELL, MEMORY DEVICE AND METHOD FOR MANUFACTURING MEMORY CELL - A memory cell including a substrate, a stacked gate structure and a first isolation structure is provided. The substrate has a first doped region, a second doped and a channel region located between the first doped region and the second doped region. The stacked gate structure is disposed on the channel and at least includes a charge trapping layer and a gate from bottom to top. The first isolation structure is disposed in the substrate and is connected to the first doped region and extends downwards from the first doped region for a predetermined length, and a bottom of the first isolation structure is lower than a bottom of the first doped region. | 03-08-2012 |
| 20120043657 | METHOD FOR FABRICATING CONDUCTIVE LINES - Methods for fabricating conductive metal lines of a semiconductor device are described herein. In one embodiment, such a method may comprise depositing a conductive material over a substrate, and depositing a first barrier layer on the conductive layer. Such a method may also comprise patterning a mask on the first barrier layer, the pattern comprising a layout of the conductive lines. Such an exemplary method may also comprise etching the conductive material and the first barrier layer using the patterned mask to form the conductive lines. In addition, a low temperature post-flow may be performed on the structure. The method may also include depositing a dielectric material over and between the patterned conductive lines. | 02-23-2012 |
| 20120040532 | PAD AND METHOD FOR CHEMICAL MECHANICAL POLISHING - A method for chemical-mechanical polishing two adjacent structures of a semiconductor device is provided. The method for mechanical polishing comprising: (a) providing a semiconductor device comprising a recess formed in a surface thereof, a first layer formed over the surface, and a second layer filled with the recess and formed on the first layer; and (b) substantially polishing the first and second layer with a pad and a substantially inhibitor-free slurry, wherein the pad comprising a corrosion inhibitor of the second layer. | 02-16-2012 |
| 20120037989 | LDMOS HAVING SINGLE-STRIP SOURCE CONTACT AND METHOD FOR MANUFACTURING SAME - LDMOS devices having a single-strip contact pad in the source region, and related methods of manufacturing are disclosed. The LDMOS may comprise a first well lightly doped with a first dopant and formed into a portion of a substrate, the first well having a drain region at its surface heavily doped with the first dopant, and a second well lightly doped with a second dopant formed in another portion of the substrate, the second well having a source region at its surface comprising first portions heavily doped with the first dopant directly adjacent second portions heavily doped with the second dopant. Also, the LDMOS device may comprise a field oxide at the upper surface of the substrate between the source and drain regions, and contacting the first well but separated from the second well, and a gate formed partially over the field oxide and partially over the source region. The LDMOS may also comprise contact pads in contact with the gate, and source and drain regions, wherein the contact pad in contact with the source regions comprises a single-strip of conductive material extending across the source region. | 02-16-2012 |
| 20120037877 | ONE-MASK PHASE CHANGE MEMORY PROCESS INTEGRATION - An example embodiment disclosed is a method for fabricating a phase change memory cell. The method includes forming a non-sublithographic via within an insulating substrate. The insulating substrate is embedded on the same layer as a first metalization layer (Metal | 02-16-2012 |
| 20120037876 | Resistance Random Access Memory Structure for Enhanced Retention - A bistable resistance random access memory is described for enhancing the data retention in a resistance random access memory member. A dielectric member, e.g. the bottom dielectric member, underlies the resistance random access memory member which improves the SET/RESET window in the retention of information. The deposition of the bottom dielectric member is carried out by a plasma-enhanced chemical vapor deposition or by high-density-plasma chemical vapor deposition. One suitable material for constructing the bottom dielectric member is a silicon oxide. The bistable resistance random access memory includes a bottom dielectric member disposed between a resistance random access member and a bottom electrode or bottom contact plug. Additional layers including a bit line, a top contact plug, and a top electrode disposed over the top surface of the resistance random access memory member. Sides of the top electrode and the resistance random access memory member are substantially aligned with each other. | 02-16-2012 |
| 20120037191 | CLEANING SEQUENCE FOR OXIDE QUALITY MONITORING SHORT-LOOP SEMICONDUCTOR WAFER - Disclosed herein are methods for novel cleaning processes for inline quality monitoring short-loop semiconductor wafers. In one embodiment, an exemplary process may comprise immersing the short-loop wafer in an SC-2 aqueous solution comprising hydrochloric acid and hydrogen peroxide at a temperature of about 60° C., and for a time period of about 600 seconds, and then rinsing the wafer with deionized water to remove residual SC-2 solution immediately following immersing the wafer in the SC-2 solution. This exemplary method may then comprise immersing the short-loop wafer in an SC-1 aqueous solution comprising ammonia and hydrogen peroxide immediately after rinsing the wafer to remove residual SC-2 solution, and then rinsing the wafer with deionized water to remove residual SC-1 solution immediately following immersing the wafer in the SC-1 solution. In such a method, however, the wafer is immersed in an HF aqueous solution comprising hydrofluoric acid immediately prior to immersing the wafer in the SC-2 solution, or immediately after immersing the wafer in the SC-1 solution. | 02-16-2012 |
| 20120033518 | CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 02-09-2012 |
| 20120025278 | SCHOTTKY DIODE - A Schottky diode comprises an ohmic layer that can serve as a cathode and a metal layer that can serve as an anode, and a drift channel formed of semiconductor material that extends between the ohmic and metal layers. The drift channel includes a heavily doped region adjacent to the ohmic contact layer. The drift channel forms a Schottky barrier with the metal layer. A pinch-off mechanism is provided for pinching off the drift channel while the Schottky diode is reverse-biased. As a result, the level of saturation or leakage current between the metal layer and the ohmic contact layer under a reverse bias condition of the Schottky diode is reduced. | 02-02-2012 |
| 20120022957 | System and Method of Managing Contactless Payment Transactions Using a Mobile Communication Device as a Stored Value Device - A method handling payment transactions in a system using mobile communication devices as stored value devices is disclosed. A transaction operations server receives multiple records of the transaction from the stored value device—one via a communication channel through the telecommunication provider network, and another via an independent communication channel. The records are reconciled at the transaction server for transaction verification. | 01-26-2012 |
| 20120020138 | TRANSISTOR HAVING AN ADJUSTABLE GATE RESISTANCE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME - A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor. | 01-26-2012 |
| 20120019232 | Current Source with Tunable Voltage-Current Coefficient - A current source providing an output current with a fixed current range includes a bias circuit, a resistor, a current mirror, and a controller. The bias circuit provides a first voltage weighted with a first tunable coefficient and a second voltage weighted with a second tunable coefficient. The resistor has a tunable resistance for determining a bias current according to a voltage difference between the first and the second voltages and the tunable resistance. The current mirror generates the output current according to the bias current. The controller adjusts the tunable resistance and one of the first and the second tunable coefficients to achieve a voltage-current coefficient with different values, while the bias current and the output current are kept within a fixed current range. | 01-26-2012 |
| 20120018845 | Polysilicon Plug Bipolar Transistor For Phase Change Memory - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base. | 01-26-2012 |
| 20120018790 | NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF - A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions. | 01-26-2012 |
| 20120016472 | Color Tactile Vision System - A tactile display writer unit includes a probe having a contact tip, and at least a first actuator and a second actuator coupled to the probe, whereby activation of the actuators results in a displacement of the probe tip in one or more of a z-direction and in a lateral direction having a vector in an x-y plane. Also, a display writer includes a plurality of such units supported in an x-y array. The writer units may have a third actuator coupled to the probe. Also, a tactile vision system includes such a display writer, an image processor, and an image sensor. The processor transforms RGB image information from the image sensor into hue-based information having two or more attributes; and the actuators in the tactile display writer are activated by the information attributes. Also, a method for producing a tactile color stimulus at a site on the skin of a subject includes providing a probe having a contact tip; displacing the tip at the contact site in a direction generally normal to the skin surface at the site to an extent that relates one attribute of a hue-based model of the color, and displacing the tip in at least one lateral direction generally in a plane parallel to the skin surface at the site to an extent that relates to at least one additional attribute of the color. | 01-19-2012 |
| 20120011300 | METHOD AND APPARATUS FOR HIGH-SPEED BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY - Techniques utilizing an erase-once, program-many progressive indexing structure manage data in a flash memory device which avoids the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. Consequently, block-based flash memory can be used for high-speed byte access. | 01-12-2012 |
| 20120008388 | NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF - An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting a main voltage distribution group and a plurality of secondary voltage distribution groups, wherein each of the main voltage distribution group and the secondary voltage distribution groups includes N threshold-voltage distribution curves, and N is an integer greater than 2; selecting a first operation level and a second operation level according to a programming command; programming the first storage position according to the threshold-voltage distribution curve corresponding to the first operation level in the main voltage distribution group; selecting one of the secondary voltage distribution groups according to the first operation level and programming the second storage position according to the threshold-voltage distribution curve corresponding to the second operation level in the selected secondary voltage distribution group. | 01-12-2012 |
| 20120008363 | Diode-Less Array for One-Time Programmable Memory - A one-time programmable memory array includes a first row conductor extending in a first row direction and disposed at a first elevation, a second row conductor extending in a second row direction and disposed at a second elevation and a column conductor extending in a column direction and disposed adjacent to the first row conductor and adjacent to the second row conductor. The array also includes a dielectric layer covering at least a portion of the column conductor, a fuse link coupled between the dielectric layer on the column conductor and the second row conductor. | 01-12-2012 |
| 20120002484 | OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE - A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells. | 01-05-2012 |
| 20120000423 | HDP-CVD SYSTEM - An HDP-CVD system is described, including an HDP-CVD chamber for depositing a material on a wafer, and a pre-heating chamber disposed outside of the HDP-CVD chamber to pre-heat the wafer, before the wafer is loaded in the HDP-CVD chamber, to a temperature higher than room temperature and required in the deposition step to be conducted in the HDP-CVD chamber. The pre-heating chamber is equipped with a heating lamp for the pre-heating. The wafer has been formed with a trench before being pre-heated. | 01-05-2012 |
| 20110317493 | Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit - Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. | 12-29-2011 |
| 20110317480 | PHASE CHANGE MEMORY CODING - An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit. | 12-29-2011 |
| 20110317471 | Nonvolatile stacked nand memory - A memory cell is arranged to enhance the electrical field of the memory element. The memory cell has a metal-oxide memory element, a nonconductive element, and a conductive element. The metal-oxide memory element is in a current path between a first electrode at a first voltage and a second electrode at a second voltage. The nonconductive element is adjacent to the metal-oxide memory element. | 12-29-2011 |
| 20110316096 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device can be manufactured by a method that includes forming a structure that includes a plurality of layers of semiconductor material. One or more etching processes are performed on the multi-layered semiconductor structure, and then an Ar/O | 12-29-2011 |
| 20110305088 | HOT CARRIER PROGRAMMING IN NAND FLASH - A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers. | 12-15-2011 |
| 20110305074 | SELF-ALIGNED BIT LINE UNDER WORD LINE MEMORY ARRAY - A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps. | 12-15-2011 |
| 20110304341 | METHOD OF TESTING INTEGRATED CIRCUITS - A method of testing integrated circuits includes providing an integrated circuit test system that has a voltage supply and a plurality of control channels. A first switching element is connected between the voltage supply and a first integrated circuit, and a second switching element is connected between the voltage supply and the second integrated circuit. The switching elements can include, for example, electromagnetic relays. The relays are controlled by respective test system control channels to selectively provide electrical power to each of the integrated circuits. | 12-15-2011 |
| 20110303968 | Nonvolatile Memory Array With Continuous Charge Storage Dielectric Stack - An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines. | 12-15-2011 |
| 20110300682 | CHARGE TRAPPING DEVICES WITH FIELD DISTRIBUTION LAYER OVER TUNNELING BARRIER - A memory cell comprising: a semiconductor substrate with a surface with a source region and a drain region disposed below the surface of the substrate and separated by a channel region; a tunneling barrier dielectric structure with an effective oxide thickness of greater than 3 nanometers disposed above the channel region; a conductive layer disposed above the tunneling barrier dielectric structure and above the channel region; a charge trapping structure disposed above the conductive layer and above the channel region; a top dielectric structure disposed above the charge trapping structure and above the channel region; and a top conductive layer disposed above the top dielectric structure and above the channel region are described along with devices thereof and methods for manufacturing. | 12-08-2011 |
| 20110292728 | INTEGRATED CIRCUIT OF DEVICE FOR MEMORY CELL - A reading method for a multi-level cell (MLC) memory includes the following steps. A number of word line voltages are sequentially provided to an MLC memory cell. A number of bit line voltages corresponding to the word line voltages are sequentially provided to the MLC memory cell. One of the word line voltages is higher than another one of the word line voltages, and one of the bit line voltages corresponding to the one of the word line voltages is lower than another one of the bit line voltages corresponding to the another one of the word line voltages. | 12-01-2011 |
| 20110291638 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with tolerance of variation in power. A compensation circuit is powered by a supply voltage. The compensation circuit generates a compensated voltage reference, which is compensated for variation in the supply voltage. The compensated voltage reference is compared by comparison circuitry against an output of timing circuitry, to determine timing of the clock signal. | 12-01-2011 |
| 20110286283 | 3D TWO-BIT-PER-CELL NAND FLASH MEMORY - A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string. | 11-24-2011 |
| 20110286258 | NONVOLATILE MEMORY DEVICE HAVING A TRANSISTOR CONNECTED IN PARALLEL WITH A RESISTANCE SWITCHING DEVICE - A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states. | 11-24-2011 |
| 20110280058 | NONVOLATILE MEMORY DEVICE - A memory device comprises an array of memory cells each capable of storing multiple bits of data. Each memory cell includes a programmable transistor in series with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states. | 11-17-2011 |
| 20110278528 | SELF ALIGNED FIN-TYPE PROGRAMMABLE MEMORY CELL - A fin-type programmable memory cell includes a bottom electrode electrically coupled to an access device, a top electrode, and an L-shaped memory material element electrically coupled to the bottom and top electrodes. A memory array includes an array of such memory cells, electrically coupled to an array of access devices. Method for making a memory cell, includes: forming a dielectric support layer over a bottom electrode, the dielectric support layer having an upper surface; forming a cavity through the dielectric support layer, exposing a surface of the bottom electrode and defining a dielectric support structure having a sidewall; forming a film of memory material over the dielectric support structure and in the cavity; depositing a dielectric spacer layer over the memory material film; forming a dielectric sidewall spacer from the dielectric spacer layer and a memory material structure having a generally horizontal portion underlying the dielectric sidewall spacer and a generally vertical portion between the dielectric sidewall spacer and the sidewall of the dielectric support structure; forming a dielectric fill; planarizing the dielectric fill to expose upper ends of the vertical portion of the memory material structure; depositing a top electrode material over the planarized dielectric fill; and forming a top electrode from the top electrode material and a memory material element from the memory material structure. | 11-17-2011 |
| 20110273936 | ERASE PROCESS FOR USE IN SEMICONDUCTOR MEMORY DEVICE - A method of erasing memory cells of a memory device includes programming memory cells if the erasing procedure is suspended. The erasing procedure can include pre-programming, erasing, and soft-programming of memory cells in a selected memory unit. If a suspend command is received, for example to allow for a read operation of memory cells of another unit of memory, the erasing procedure stops the pre-programming, erasing, or soft-programming, and proceeds with programming one or more memory cells of the memory unit that was being erased. | 11-10-2011 |
| 20110273930 | Diode Memory - A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal. | 11-10-2011 |
| 20110273237 | Oscillator With Frequency Determined By Relative Magnitudes of Current Sources - An oscillator circuit includes a circuit loop and multiple current sources. The circuit loop includes an output having the oscillating signal. The multiple current sources are turned on independently of a phase of the oscillating signal. The current sources control magnitudes of both charging current and discharging current at nodes of the circuit loop, including the output. Relative magnitudes of different current sources determine a frequency of the oscillating signal. | 11-10-2011 |
| 20110267889 | A HIGH SECOND BIT OPERATION WINDOW METHOD FOR VIRTUAL GROUND ARRAY WITH TWO-BIT MEMORY CELLS - A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array. | 11-03-2011 |
| 20110267881 | MEMORY ARRAY - A memory array is shown, including memory cells with source and drain doped regions, and global bit lines coupled to the doped regions via select transistors. The connections of the select transistors are configured such that the respective loading capacitances of two global bit lines respectively coupled to the source and the drain of a memory cell to be read do not vary with the memory cell to be read. | 11-03-2011 |
| 20110266601 | Single Gate Semiconductor Device - A semiconductor device has a gate multiple doping regions on both sides of the gate. The gate can be shared by a transistor and a capacitor. | 11-03-2011 |
| 20110263125 | METHOD OF FORMING MARK IN IC-FABRICATING PROCESS - A method of forming a mark in an IC fabricating process is described. Two parts of the mark each including a plurality of linear patterns are respectively defined by two exposure steps that either belong to two lithography processes respectively or constitute a double-exposure process including X-dipole and Y-dipole exposure steps. | 10-27-2011 |
| 20110263075 | Vacuum Jacket For Phase Change Memory Element - A memory device including a phase change element and a vacuum jacket. The device includes a first electrode element; a phase change element in contact with the first electrode element; an upper electrode element in contact with the phase change element; a bit line electrode in contact with the upper electrode element; and a dielectric fill layer surrounding the phase change element and the upper electrode element, spaced from the same and sealed by the bit line electrode to define a vacuum jacket around the phase change element and upper electrode element. | 10-27-2011 |
| 20110255350 | METHOD OF OPERATING MEMORY CELL - A method of operating a memory cell is provided. The memory cell has first, second, third and fourth storage regions in a charge-storage layer between a substrate and a word line. The first and second storage regions are respectively adjacent to lower and upper portions at one side of the protruding part of the substrate, and the third and fourth storage regions are respectively adjacent to lower and upper portions at the other side of the same. The second and third storage regions are regarded as a top storage region. When the top storage region is programmed, a first positive voltage is applied to the word line, a second positive voltage is applied to a top bit line in a top portion of the protruding part, and a bottom voltage is applied to first and second bottom bit lines in the substrate beside the protruding part respectively. | 10-20-2011 |
| 20110255349 | METHOD OF OPERATING NON-VOLATILE MEMORY CELL - A method of operating a memory cell for 3D array of this invention is described as follows. Carriers of a first type are injected into a charge storage layer of the memory cell by applying a double-side biased (DSB) voltage to double sides of the memory cell. Carriers of a second type are injected into the charge storage layer by applying FN voltages. | 10-20-2011 |
| 20110250729 | METHOD FOR FABRICATING MEMORY - A method for fabricating a memory is described. Word lines are provided in a first direction. Bit lines are provided in a second direction. A top electrode is formed connecting to a corresponding word line. A bottom electrode is formed connecting to a corresponding bit line. A resistive layer is formed on the bottom electrode. At least two separate L-shaped liners are formed, wherein each L-shaped liner has variable resistive materials on both ends of the L-shaped liner and each L-shaped liner is coupled between the top electrode and the resistive layer. | 10-13-2011 |
| 20110242891 | OPERATION METHODS FOR MEMORY CELL AND ARRAY FOR REDUCING PUNCH THROUGH LEAKAGE - A method for programming a first memory cell in a memory array. In a specific embodiment, each memory cell has a drain, a source, a channel, and a control gate overlying a charge storage material and the channel. The source of the first memory cell is coupled to the drain of a second memory cell. A voltage is applied to the drain of the first memory cell, and the source of the second memory cell is grounded. The method includes floating the drain of the second memory cell and the source of the first memory cell and turning on the channels of the first and second memory cells, effectively forming an extended channel region. Hot carriers are injected to the charge storage material of the first cell to program the first memory cell. The extended channel lowers electrical fields and reduces punch through leakage in unselected memory cells. | 10-06-2011 |
| 20110242874 | RESISTIVE MEMORY AND METHOD FOR CONTROLLING OPERATIONS OF THE SAME - A resistive memory and a method for controlling operations of the resistive memory are provided. The resistive memory has a first memory layer, a second memory layer and a medium layer. Each of the first memory layer and the second memory layer is used to store data. The medium layer is formed between the first memory layer and the second memory layer. The method comprises at least a step of measuring a resistance between the first memory layer and the second memory layer, and determining which one of a first state, a second state and a third state is a state of the resistive memory according to the measured resistance. | 10-06-2011 |
| 20110241100 | STACKED NON-VOLATILE MEMORY DEVICE AND METHODS FOR FABRICATING THE SAME - A stacked non-volatile memory device comprises a plurality of bit line and word line layers stacked on top of each other. The bit line layers comprise a plurality of bit lines that can be formed using advanced processing techniques making fabrication of the device efficient and cost effective. The device can be configured for NAND operation. | 10-06-2011 |
| 20110241078 | Stacked Bit Line Dual Word Line Nonvolatile Memory - An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics. | 10-06-2011 |
| 20110241077 | INTEGRATED CIRCUIT 3D MEMORY ARRAY AND MANUFACTURING METHOD - A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable element and a rectifier. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection. | 10-06-2011 |
| 20110238939 | MEMORY DEVICES WITH DATA PROTECTION - A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit. | 09-29-2011 |
| 20110230024 | METHOD FOR MANUFACTURING NON-VOLATILE MEMORY - A method for manufacturing a non-volatile memory is provided. The method comprises steps of providing a substrate. Thereafter, a plurality of first doped regions are formed in the substrate and then a plurality of trenches are formed in a portion of the first doped regions. A plurality of second doped regions are formed in a portion of the substrate under the bottoms of the trenches respectively. Then, a charge storage layer is formed conformal to a surface of the substrate and a conductive layer is formed over the substrate, wherein the conductive layer covers the charge storage layer and fills in the trenches. | 09-22-2011 |
| 20110227552 | Apparatus of Supplying Power and Method Therefor - A power supply apparatus and a method for supplying power are provided. The apparatus, for use in a system having a first power signal, includes an assistance unit and a power supply device. The assistance unit outputs at least one maintaining signal according to the first power signal selectively. The power supply device outputs a second power signal, wherein the power supply device maintains the second power signal according to the at least one maintaining signal, for example, in an inactive state, such as an idle or standby state or other suitable timing. | 09-22-2011 |
| 20110220986 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device including a substrate, a conductive layer, a charge storage layer, first and second dopant regions and first and second cell dopant regions is provided. A plurality of trenches is deployed in the substrate. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The first and second dopant regions having a first conductive type are configured in the substrate under bottoms of the trenches and in an upper portion of the substrate between two adjacent trenches, respectively. The first and second cell dopant regions having a second conductive type are configured in the substrate between lower portions of side surfaces of the trenches and in the substrate adjacent to the bottoms of the second dopant regions, respectively. The first and the second conductive types are different dopant types. | 09-15-2011 |
| 20110217818 | PHASE CHANGE MEMORY CELL HAVING VERTICAL CHANNEL ACCESS TRANSISTOR - A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. | 09-08-2011 |
| 20110216601 | CURRENT SINK SYSTEM BASED ON SAMPLE AND HOLD FOR SOURCE SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to a magnitude of an operating voltage between first and second nodes. During a first time interval, the operating voltage is set in response to a magnitude of the reference current using a feedback path. During a second time interval following the first time interval, the operating voltage is held independent of the feedback path. The data value stored in the memory cell is determined based on a difference in current between the read current and the sink current during the second time interval. | 09-08-2011 |
| 20110210776 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 09-01-2011 |
| 20110204447 | ESD TOLERANT I/O PAD CIRCUIT INCLUDING A SURROUNDING WELL - An electrostatic discharge tolerant device includes a semiconductor body having a first conductivity type, and a pad. A surrounding well having a second conductivity type is laid out in a ring to surround an area for an electrostatic discharge circuit in the semiconductor body. The surrounding well is relatively deep, and in addition to defining the area for the electrostatic discharge circuit, provides the first terminal of a diode formed with the semiconductor body. Within the area surrounded by the surrounding well, a diode coupled to the pad and a transistor coupled to the voltage reference are connected in series and form a parasitic device in the semiconductor body. | 08-25-2011 |
| 20110204441 | LOW ON-RESISTANCE LATERAL DOUBLE-DIFFUSED MOS DEVICE - A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region. | 08-25-2011 |
| 20110198698 | BIT LINE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device including a substrate, a plurality of stacked gate structures, a plurality of doped regions, a plurality of liner layers, a plurality of conductive layers, a plurality of dielectric layers and a plurality of word lines is provided. The substrate has a plurality of trenches therein. The stacked gate structures are on the substrate between the trenches. The doped regions are in the substrate at sidewalls or bottoms of the trenches. The liner layers are on at least a portion of sidewalls of the stacked gate structures and on sidewalls of the trenches. The conductive layers are in the trenches and electrically connected to the doped regions. The dielectric layers are on the conductive layers and between the stacked gate structures. The word lines are on the substrate and electrically connected to the stacked gate structures. | 08-18-2011 |
| 20110198686 | NITRIDE READ ONLY MEMORY DEVICE WITH BURIED DIFFUSION SPACERS AND METHOD FOR MAKING THE SAME - A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described. | 08-18-2011 |
| 20110198557 | METHOD FOR FABRICATION OF CRYSTALLINE DIODES FOR RESISTIVE MEMORIES - The present invention, in one embodiment, provides a method of producing a PN junction the method including at least the steps of providing a Si-containing substrate; forming an insulating layer on the Si-containing substrate; forming a via through the insulating layer to expose at least a portion of the Si-containing substrate; forming a seed layer of the exposed portion of the Si containing substrate; forming amorphous Si on at least the seed layer; converting at least a portion of the amorphous Si to provide crystalline Si; and forming a first dopant region abutting a second dopant region in the crystalline Si. | 08-18-2011 |
| 20110191728 | INTEGRATED CIRCUIT HAVING LINE END CREATED THROUGH USE OF MASK THAT CONTROLS LINE END SHORTENING AND CORNER ROUNDING ARISING FROM PROXIMITY EFFECTS - An integrated circuit that includes a line end created through use of a mask that controls line end shortening and corner rounding arising from proximity effects is provided. The mask includes a main feature having opaque and transmissive areas arranged to reflect a patterned feature of the line end, at least one of an opaque edge or a transmissive edge located at each end of the main feature, wherein the opaque edge has a set of transmissive assist features arranged therein such that the set of transmissive assist features align alternately with the transmissive areas of the main feature, and the transmissive edge has a set of opaque assist features arranged therein such that the set of opaque assist features align alternately with the opaque areas of the main feature. | 08-04-2011 |
| 20110189836 | ION/IOFF IN SEMICONDUCTOR DEVICES BY UTILIZING THE BODY EFFECT - A method for reducing leakage current of a semiconductor device includes supplying a substantially constant and non-zero bulk bias to a relatively low threshold voltage semiconductor device during formation of a conductive channel of the semiconductor device and during the formation of a non-conductive channel of the semiconductor device. | 08-04-2011 |
| 20110189819 | Resistive Memory Structure with Buffer Layer - A memory device comprises first and second electrodes with a memory element and a buffer layer located between and electrically coupled to them. The memory element comprises one or more metal oxygen compounds. The buffer layer comprises at least one of an oxide and a nitride. Another memory device comprises first and second electrodes with a memory element and a buffer layer, having a thickness of less than 50 Å, located between and electrically coupled to them. The memory comprises one or more metal oxygen compounds. An example of a method of fabricating a memory device includes forming first and second electrodes. A memory, located between and electrically coupled to the first and the second electrodes, is formed; the memory comprises one or more metal oxygen compounds and the buffer layer comprises at least one of an oxide and a nitride. | 08-04-2011 |
| 20110182123 | FLASH MEMORY AND MANUFACTURING METHOD AND OPERATING METHOD THEREOF - A flash memory and a manufacturing method and an operating method thereof are provided. The flash memory includes a substrate, a charge-trapping structure, a first gate, a second gate, a third gate, a first doped region and a second doped region. The substrate has a protrusion portion. The charge-trapping structure is disposed over the substrate. The first gate and the second gate are disposed respectively over the charge-trapping structure at two sides of the protrusion portion. The top surfaces of the first gate and the second gate are lower than the top surface of the charge-trapping structure located on the top of the protrusion portion. The third gate is disposed over the charge-trapping structure located on the top of the protrusion portion. The first doped region and the second doped region are disposed respectively in the substrate at two sides of the protrusion portion. | 07-28-2011 |
| 20110180864 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions. | 07-28-2011 |
| 20110180775 | PROGRAMMABLE METALLIZATION CELL WITH ION BUFFER LAYER - A programmable metallization device, comprises a first electrode; a memory layer electrically coupled to the first electrode and adapted for electrolytic formation and destruction of a conducting bridge therethrough; an ion-supplying layer containing a source of ions of a first metal element capable of diffusion into and out of the memory layer; a conductive ion buffer layer between the ion-supplying layer and the memory layer, and which allows diffusion therethrough of said ions; and a second electrode electrically coupled to the ion-supplying layer. Circuitry is coupled to the device to apply bias voltages to the first and second electrodes to induce creation and destruction of conducting bridges including the first metal element in the memory layer. The ion buffer layer can improve retention of the conducting bridge by reducing the likelihood that the first metallic element will be absorbed into the ion supplying layer. | 07-28-2011 |
| 20110176378 | Memory Program Discharge Circuit - A memory integrated circuit has an array of nonvolatile memory cells, bit lines accessing the array of nonvolatile memory cells, and bit line discharge circuitry. The bit lines have multiple discharge paths for a bit line at a same time, during a program operation. | 07-21-2011 |
| 20110175203 | INTEGRATED CIRCUIT WITH IMPROVED INTRINSIC GETTERING ABILITY - An integrated circuit with improved intrinsic gettering ability is described, having a bulk micro-defect (BMD) density of 3.85×10 | 07-21-2011 |
| 20110175050 | Metal Oxide Resistance Based Semiconductor Memory Device With High Work Function Electrode - Various aspect are directed to a memory device or memory cell with a metal-oxide memory element arranged in electrical series along a current path between at least a first electrode, a metal-oxide memory element adjacent to the first electrode, and a second electrode. The first electrode comprises an electrode material having a first work function. The metal-oxide memory element comprises a metal-oxide material having a second work function. The first work function is greater than the second work function. Thermionic emission characterizes the current through this memory. | 07-21-2011 |
| 20110173512 | MEMORY AND METHOD FOR CHECKING READING ERRORS THEREOF - A method for checking reading errors of a memory includes the following steps. A first data fragment is received. A first count index according to the first data fragment is generated, wherein the first count index is corresponding to a quantity of one kind of binary value in the first data fragment. The first data fragment is written into the memory. The first data fragment is read from the memory as a second data fragment. A second count index is generated according to the second data fragment. The first count index is compared with the second count index. | 07-14-2011 |
| 20110170351 | Memory Cell Array of Memory - A memory cell array of a memory comprises a main memory cell array, including local bit lines, word lines and memory cells, and a selected array, including a global bit line, a bit line transistor (BLT) control line, a transistor and a fixed value memory cell. The local bit lines comprise first and second local bit lines. Each memory cell for storing data corresponds and is connected to one local bit line and one word line. The transistor is coupled to the global bit line, first local bit line and BLT control line, and selectively turns on to connect the global bit line to the first local bit line. The fixed value memory cell coupled to the global bit line, second local bit line, and BLT control line is programmed to a fixed value so that a threshold voltage thereof is greater than a threshold voltage of the transistor. | 07-14-2011 |
| 20110169175 | OVERLAY MARK - An overlay mark is used in pattern registration on a semiconductor wafer with an oxide layer. Four sets of two trenches each are formed in the oxide layer. Each trench in a set is parallel to the other trench of the same set. The trenches are configured such that each set forms one side of a box shape. | 07-14-2011 |
| 20110165753 | Method for Making Self Aligning Pillar Memory Cell Device - A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed. | 07-07-2011 |
| 20110164461 | Memory Device - A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals. | 07-07-2011 |
| 20110163288 | Manufacturing Method for Pipe-Shaped Electrode Phase Change Memory - A method for manufacturing a memory cell device includes forming a bottom electrode comprising a pipe-shaped member, a top, a bottom and sidewalls having thickness in a dimension orthogonal to the axis of the pipe-shaped member, and having a ring-shaped top surface. A disc shaped member is formed on the bottom of the pipe-shaped member having a thickness in a dimension coaxial with the pipe-shaped member that is not dependent on the thickness of the sidewalls of the pipe-shaped member. A layer of phase change material is deposited in contact with the top surface of the pipe-shaped member. A top electrode in contact with the layer of programmable resistive material. An integrated circuit including an array of such memory cells is described. | 07-07-2011 |
| 20110161750 | Pre-Code Device, and Pre-Code System and Pre-Coding Method Thereof - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 06-30-2011 |
| 20110161718 | Command Decoding Method and Circuit of the Same - A decoding circuit for decoding a command is provided. The received command is transmitted during at least two clock periods of a clock signal, and the received command is divided to a former encoded data and a latter encoded data. The decoding circuit includes a pre-trigger signal generating unit, a comparing unit, and a starting signal generating unit. The pre-trigger signal generating unit receives the former encoded data and generates a pre-trigger signal when the former encoded data of the received command matches the corresponding former encoded data of a predetermined command. The comparing unit generates a match signal when the latter encoded data of the received command is the same with the latter encoded data of the predetermined command. The starting signal generating unit outputs a starting signal according to the pre-trigger signal and the match signal. The starting signal starts a corresponding operation of the predetermined command. | 06-30-2011 |
| 20110159682 | METHODS OF MANUFACTURING MEMORY DEVICES - A method of manufacturing a memory device is disclosed. The method includes providing a substrate, forming a number of memory sectors on the substrate, wherein each of the memory sectors is coupled to an adjacent one via a first diffused region in the substrate and is coupled to another adjacent one via at least one second diffused region in the substrate, forming a first dielectric layer on the memory sectors, forming a first conductive structure through the first dielectric layer to the first diffused region, and at least one second conductive structure through the first dielectric layer to the at least one second diffused region, forming a patterned first mask layer on the first dielectric layer, the first conductive structure and the at least one second conductive structure, the patterned first mask layer exposing the first conductive structure, and etching back the first conductive structure. | 06-30-2011 |
| 20110157986 | MEMORY AND OPERATING METHOD THEREOF - A memory and an operating method thereof are provided therein. When searching a boundary of a threshold voltage distribution of the memory, data errors resulted from tail bits of the memory would be corrected. Therefore, a sensing window could be broader, and the boundary of the threshold voltage distribution could be determined precisely. | 06-30-2011 |
| 20110156259 | METAL-TO-CONTACT OVERLAY STRUCTURES AND METHODS OF MANUFACTURING THE SAME - The present invention provides a semiconductor device with a metal-to-contact overlay structure. The semiconductor device includes a substrate, a dielectric layer on the substrate, a contact coupled to the substrate in the dielectric layer, a first conductive region on the contact in the dielectric layer, a dielectric sidewall on the contact in the dielectric layer, the dielectric sidewall surrounding the first conductive region, and a second conductive region on the first conductive region on the dielectric layer. | 06-30-2011 |
| 20110156102 | MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line. | 06-30-2011 |
| 20110149675 | Local Word Line Driver - A two transistor word line driver is disclosed. An example disclosed word line driver is simplified with common signals on the gates of the p-type and the n-type transistors. An example disclosed word line driver consumes less power by applying a negative voltage to a word line driver selected from multiple word line drivers. | 06-23-2011 |
| 20110149671 | Operation Method and Leakage Controller for a Memory and a Memory Applying the Same - An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step. | 06-23-2011 |
| 20110149669 | Sense Amplifier and Data Sensing Method Thereof - A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node. | 06-23-2011 |
| 20110140193 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a non-volatile memory and a method of manufacturing the same are provided. The semiconductor device includes a base material and a stack structure. The stack structure disposed on the base material at least includes a tunneling layer, a trapping layer and a dielectric layer. The trapping layer is disposed on the tunneling layer. The dielectric layer has a dielectric constant and is disposed on the trapping layer. The dielectric layer is transformed from a first solid state to a second solid state when the dielectric layer undergoes a process. | 06-16-2011 |
| 20110138216 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
| 20110138213 | Clock Integrated Circuit - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
| 20110133814 | TX OUTPUT COMBINING METHOD BETWEEN DIFFERENT BANDS - An output buffer includes a first output transistor, a first switch, a second switch and a third switch. The first output transistor is connected to a first operational voltage for outputting the first operational voltage as the data signal. The first switch is connected to a bulk of the first output transistor for receiving an enable signal. The second switch is connected to the first switch and a second operational voltage for receiving the enable signal, wherein the second operational voltage is lower than the first operational voltage. The third switch includes a first terminal connected to the bulk of the first output transistor, a control terminal connected to the first switch, and a second terminal connected to the first operational voltage. | 06-09-2011 |
| 20110133804 | CLOCK INTEGRATED CIRCUIT - The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more of the variations in temperature, ground noise, and power noise. | 06-09-2011 |
| 20110133150 | Phase Change Memory Cell with Filled Sidewall Memory Element and Method for Fabricating the Same - Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically coupling the bottom electrode to the top electrode. The memory element has an outer surface contacting a dielectric sidewall spacer that is on the sidewall of the via, and comprises a stem portion on the bottom electrode and a cup portion on the stem portion. A fill material is within an interior defined by an inner surface of the cup portion of the memory element. | 06-09-2011 |
| 20110128809 | Method and Apparatus of Addressing A Memory Integrated Circuit - A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes. | 06-02-2011 |
| 20110128791 | Method and Apparatus of Performing an Erase Operation on a Memory Integrated Circuit - Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines. | 06-02-2011 |
| 20110122721 | Y-Decoder and Decoding Method Thereof - A Y-decoder includes a selection unit and a Y-MUX. The selection unit is coupled to the memory array for selecting the column lines. The Y-MUX is coupled to the selection unit for supplying a voltage to the selected column line. The Y-MUX includes a first switch, a second switch, a third switch and a fourth switch coupled in parallel. The first switch and the second switch are respectively for receiving a first shielding voltage and a second shielding voltage. The third switch and the fourth switch are respectively for receiving a first sensing voltage and a second sensing voltage. | 05-26-2011 |
| 20110122690 | METHOD FOR PROGRAMMING MULTI-LEVEL CELL AND MEMORY APPARATUS - A method for programming a multi-level cell and a memory apparatus are described, wherein each cell has two storage sites. The method includes making the first storage site have a first Vt level and the second storage site have a second Vt level. The first Vt level is selected from M Vt levels. When the first Vt level is the i-th level among the M Vt levels, the second Vt level is selected from n | 05-26-2011 |
| 20110121411 | THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING AND OPERATING THE SAME - The invention provides a semiconductor cell comprising a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region. | 05-26-2011 |
| 20110121253 | MEMORY DEVICE - A memory device is described. The memory device comprises a bottom electrode, a first pair of spacers, a second pair of spacers and a phase-change element. The bottom electrode has a lower horizontal portion and a vertical portion, and the vertical portion has a top surface and a side. The first pair of spacers covers the side of the vertical portion. The second pair of spacers covers a first portion of the top surface of the vertical portion. The phase-change element is contacted a second portion of the top surface of the vertical portion. | 05-26-2011 |
| 20110116317 | PROGRAM AND ERASE METHODS WITH SUBSTRATE TRANSIENT HOT CARRIER INJECTIONS IN A NON-VOLATILE MEMORY - The present invention describes a uniform program method and a uniform erase method of a charge trapping memory by employing a substrate transient hot electron technique for programming, and a substrate transient hot hole technique for erasing, which emulate an FN tunneling method for NAND memory operation. The methods of the present invention are applicable to a wide variety of charge trapping memories including n-channel or p-channel SONOS types of memories and floating gate (FG) type memories. the programming of the charge trapping memory is conducted using a substrate transient hot electron injection in which a body bias voltage Vb has a short pulse width and a gate bias voltage Vg has a pulse width that is sufficient to move electrons from a channel region to a charge trapping structure. | 05-19-2011 |
| 20110116309 | Refresh Circuitry for Phase Change Memory - A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array. | 05-19-2011 |
| 20110116308 | MULTIPLE PHASE CHANGE MATERIALS IN AN INTEGRATED CIRCUIT FOR SYSTEM ON A CHIP APPLICATION - An integrated circuit includes a plurality of memory cells on a substrate, in which a first set of memory cells uses a first memory material, and a second set of memory cells uses a second memory material. The first and second memory materials have different properties such that the first and second sets of memory cells have different operational memory characteristics, such as switching speeds, retention and endurance. | 05-19-2011 |
| 20110115551 | CHARGE PUMP UTILIZING EXTERNAL CLOCK SIGNAL - A method of generating a pumping voltage in an integrated circuit includes receiving an external clock signal from outside of the integrated circuit. The frequency of the received external clock signal is changed according to one or more modulation ratios, resulting in one or more respective modulated external clock signal. The external clock signal or one of the modulated external clock signals is then selected for use as a pump clock signal. The pump clock signal is used for driving the pump capacitance of a pump circuit for generating the pumping voltage. | 05-19-2011 |
| 20110108792 | Single Crystal Phase Change Material - A method for fabricating a phase change memory (PCM) cell includes forming a dielectric layer over an electrode, the electrode comprising an electrode material; forming a via hole in the dielectric layer such that the via hole extends down to the electrode; and growing a single crystal of a phase change material on the electrode in the via hole. A phase change memory (PCM) cell includes an electrode comprising an electrode material; a dielectric layer over the electrode; a via hole in the dielectric layer; and a single crystal of a phase change material located in the via hole, the single crystal contacting the electrode at the bottom of the via hole. | 05-12-2011 |
| 20110104881 | METHOD OF REDUCING WORDLINE SHORTING - A method of fabricating a memory device includes providing a substrate having an insulating layer, forming first, second, and third conductive layers on the insulating layer, forming a mask on the third conductive layer, etching through the third conductive layer and a first portion thickness of the second conductive layer using the mask to provide an etched sidewall portions of the third conductive layer and an etched upper surface of the second polysilicon layer, and forming a liner layer along the etched sidewall portions and the etched upper surface. | 05-05-2011 |
| 20110097825 | Methods For Reducing Recrystallization Time for a Phase Change Material - A method for reducing recrystallization time for a phase change material of a memory cell element in conjunction with the manufacture of a memory cell device can be carried out as follows. A phase change material, a buffer layer material and a cladding layer material are selected. The buffer layer material is deposited on the substrate, the phase change material is deposited on the buffer layer, and the cladding layer material is deposited on the phase change material to form a memory cell element. The thickness of the phase change material is preferably less than 30 nm and more preferably less than 10 nm. The recrystallization time of the phase change material of the memory cell element is determined. If the recrystallization time is not less than a length of time X, these steps are repeated while changing at least one of the selected materials and material thicknesses. | 04-28-2011 |
| 20110095353 | ONE-TRANSISTOR CELL SEMICONDUCTOR ON INSULATOR RANDOM ACCESS MEMORY - Silicon-oxide-nitride-oxide-silicon SONOS-type devices (or BE-SONOS) fabricated in Silicon-On-Insulator (SOI) technology for nonvolatile implementations. An ultra-thin tunnel oxide can be implemented providing for very fast program/erase operations, supported by refresh operations as used in classical DRAM technology. The memory arrays are arranged in divided bit line architectures. A gate injection, DRAM cell is described with no tunnel oxide. | 04-28-2011 |
| 20110089578 | WAFER STRUCTURE - A wafer structure includes a plurality of dies, an edge portion, a passivation layer, and a UV-blocking metal layer. Each of the dies having an integrated circuit formed thereon, and the circuit includes an upmost metal layer that includes bonding pads. A composite dielectric layer corresponding to dielectric layers of the integrated circuit is disposed on the edge portion, and a cavity is formed in the composite dielectric layer over the edge portion. The passivation layer is located over the whole wafer and covers the upmost metal layer. The UV-blocking metal layer is located on the passivation layer and covers the edge portion and at least a portion of each of the dies. The cavity, the passivation layer, and the UV-blocking metal layer result in an alignment mark. | 04-21-2011 |
| 20110089480 | MEMORY AND MANUFACTURING METHOD THEREOF - A memory having isolated dual memory cells is provided. A first isolation wall and a second isolation wall are separately disposed between a source and a drain on a substrate. An isolation bottom layer and a polysilicon layer are orderly disposed on the substrate between the first and the second isolation walls. A first charge storage structure and a first gate are orderly disposed on the substrate between the first isolation wall and the source. A second charge storage structure and a second gate are orderly disposed on the substrate between the second isolation wall and the drain. A word line disposed on the polysilicon layer, the first gate, the second gate, the first isolation wall and the second isolation wall is electrically connected to the first gate, the second gate and the polysilicon layer. | 04-21-2011 |
| 20110089393 | Memory and Method of Fabricating the Same - A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal element, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance. | 04-21-2011 |
| 20110087838 | Memory Device and Operation Method Therefor - Provided is a MLC (Multi-level cell) memory device, comprising: a memory array, including a plurality of groups each storing a plurality of bits; and an inverse bit storage section, storing a first inverse bit data including a plurality of inverse bits, the plurality of bits in the same group in the memory array being related to a respective inverse bit. | 04-14-2011 |
| 20110086482 | APPARATUS AND ASSOCIATED METHOD FOR MAKING A FLOATING GATE CELL WITH INCREASED OVERLAY BETWEEN THE CONTROL GATE AND FLOATING GATE - A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design. | 04-14-2011 |
| 20110085384 | CURRENT SINK SYSTEM FOR SOURCE-SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 04-14-2011 |
| 20110085383 | CURRENT SINK SYSTEM FOR SOURCE SIDE SENSING - Source-side sensing techniques described herein determine the data value stored in a memory cell based on the difference in current between the read current from the source terminal of the memory cell and a sink current drawn from the read current. The sink current is drawn in response to the magnitude of a reference current provided by a reference current source such as a reference cell. | 04-14-2011 |
| 20110085380 | Method of Programming a Memory - A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an n | 04-14-2011 |
| 20110085378 | Memory and Operation Method Therefor - In an operation method for a memory including a plurality of memory cells, a first reading is performed on the memory cells by applying a reference voltage; the reference voltage is moved if it is checked that the first reading result is not correct; a second reading is performed on the memory cells by applying the moved reference voltage; a first total number of a first logic state in the first reading is compared with a second total number of the first logic state in the second reading if it is checked that the second reading result is not correct; and the moving of the reference voltage is stopped if the first reading result has the same number of the first logic state as the second reading result, and the moved reference voltage is stored as a target reference voltage. | 04-14-2011 |
| 20110084397 | 3D INTEGRATED CIRCUIT LAYER INTERCONNECT - A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided. | 04-14-2011 |
| 20110080784 | NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF - An operation method of a non-volatile memory suitable for a multi-level cell having a first storage position and a second storage position is provided. The operation method includes: setting N threshold-voltage distribution curves, wherein the N threshold-voltage distribution curves correspond to N levels and N is an integer greater than 2; programming the first and the second storage positions to the 1 | 04-07-2011 |
| 20110080780 | Method for Programming a Multilevel Phase Change Memory Device - A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level. | 04-07-2011 |
| 20110080766 | Resistive Memory Device and Manufacturing Method Thereof and Operating Method Thereof - A method of manufacturing resistive memory includes the steps: forming a first implanted stacked structure having a first impurity diffusion layer, a second impurity diffusion layer, and a third impurity diffusion layer in a substrate; etching at least the first implanted stacked structure to form a plurality of second implanted stacked structures, wherein the first impurity diffusion layers are first signal lines; forming a plurality of first insulating layers between the second implanted stacked structures; etching the second implanted stacked structures to form a plurality of third implanted stacked structures, wherein the first signal lines are not etched; forming a plurality of second insulating layers between the third implanted stacked structures; forming a plurality of memory material layers electrically coupled to the third impurity diffusion layers; and forming a plurality of second signal lines perpendicular to the first signal lines and electrically coupled to the memory material layers. | 04-07-2011 |
| 20110079840 | MEMORY CELL AND MANUFACTURING METHOD THEREOF AND MEMORY STRUCTURE - A memory cell is provided. The memory cell includes a substrate, an isolation layer, a gate, a charge storage structure, a first source/drain region, a second source/drain region and a channel layer. The isolation layer is disposed over the substrate. The gate is disposed over the isolation layer. The charge storage structure is disposed over the isolation layer and the gate. The first source/drain region is disposed over the charge storage structure at two sides of the gate. The second source/drain region is disposed over the charge storage structure at top of the gate. The channel layer is disposed over the charge storage structure at sidewall of the gate and is electrically connected with the first source/drain region and the second source/drain region. | 04-07-2011 |
| 20110076825 | Method for Making a Self Aligning Memory Device - A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width. | 03-31-2011 |
| 20110075486 | CHARGE TRAPPING MEMORY CELL HAVING BANDGAP ENGINEERED TUNNELING STRUCTURE WITH OXYNITRIDE ISOLATION LAYER - A band gap engineered, charge trapping memory cell includes a charge storage structure including a trapping layer. a blocking layer, and a dielectric tunneling structure including a thin tunneling layer, a thin bandgap offset layer and a thin isolation layer comprising silicon oxynitride. The memory cell is manufactured using low thermal budget processes. | 03-31-2011 |
| 20110074030 | METHOD FOR PREVENTING Al-Cu BOTTOM DAMAGE USING TiN LINER - A semiconductor device and related method for fabricating the same include providing a stacked structure including an insulating base layer and lower and upper barrier layers with a conductive layer in between, etching the stacked structure to provide a plurality of conductive columns that each extend from the lower barrier layer, each of the conductive columns having an overlying upper barrier layer cap formed from the etched upper barrier layer, wherein the lower barrier layer is partially etched to provide a land region between each of the conductive lines, forming a liner layer over the etched stacked structure exposing the land region, and etching the liner layer and removing the exposed land region to form a plurality of conductive lines | 03-31-2011 |
| 20110073937 | Method for Fabricating a Charge Trapping Memory Device - A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer. | 03-31-2011 |
| 20110069571 | Word Line Decoder Circuit Apparatus and Method - One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation. | 03-24-2011 |
| 20110069538 | MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE - A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse. | 03-24-2011 |
| 20110068837 | APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER - An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch. | 03-24-2011 |
| 20110068418 | SUBSTRATE SYMMETRICAL SILICIDE SOURCE/DRAIN SURROUNDING GATE TRANSISTOR - Field effect transistors described herein include first and second terminals vertically separated by a channel region. The first and second terminals comprise first and second silicide elements respectively. The first silicide element prevents the migration of carriers from the first terminal into the underlying semiconductor body or adjacent devices which can activate parasitic devices. The first silicide element is also capable of acting as a low resistance conductive line for interconnecting devices or elements. The second silicide element provides a low resistance contact between the second terminal and overlying elements. | 03-24-2011 |
| 20110063902 | 2T2R-1T1R MIX MODE PHASE CHANGE MEMORY ARRAY - A memory device as described herein includes an array of programmable resistance memory cells. The memory device further includes sense circuitry having a dual memory cell (2T-2R) mode to read a data value stored in a pair of memory cells in the array based on a difference in resistance between a first memory cell in the pair and a second memory cell in the pair. The sense circuitry also has a single memory cell (1T-1R) mode to read a data value in a particular memory cell in the array based on the resistance of the particular memory cell. | 03-17-2011 |
| 20110062507 | SEMICONDUCTOR DEVICE AND A METHOD OF FABRICATING THE SAME - A semiconductor device is provided. The semiconductor device includes a memory device, and the memory device includes a substrate, two stacked gates, two spacers, an insulating layer, and a dielectric layer. The stacked gates having a gap therebetween are located on the substrate. The spacers having a pipe or a seam therebetween are respectively located at sidewalls of each of the stacked gates in the gap. The pipe or the seam is filled with the insulating layer. The dielectric layer is located on the substrate and covers the insulating layer and the stacked gates. | 03-17-2011 |
| 20110060962 | Method and Apparatus for Accessing Memory With Read Error By Changing Comparison - In response to a disagreement between a previously generated check code associated with previously programmed data bits and a more recently generated check code generated in response to a read command, the comparison process is changed, between i) a value representing accessed data and ii) a reference applied to such accesses to distinguish between logical levels. For example, the ratio of resistances characterizing input circuits of a sense amplifier and/or the read bias arrangement and/or a read reference of a memory integrated circuit is/are changed. | 03-10-2011 |
| 20110058430 | Voltage Regulation Method and Memory Applying Thereof - A voltage regulating method applied to a memory to regulate a word line voltage corresponding to a set of memory cells of the memory comprises the following steps. Firstly, a first value, which is for indicating an amount of data having a specific data value in a set of written data, is counted, wherein the set of written data is written into the set of memory cells. Next, a second value, which is for indicating an amount of data having the specific data value in a set of read data, is counted, wherein the set of read data is obtained by reading the set of written data. Then, a regulating voltage is determined according to a difference between the first and second values. After that, the word line voltage is regulated to be a sum of the word line voltage and the regulating voltage. | 03-10-2011 |
| 20110058414 | MEMORY WITH MULTIPLE REFERENCE CELLS - A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels. | 03-10-2011 |
| 20110056432 | CONTACT BARRIER LAYER DEPOSITION PROCESS - A method for depositing a barrier layer onto a substrate is disclosed. A layer of titanium (Ti) is deposited onto the substrate using an ionized metal plasma (IMP) physical vapor deposition process. The IMP process includes: generating gaseous ions, accelerating the gaseous ions towards a titanium target, sputtering the titanium atoms from the titanium target with the gaseous ions, ionizing the titanium atoms using a plasma, and depositing the ionized titanium atoms onto the substrate to form the layer of Ti. A first layer of titanium nitride (TiN) is deposited onto the layer of Ti using a metal organic chemical vapor deposition (MOCVD) process. A second layer of TiN is deposited onto the first layer of TiN using a thermal chemical vapor deposition process. The newly completed barrier layer is annealed in the presence of nitrogen at a temperature of between about 500° C. to about 750° C. | 03-10-2011 |
| 20110055670 | Programming Method and Memory Device Using the Same - A programming method applied to a memory is provided. The memory includes a number of memory cells. The method includes the following steps. A target cell of the memory cells is programmed in response to a first programming command. The target cell is programmed in response to a second programming command. | 03-03-2011 |
| 20110053328 | METHOD FOR MANUFACTURING MEMORY CELL - In a method for manufacturing a memory cell, a substrate is provided. A doped region with a first conductive type is formed in the substrate near a surface of the substrate. A portion of the substrate is removed to define a plurality of fin structures in the substrate. A plurality of isolation structures is formed among the fin structures. A surface of the isolation structures is lower than a surface of the fin structures. A gate structure is formed over the substrate and straddles the fin structure. The gate structure includes a gate straddling the fin structure and a charge storage structure located between the fin structure and the gate. A source/drain region is formed with a second conductive type in the fin structure exposed by the gate structure, and the first conductive type is different from the second conductive type. | 03-03-2011 |
| 20110051525 | POWER SAVING METHOD AND CIRCUIT THEREOF FOR A SEMICONDUCTOR MEMORY - A power saving method for a semiconductor memory is provided. The power saving method for a semiconductor memory including the steps of receiving a plurality of address codes, each of which has a first part code and a second part code; and activating a first boost process when the first part code of a currently received address code is different from the first part code of a last received address code, otherwise a second boost process is activated. | 03-03-2011 |
| 20110049677 | Buried Layer of An Integrated Circuit - Various aspects of the technology are directed to integrated circuit manufacturing methods and integrated circuits. In one method, a first charge type buried layer in a semiconductor material of an integrated circuit by implanting first charge type dopants of the first charge type buried layer through a sacrificial oxide over the semiconductor material and through an intermediate region of the semiconductor material transited by the implanted first charge type dopants. When the implanted dopants pass through the sacrificial oxide, damage to the semiconductor crystalline lattice is averted. If the sacrificial oxide were absent, the implanted dopants would have passed through and damaged the semiconductor crystalline lattice instead. Later, a pre-anneal oxide is grown and removed. | 03-03-2011 |
| 20110049456 | PHASE CHANGE STRUCTURE WITH COMPOSITE DOPING FOR PHASE CHANGE MEMORY - A memory device is described using a composite doped phase change material between a first electrode and a second electrode. A memory element of phase change material, such as a chalcogenide, is between the first and second electrodes and has an active region. The phase change material has a first dopant, such as silicon oxide, characterized by tending to segregate from the phase change material on grain boundaries in the active region, and has a second dopant, such as silicon, characterized by causing an increase in recrystallization temperature of, and/or suppressing void formation in, the phase change material in the active region. | 03-03-2011 |
| 20110044097 | PHASE CHANGE MEMORY AND OPERATION METHOD OF THE SAME - An operation method of phase change memory (PCM) is provided. The operation method includes applying a RESET pulse to a phase change material of the PCM, wherein the RESET pulse has a profile with a first tail such that a plurality of seeds are formed in the phase change material. Due to the design of the RESET pulse in the operation method, it can speed up the crystal process. | 02-24-2011 |
| 20110042738 | NITRIDGE READ-ONLY MEMORY CELL AND METHOD OF MANUFACTURING THE SAME - A nitride read-only memory cell and a method of manufacturing the same are provided. First, a substrate is provided, and a first oxide layer is formed on the substrate. Next, a nitride layer is deposited on the first oxide layer via a first gas and a second gas. The flow ratio of the first gas to the second gas is 2:1. After that, a second oxide layer is formed on the nitride layer. Then, a bit-line region is formed at the substrate. Afterward, a gate is formed on the second oxide layer. The first oxide layer, nitride layer, the second oxide layer and the gate compose a stack structure of the cell. Further, a spacer is formed on the side-wall of the stack structure. | 02-24-2011 |
| 20110039386 | LATERAL POCKET IMPLANT CHARGE TRAPPING DEVICES - A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trapping structure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes. | 02-17-2011 |
| 20110038218 | Memory Chip and Method for Operating the Same - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 02-17-2011 |
| 20110038208 | METHOD OF READING DUAL-BIT MEMORY CELL - A method of reading a dual-bit memory cell includes a controlling terminal, a first terminal, and a second terminal. The dual-bit memory cell has a first bit storage node and a second bit storage node near the first terminal and the second terminal respectively. First, a controlling voltage and a read voltage are applied to the controlling terminal and the first terminal respectively. The second terminal is grounded to measure a first output current value of the first terminal. Then, the controlling voltage and the read voltage are applied to the controlling terminal and the second terminal respectively. The first terminal is grounded to measure a second output current value of the second terminal. Afterward, the bit state of the first bit storage node and the bit state of the second bit storage node is read simultaneously according to the first output current value and the second output current value. | 02-17-2011 |
| 20110034003 | Vacuum Cell Thermal Isolation for a Phase Change Memory Device - A memory device with improved thermal isolation. The memory cell includes a first electrode element, having an upper surface; an insulator stack formed on the first electrode element, including first, second and third insulating members, all generally planar in form and having a central cavity formed therein and extending therethrough, wherein the second insulator member is recessed from the cavity; a phase change element, generally T-shaped in form, having a base portion extending into the cavity to make contact with the first electrode element and making contact with the first and third insulating members, and a crossbar portion extending over and in contact with the third insulating member, wherein the base portion of the phase change element, the recessed portions of the second insulating member and the surfaces of the first and third insulating members define a thermal isolation void; and a second electrode formed in contact with the phase change member. | 02-10-2011 |
| 20110032771 | Memory and Reading Method Thereof - A reading method applied for a memory, which includes a cell row including a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line is provided. The reading method comprises the following steps. Firstly, the first bit line coupled to a first terminal of the first memory cell is selected for reading the first memory cell in a time period. Next, the second terminal of the first memory cell is discharged via the second bit line coupled to the second memory cell in the time period. | 02-10-2011 |
| 20110032770 | High Temperature Methods for Enhancing Retention Characteristics of Memory Devices - Methods are described for improving the retention of a memory device by execution of a retention improvement procedure. The retention improvement procedure comprises a baking process of the memory device in a high temperature environment, a verifying process of the memory device that checks the logic state of memory cells, and a reprogramming process to program the memory device once again by programming memory cells in a 0-state to a high-Vt state. The baking step of placing the memory device in a high temperature environment causes a charge loss by expelling shallow trapped charges, resulting in the improvement of retention reliability. | 02-10-2011 |
| 20110026742 | METHOD OF FABRICATING INTEGRATED SEMICONDUCTOR DEVICE AND STRUCTURE THEREOF - A method of fabricating an integrated semiconductor device, comprising: providing a substrate having a first region and a second region; and forming a semiconductor unit on the first region and forming a micro electro mechanical system (MEMS) unit on the second region in one process. | 02-03-2011 |
| 20110024326 | IC PACKAGE TRAY EMBEDDED RFID - A carrier tray as described herein includes a container having pockets for holding electrical components such as integrated circuits during manufacturing, and a device coupled to the container for tracking usage of the carrier tray into and out of process chambers used for performing particular processes on the electrical components carried therein. Stations and methods of using the carrier tray are also described herein. | 02-03-2011 |
| 20110019487 | APPARATUS AND METHOD FOR DETECTING WORD LINE LEAKAGE IN MEMORY DEVICES - According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line. | 01-27-2011 |
| 20110019473 | MEMORY ARRAY AND METHOD OF OPERATING ONE OF A PLURALITY OF MEMORY CELLS - An embodiment of the invention provides a memory array including a plurality of bit lines, a plurality of memory cells and a device. Each of the plurality of memory cells has a first node, a second node and a third node, wherein the third node is coupled to one of the plurality of bit lines. The device couples the plurality of bit lines together to form a common node for one of the plurality of memory cells. | 01-27-2011 |
| 20110019456 | SENSE AMPLIFIER WITH SHIELDING CIRCUIT - A sense amplifier comprises a sense node, a reference node, a memory input stage circuit, a reference input stage circuit, an output stage circuit, and a shielding circuit. The memory input stage circuit comprises first input node for maintaining a first sense voltage established by a cell current and establishes a second sense voltage on the sense node in response to the first sense voltage. The reference input stage circuit comprises an output node and a second input node, which is for maintaining a first reference voltage established by the reference current and establishes a second reference voltage on the reference node in response to the first reference voltage. The output stage circuit obtains a sense result in response to the second reference voltage and the second sense voltage. The first shielding circuit shields the output node from being interfered with the second reference voltage on the reference node. | 01-27-2011 |
| 20110017970 | SELF-ALIGN PLANERIZED BOTTOM ELECTRODE PHASE CHANGE MEMORY AND MANUFACTURING METHOD - A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers. | 01-27-2011 |
| 20110016370 | MEMORY APPARATUS AND OPERATION METHOD THEREOF - A memory apparatus and an operation method thereof are provided. The memory apparatus includes a plurality of multi-level cells and a controller. The controller encodes input data according to a target encoding code to generate a plurality of encoded subsets, and stores the encoded subsets into the multi-level cells. Thereafter, the controller could read data from the multi-level cells, perform an error correction procedure on the read data to correct and recover the read data as recovered data, and decode the recovered data according to the target encoding code. Consequently, sensing windows between threshold voltage distributions of the multi-level cells are expanded. | 01-20-2011 |
| 20110016291 | Serial Memory Interface for Extended Address Space - An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address. | 01-20-2011 |
| 20110016288 | Serial Flash Memory and Address Transmission Method Thereof - A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock. | 01-20-2011 |
| 20110013462 | Method for Operating Memory - A memory operating method includes the following steps. First, a memory with a charge storage structure is provided. Next, the memory is biased to a first threshold voltage. Then, the memory is biased to a second threshold voltage. Next, the memory is biased to a third threshold voltage. The first threshold voltage is higher than a first level. The second threshold voltage is lower than a second level. The third threshold voltage is approximating or equal to the second level. | 01-20-2011 |
| 20110013446 | REFRESH CIRCUITRY FOR PHASE CHANGE MEMORY - A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array. | 01-20-2011 |
| 20110012192 | Vertical Channel Transistor Structure and Manufacturing Method Thereof - A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate. | 01-20-2011 |
| 20110012084 | RESISTOR RANDOM ACCESS MEMORY CELL WITH REDUCED ACTIVE AREA AND REDUCED CONTACT AREAS - A memory device has a sidewall insulating member with a sidewall insulating member length according to a first spacer layer thickness. A first electrode formed from a second spacer layer having a first electrode length according to a thickness of a second spacer layer and a second electrode formed from the second spacer layer having a second electrode length according to the thickness of the second spacer layer are formed on sidewalls of the sidewall insulating member. A bridge of memory material having a bridge width extends from a top surface of the first electrode to a top surface of the second electrode across a top surface of the sidewall insulating member, wherein the bridge comprises memory material. | 01-20-2011 |
| 20110012083 | PHASE CHANGE MEMORY CELL STRUCTURE - A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface. | 01-20-2011 |
| 20110012079 | THERMAL PROTECT PCRAM STRUCTURE AND METHODS FOR MAKING - A memory cell as described herein includes a conductive contact and a memory element comprising programmable resistance memory material overlying the conductive contact. An insulator element extends from the conductive contact into the memory element, the insulator element having proximal and distal ends and an inside surface defining an interior. The proximal end is adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end. The memory element is within the interior extending downwardly from the distal end to contact a top surface of the bottom electrode at a first contact surface. A top electrode can be separated from the distal end of the insulator element by the memory element and contact the memory element at a second contact surface having a surface area greater than that of the first contact surface. | 01-20-2011 |
| 20110007577 | ACCESSING METHOD AND A MEMORY USING THEREOF - A memory comprises a memory cell, a sense amplifier, and a control unit. The memory cell stores a first bit and a second bit. The sense amplifier senses a first cell current and a second cell current corresponding to the first and the second bits respectively with a voltage applying on the memory cell. The control unit determines a digital state of the first bit by comparing a first reference current with the first cell current or by comparing a reference data with a first delta current between the first cell current and the second cell current. | 01-13-2011 |
| 20110006279 | PHASE CHANGE MEMORY - A phase change memory (PCM) is provided which includes a substrate, a plurality of bottom electrodes, a plurality of top electrodes, a plurality of phase change materials, and a plurality of thermal disturbance-preventing parts. The bottom electrodes are disposed in the substrate, and the top electrodes are disposed on the substrate. The phase change (PC) materials are disposed between the top and bottom electrodes, and each of the PC materials is conducted with one of the top electrodes and one of the bottom electrodes. The thermal disturbance-preventing parts are utilized to reduce the effect of thermal disturbance upon the PCM. | 01-13-2011 |
| 20110003452 | HIGH-k CAPPED BLOCKING DIELECTRIC BANDGAP ENGINEERED SONOS AND MONOS - A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-κ material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used. | 01-06-2011 |
| 20110003446 | Semiconductor Device and Method for Manufacturing the Same - A semiconductor device includes an insulating layer, a channel structure, an insulating structure and a gate. The channel structure includes a channel bridge for connecting two platforms. The bottom of the channel bridge is separated from the insulating layer by a distance, and the channel bridge has a plurality of separated doping regions. The insulating structure wraps around the channel bridge, and the gate wraps around the insulating structure. | 01-06-2011 |
| 20110002166 | TWO-BIT NON-VOLATILE FLASH MEMORY ARRAY - A memory array comprises a semiconductor substrate, two-bit memory cells, word lines, a gate voltage source, bit lines and bit line control cells. The memory cells have a first and a second source/drain regions, each memory cell includes a dielectric trapping layer, and the dielectric trapping layer is disposed between a first oxide layer and a gate layer. The word lines are coupled to the gate layer. The gate voltage source is coupled to the word lines and configured to apply erase voltages between 14 and 20 volts to the word lines. The bit lines are in electrical communication with the first and the second source/drain regions. The bit line control cells are disposed at the beginning and end of each bit line, the bit line control cells are configured to control the electrical communication of each bit line with the first and the second source/drain regions. | 01-06-2011 |
